Tsung-Yi Wu, Tzi-Wei Kao, Shi-Yi Huang, Tai-Lun Li, How-Rern Lin. Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. In Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010. pages 444-449, IEEE, 2010. [doi]
@inproceedings{WuKHLL10,
title = {Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs},
author = {Tsung-Yi Wu and Tzi-Wei Kao and Shi-Yi Huang and Tai-Lun Li and How-Rern Lin},
year = {2010},
doi = {10.1109/ASPDAC.2010.5419842},
url = {http://dx.doi.org/10.1109/ASPDAC.2010.5419842},
tags = {rule-based},
researchr = {https://researchr.org/publication/WuKHLL10},
cites = {0},
citedby = {0},
pages = {444-449},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010},
publisher = {IEEE},
isbn = {978-1-60558-837-7},
}