Kenji Shimazaki - researchr alias

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Viewing Publication 1 - 13 from 13

2010

Gate delay estimation in STA under dynamic power supply noiseTakaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto. aspdac 2010: 775-780 [doi]

Gate Delay Estimation in STA under Dynamic Power Supply NoiseTakaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto. ieicet, 93-A(12):2447-2455, 2010. [doi]

2009

A minimum decap allocation technique based on simultaneous switching for nanoscale SoCKenji Shimazaki, Takaaki Okumura. cicc 2009: 21-24 [doi]

2006

An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC DesignsKenji Shimazaki, Makoto Nagata, Mitsuya Fukazawa, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa. ieicet, 89-C(11):1535-1543, 2006. [doi]

2005

Substrate-noise and random-fluctuations reduction with self-adjusted forward body biasYoshihide Komatsu, Koichiro Ishibashi, Masaharu Yamamoto, Toshiro Tsukada, Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata. cicc 2005: 35-38 [doi]

Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased CircuitsKenji Shimazaki, Makoto Nagata, Takeshi Okumoto, Shozo Hirano, Hiroyuki Tsujikawa. ieicet, 88-C(4):589-596, 2005. [doi]

An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designsKenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa. cicc 2005: 31-34 [doi]

Power-Supply Noise Reduction with Design for ManufacturabilityHiroyuki Tsujikawa, Kenji Shimazaki, Shozo Hirano, Kazuhiro Sato, Masanori Hirofuji, Junichi Shimada, Mitsumi Ito, Kiyohito Mukai. ieicet, 88-A(12):3421-3428, 2005. [doi]

2003

A substrate noise analysis methodology for large-scale mixed-signal ICsWen Kung Chu, Nishath K. Verghese, Heayn-Jun Chol, Kenji Shimazaki, Hiroyuki Tsujikawa, Shouzou Hirano, Shirou Doushoh, Makoto Nagata, Atsushi Iwata, Takafumi Ohmoto. cicc 2003: 369-372 [doi]

A Design Methodology for Low EMI Noise LSI with Fast and Accurate EstimationHiroyuki Tsujikawa, Shozo Hirano, Kenji Shimazaki. ieiceta, 86-A(12):2974-2982, 2003. [doi]

2002

An EMI-Noise Analysis on LSI Design with Impedance EstimationKenji Shimazaki, Shouzou Hirano, Hiroyuki Tsujikawa. isqed 2002: 169-174 [doi]

A design methodology for low EMI-noise microprocessor with accurate estimation-reduction-verificationHiroyulu Tsujikawa, Kenji Shimazaki, Shozo Hirano, Motohiro Ohki, Talcashi Yoneda, Hiroshi Benno. cicc 2002: 299-302 [doi]

2000

LEMINGS: LSI s EMI-Noise Analysis with Gate Level SimulatorKenji Shimazaki, Hiroyuki Tsujikawa, Seijiro Kojima, Shouzou Hirano. isqed 2000: 129-136 [doi]

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