Table of Contents

• Automatic tuning of RC filters and fast automatic gain control for CMOS low-IF transceiverTakashi Oshima, Kenji Maio, Willy Hioe, Yoshiyuki Shibahara, Takeshi Doi. 5-8 [doi]
• OTA linearity enhancement technique for high frequency applications with IM3 below -65dBArtur J. Lewinski, José Silva-Martínez. 9-12 [doi]
• th order broadband 10.7 MHz SC ladder filterJosé Silva-Martínez, Joseph Adut, Miguel Rocha-Pérez. 13-16 [doi]
• A 28-MHz wide-band switched-capacitor bandpass filter with high attenuationKenneth W. H. Ng, Howard C. Luong. 17-20 [doi]
• A power efficient channel selection filter/coarse AGC with no range switching transientsYorgos Palaskas, Yannis P. Tsividis, Vito Boccuzzi. 21-24 [doi]
• The iFlow design factory infrastructure for a 17M-gate, 0.13μm, 333MHz design [SoC design]Gilles-Eric Descamps, Satish Bagalkotkar. 27-34 [doi]
• Design and development of the first single-chip full-duplex OC48 traffic manager and ATM SAR SoCAurangzeb Khan, Kaushik Patel, Amit Aurora, Adnan Raza, Bidyut Parruck, Anandarup Bagchi, Abijit Ghosh, Boris Litinsky, Eric Hong, Eric Zhao, Jeremy Ngo, Kenson Ko, Leena Singh, Pavel Arnaudov, Peter Wu, Rama Ramakrishnan, Rami Zecharia, Shankar Channabasappa, Suril Kumar, Sanjay Wattal, Tony Wang, Uday Joshi, Zohar Golan, Zunning Luo, Duc-Ngoc Le, Irfan Ahmed, Frederick Chiu, King Y. Chow, Hiroyuki Furuzono, David Ge, Min Li, Martin Mueller, Son Nguyen, Trung Nguyen, Jean Saito, John Shen, Antonio Todesco, Allen Tsou, Demin Wang, Steven Yang, John Yu, Xia Zhong. 35-38 [doi]
• The Intel® PXA800F wireless Internet-on-a-chip architecture and designDilip Krishnaswamy, Ray Stevens, Robert N. Hasbun, Juan R. Revilla, Chris Hagan. 39-42 [doi]
• SoC implementation issues for synthesizable embedded programmable logic coresJames C. H. Wu, Victor Aken Ova, Steven J. E. Wilton, Resve Saleh. 45-48 [doi]
• Cyclone ™: a low-cost, high-performance FPGAPaul Leventis, Mark Chan, Michael Chan, David M. Lewis, Behzad Nouban, Giles Powell, Brad Vest, Myron Wong, Renxin Xia, John Costello. 49-52 [doi]
• Regular logic fabrics for a via patterned gate array (VPGA)K. Y. Tong, V. Kheterpal, Vyacheslav Rovner, Lawrence T. Pileggi, Herman Schmit. 53-56 [doi]
• Leakage power analysis of a 90nm FPGATim Tuan, Bo-Cheng Lai. 57-60 [doi]
• Architecture of datapath-oriented coarse-grain logic and routing for FPGAsAndy Ye, Jonanthan Rose, David M. Lewis. 61-64 [doi]
• Analysis of timing recovery for multi-Gbps PAM transceiversChih-Kong Ken Yang, Koon-Lun Jackie Wong. 67-72 [doi]
• A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolatorRainer Kreienkamp, Ulrich Langmann, Christoph Zimmermann, Takuma Aoyama. 73-76 [doi]
• A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/OsHiok-Tiaq Ng, M.-J. Edward Lee, Ramin Farjad-Rad, Ramesh Senthinathan, William J. Dally, Anhtuyet Nguyen, Rohit Rathi, Trey Greer, John Poulton, John H. Edmondson, James Tran. 77-80 [doi]
• A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loopWoogeun Rhee, Herschel A. Ainspan, Sergey V. Rylov, Alexander V. Rylyakov, Michael P. Beakes, Daniel J. Friedman, Sudhir M. Gowda, Mehmet Soyuer. 81-84 [doi]
• MOSFET HF distortion behavior and modeling for RF IC designTzung-Yin Lee, Yuhua Cheng. 87-90 [doi]
• Non-linear transmission lines for pulse shaping in siliconEhsan Afshari, Ali Hajimii. 91-94 [doi]
• Differentially-shielded monolithic inductorsTak Shun Dickson Cheung, John R. Long, Kunal Vaed, Richard Volant, A. Chinthakindi, Chris M. Schnabel, J. Florkey, Z. X. He, Kenneth Stein. 95-98 [doi]
• A comparison of non-quasi-static and quasi-static harmonic balance implementations for coupled device and circuit simulationYutao Hu, Kartikeya Mayaram. 99-102 [doi]
• Analysis of spectral spreading in a phase-modulated system for 1.75-GHz GSM RF transmitter designHyunchol Shin, Brett C. Walker, Dongling Pan, Jeremy Dunworth, James Jaffee. 103-106 [doi]
• Statistical analysis of integrated passive delay linesBehnam Analui, Ali Hajimiri. 107-110 [doi]
• Cascaded noise-shaping modulators for oversampled data conversionBruce A. Wooley. 113-114 [doi]
• A 16-bit, 5MHz multi-bit sigma-delta ADC using adaptively randomized DWAYong-In Park, S. Karthikeyan, Wem Ming Koe, Zhongnong Jiang, Tiak-Chean Tan. 115-118 [doi]
• A 1.8-V 3-MS/s 13-bit ΔΣ A/D converter with pseudo data-weighted-averaging in 0.18-μm digital CMOSAnas A. Hamoui, Kenneth W. Martin. 119-122 [doi]
• A 92MHz, 80dB peak SNR SC bandpass ΣΔ modulator based on a high GBW OTA with no Miller capacitors in 0.35μm CMOS technologyBharath Kumar Thandri, José Silva-Martínez, José Miguel Rocha-Pérez, Jing Wang. 123-126 [doi]
• th-order continuous-time bandpass ΔΣ modulatorTodd S. Kaplan, Jose M. Cruz-Albrecht, Mehran Mokttari, Dave Mattews, Joseph F. Jensen, M. Frank Chang. 127-130 [doi]
• A 942 MHz output, 17.5 MHz bandwidth, -70dBc IMD3 ΣΔ DACSusan Luschas, R. Schreier, Hae-Seung. 131-134 [doi]
• A 200-MHz continuous-time CMOS delta-sigma modulator featuring nonlinear feedback controlTakis Zourntos. 135-138 [doi]
• High performance RF-filters suitable for above IC integration: film bulk-acoustic- resonators (FBAR) on siliconRobert Aigner. 141-146 [doi]
• CMOS LC oscillator using variable mean frequencyPing-Hsuan Hsieh, Jack Judy, Chih-Kong Ken Yang. 147-150 [doi]
• A 1-V 2.4-GHz FSK receiver with a complex BPF and a frequency doubler in CMOS/SOIMamoru Ugajin, Tsuneo Tsukahara. 151-154 [doi]
• A low power PSK receiver for space applications in 0.35-μm SOI CMOSMehmet R. Yuce, Wentai Liu, John Damiano, Bhaskar Bharath, Paul D. Franzon, Numan Sadi Dogan. 155-158 [doi]
• A 4-91 GHz distributed amplifier in a standard 0.12 μm SOI CMOS microprocessor technologyJean-Olivier Plouchart, Jonghae Kim, Noah Zamdmer, Liang-Hung Lu, Melanie Sherony, Yue Tan, Robert Groves, Robert Trzcinski, Mohamed Talbi, Asit Ray, Lawrence F. Wagner. 159-162 [doi]
• A batteryless wireless system with MTCMOS/SOI circuit technologyTakakuni Douseki, Tsuneo Tsukahara, Yoshifumi Yoshida, Fumiyasu Utsunomiya, Norio Hama. 163-168 [doi]
• Trends and challenges for wireless embedded DSPsLawrence T. Clark. 171-176 [doi]
• A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systemsHiroe Iwasaki, Jiro Naganuma, Yasuyuki Nakajima, Yutaka Tashiro, Ken Nakamura, Takeshi Yoshitome, Takayuki Onishi, Mitsuo Ikeda, Takaaki Izuoka, Makoto Endo. 177-180 [doi]
• A sub-mW MPEG-4 motion estimation processor core for mobile video applicationJunichi Miyakoshi, Yuri Kuroda, Masayuki Miyama, Kosuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto. 181-184 [doi]
• Visconti: multi-VLIW image recognition processor based on configurable processor [obstacle detection applications]Jun Tanahe, Yasuhiro Taniguchi, Takashi Miyamori, Yukimasa Miyamoto, Hideki Takeda, Masaya Tarui, Hiromitsu Nakayama, Nohuyulu Takeda, Kenichi Maeda, Masataka Matsui. 185-188 [doi]
• A fully programmable CMOS block matrix transform imager architectureAbhishek Bandyopadhyay, Paul E. Hasler. 189-192 [doi]
• A 2.3Gb/s fully integrated and synthesizable AES Rijndael coreNam Sung Kim, Trevor N. Mudge, Richard B. Brown. 193-196 [doi]
• MEMS for telecommunications: devices and reliabilityChorng-Ping Chang. 199-206 [doi]
• Three dimensional CMOS devices and integrated circuitsMei-Kei Ieong, Kathryn W. Guarini, Victor Chan, Kerry Bernstein, Rajiv V. Joshi, Jakub Kedzierski, Wilfred Haensch. 207-213 [doi]
• Amorphous silicon TFT circuit integration for OLED displays on glass and plasticArokia Nathan, Kapil Sakariya, Ani1 Kumar, Peyman Servati, Karim S. Karim, Denis Striakhilev, Andrei Sazonov. 215-222 [doi]
• Quantum-dot cellular automata by electric and magnetic field couplingGary H. Bernstein. 223-229 [doi]
• SP: an advanced surface-potential-based compact MOSFET modelGennady Gildenblat, T.-L. Chen, X. Gu, H. Wang, X. Cai. 233-240 [doi]
• A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundationPin Su, Samel K. H. Fung, Peter W. Wyatt, Hui Wan 0003, Mansun Chan, Ali M. Niknejad, Chenming Hu. 241-244 [doi]
• A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristicsKe-Wei Su, Yi-Ming Sheu, Chung-Kai Lin, Sheng-Jier Yang, Wen-Jya Liang, Xuemei Xi, Chung-Shi Chiang, Jaw-Kang Her, Yu-Tai Chia, Carlos H. Diaz, Chenming Hu. 245-248 [doi]
• MCAST: an abstract-syntax-tree based model compiler for circuit simulationBo Wan, Bo P. Hu, Lili Zhou, C.-J. Richard Shi. 249-252 [doi]
• A Verilog-A compact model for ESD protection NMOSTsJunjun Li, Sopan Joshi, Elyse Rosenbaum. 253-256 [doi]
• An accurate DAC modeling technique based on wavelet theoryJames T. Doyle, Young-Jun Lee, Yong-Bin Kim. 257-260 [doi]
• MIMO signal processing - the next frontier for capacity enhancementSyed Aon Mujtaba. 263-270 [doi]
• APP processing for high performance MIMO systems [receiver symbol detector]David Garrett, Linda M. Davis, Stephan ten Brink, Bertrand M. Hochwald. 271-274 [doi]
• An 8-user UMTS channel unit processor for 3GPP base station applicationsCharles Thomas 0002, Tom Prokop, Mark Bickerstaff, J. Niemasz, Pierre Bernadac, Patrice Saintot, R. Laufer, Dominique Bescher, R. Michel, Brett C. Walker, F. Derriennic, N. Burban, E. Le Pape, J. P. Moreau, I. Cha, S. Angioni, K. Mhirsi, J. Lee, P. Prat, G. Rogard, V. L'Aubin, D. Le Gall, C. Dagorn, D. Guillerm, P. Ragon, T. Goumis, M. Cooke, B. Widdup, G. Zhou, D. Garrettt, C. Conan, P. Cabon, A. Carter, C. Nicol, P. Keevill, P. Mankiewich. 275-278 [doi]
• Single-chip FEC codec using a concatenated BCH code for 10 Gb/s long-haul optical transmission systemsKatsutoshi Seki, K. Mikami, A. Katayama, S. Suzuki, N. Shinohara, M. Nakabayashi. 279-282 [doi]
• Low power direct digital frequency synthesizers in 0.18 μm CMOSJ. M. Pierre Langlois, Dhamin Al-Khalili. 283-286 [doi]
• A 415 MHz direct digital quadrature modulator in 0.25-μm CMOSYanlin Wu, Dengwei Fu, Alan N. Willson Jr.. 287-290 [doi]
• An integrated 10 GHz quadrature LC-VCO in SiGe: C BiCMOS - technology for low-jitter applicationsFrank Herzel, Wolfgang Winkler, Johannes Borngräber. 293-296 [doi]
• Techniques for in-band phase noise suppression in re-circulating DLLsSheng Ye, Lars C. Jansson, Ian Galton. 297-300 [doi]
• A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizerJingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski. 301-304 [doi]
• A study of injection pulling and locking in oscillatorsBehzad Razavi. 305-312 [doi]
• 45-Gb/s SiGe BiCMOS PRBS generator and PRBS checker [pseudorandom bit sequence]Seongwon Kim, Mohit Kapur, Mounir Meghelli, Alexander V. Rylyakov, Young Hoon Kwark, Daniel J. Friedman. 313-316 [doi]
• A 2-Gb/s/pin source synchronous CDMA bus interface with simultaneous multi-chip access and reconfigurable I/O capabilityJongsun Kim, Zhiwei Xu 0003, M. Frank Chang. 317-320 [doi]
• Advances in RF packaging technologies for next-generation wireless communications applications [RFIC]Lawrence Larson, Darryl Jessie. 323-330 [doi]
• SiGe BiCMOS technology for communication productsMarco Racanelli, Paul Kempf. 331-334 [doi]
• Ultra-thin silicon-on-sapphire component technology for short reach parallel optical interconnectsCharlie Kuznia, Joe Ahadian, Mark Englekirk, Man Wong, Jean Richaud, Mike Pendleton, Dick Pommer, Ron Reedy. 335-338 [doi]
• Scaling beyond the 65 nm node with FinFET-DGCMOSEdward J. Nowak, Thomas Ludwig, Ingo Aller, Jakub Kedzierski, M. Leong, BethAnn Rainey, Matthew J. Breitwisch, V. Gemhoefer, Joachim Keinert, David M. Fried. 339-342 [doi]
• Foundry technology for 130nm and beyond SoCDenny D. Tang, Carlos H. Diaz, Chih-Ping Chao, Humning Hsu, Chwan-Ying Lee, Chih-Sheng Chang, Yu-Tai Chia, Ming-Ta Yang, Jack Y.-C. Sun. 343-350 [doi]
• Design and modeling challenges for 90 NM and 50 NMVassilios Gerousis. 353-360 [doi]
• Strategies for simulation, measurement and suppression of digital noise in mixed-signal circuitsBrian Owens, Patrick Birrer, Sirisha Adluri, Robert Shreeve, Sasi Kumar Arunachalam, Husni Habal, Shu-Ching Hsu, Ajit Sharma, Kartikeya Mayaram, Terri S. Fiez. 361-364 [doi]
• Analyzing the impact of supply and substrate noise on jitter in Gb/s serial linksSridhar Ramaswamy. 365-368 [doi]
• A substrate noise analysis methodology for large-scale mixed-signal ICsWen Kung Chu, Nishath K. Verghese, Heayn-Jun Chol, Kenji Shimazaki, Hiroyuki Tsujikawa, Shouzou Hirano, Shirou Doushoh, Makoto Nagata, Atsushi Iwata, Takafumi Ohmoto. 369-372 [doi]
• Placing substrate contacts into mixed-signal circuits controlling circuit performanceAndreas Hermann, Markus Olbrich, Erich Barke. 373-376 [doi]
• Optimization of phase-locked loop circuits via geometric programmingDavid M. Colleran, Clemenz Portmannt, Arash Hassibi, César A. R. Crusius, Sunderarajan S. Mohan, Stephen P. Boyd, Thomas H. Lee, Maria del Mar Hershenson. 377-380 [doi]
• Pipelined match-lines and hierarchical search-lines for low-power content-addressable memoriesKostas Pagiamtzis, Ali Sheikholeslami. 383-386 [doi]
• 200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4Mbits ternary CAM with new charge injection match detect circuits and bank selection schemeGen Kasai, Yukihiro Takarabe, Koji Furumi, Masato Yoneda. 387-390 [doi]
• Programmable and automatically adjustable on-die terminator for DDR3-SRAM interfaceNam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho, Hyun-Geun Byun. 391-394 [doi]
• 5 chalcogenide phase-change memory device for low power, high speed embedded memory for SoC applicationsYi-Chou Chen, C. T. Chen, J. Y. Yu, Chienying Lee, Chieh-Fang Chen, S. L. Lung, Rich Liu. 395-398 [doi]
• 3) architecture for a burst operated 1.5V MRAM macroTsuneo Inaba, Kenji Tsuchida, Tadahiko Sugibayashi, Shuichi Tahara, Hiroaki Yoda. 399-402 [doi]
• Design and applications of ferroelectric nonvolatile SRAM and flip-flop with unlimited read/program cycles and stable recallShoichi Masui, Wataru Yokozeki, Michiya Oura, Tsuzumi Ninomiya, Kenji Mukaida, Yoshihisa Takayama, Toshiyuki Teramoto. 403-406 [doi]
• A 12-bit 20-MS/s pipelined ADC with nested digital background calibrationXiaoyue Wang, Paul J. Hurst, Stephen H. Lewis. 409-412 [doi]
• A 1.8-V 67mW 10-bit 100MSPS pipelined ADC using time-shifted CDS techniqueJipeng Li, Un-Ku Moon. 413-416 [doi]
• A 16-bit, 20MSPS CMOS pipeline ADC with direct INL detection algorithmShinichi Hisano, Scott E. Sapp. 417-420 [doi]
• A 9b 165MS/s 1.8V pipelined ADC with all digital transistors amplifierMezyad M. Amourah, Haydar Bilhan, Feng Ying, Lieyi Fang, Gonggui Xu, Ramesh Chandrasekarad, Randall L. Geiger. 421-424 [doi]
• Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25 μm CMOSPatrick Quinn, Maxim Pribytko. 425-428 [doi]
• A dual 10b 200MSPS pipeline D/A converter with DLL-based clock synthesizerGabriele Manganaro, Sung-Ung Kwak, Alex R. Bugeja. 429-432 [doi]
• A 10-b, 1-GSample/s track-and-hold amplifier using SiGe BiCMOS technologyAlireza Razzaghi, M.-C. Frank Chang. 433-436 [doi]
• Polar modulator for multi-mode cell phonesWendell B. Sander, Stephan V. Schell, Brian L. Sander. 439-445 [doi]
• A 1 V, 8 GHz CMOS integrated phase shifted transmitter for wideband and varying envelope communication systemsSotoudeh Hamedi-Hagh, C. André T. Salama. 447-450 [doi]
• Wide-bandwidth fully integrated Cartesian feedback transmitterFrancesco Carrara, Antonino Scuden, Giuseppe Palmisano. 451-454 [doi]
• A CMOS Bluetooth radio transceiver using a sliding-IF architectureMin Chen, Kevin H. Wang, Desong Zhao, Liang Dai, Zaw Soe, Paul Rogers. 455-458 [doi]
• A 15 mW, 70 kHz 1/f corner direct conversion CMOS receiverEnrico Sacchi, Ivan Bietti, Simone Erbat, Luns Tee, Paolo Vilmercati, Rinaldo Castello. 459-462 [doi]
• An UMTS ΣΔ fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @ 1 MHz using spurs compensation and linearization techniquesIvan Bietti, Enrico Temporiti, Guido Albasini, Rinaldo Castello. 463-466 [doi]
• Proximity communicationRobert J. Drost, Robert David Hopkins, Ivan E. Sutherland. 469-472 [doi]
• A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensationYoung-Soo Sohn, Seung-Jun Bae, Hong June Park, Changhyun Kim, Soo-In Cho. 473-476 [doi]
• Integrated circuit for high-frequency ultrasound annular arrayJames R. Talman, Steven L. Garverick, Geoffrey R. Lockwood. 477-480 [doi]
• Bipolar pulse width modulation driver for MEMS electrostatic actuator arraysSteven L. Garverick, Michael L. Nagy, Michael J. Kane, Jun Guo. 481-484 [doi]
• A 1/3" VGA linear wide dynamic range CMOS image sensor implementing a predictive multiple sampling algorithm with overlapping integration intervalsPablo M. Acosta-Serafini, Ichiro Masaki, Charles G. Sodini. 485-488 [doi]
• Piezoelectric power generation interface circuitsTriet Le, Jifeng Han, Annette R. von Jouanne, Kartikeya Mayaram, Terri S. Fiez. 489-492 [doi]
• A high voltage Dickson charge pump in SOI CMOSMohammad R. Hoque, Ty McNutt, Jimmy Zhang, H. Alan Mantooth, Mohammad M. Mojarradi. 493-496 [doi]
• Development of microelectronic based biosensorsA. Campifelli, Carmen Bartic, Jean-Michel Friedt, K. De Keersmaecker, Wim Laureyn, Laurent A. Francis, F. Frederix, Gunter Reekmans, Angelina Angelova, Jan Suls, K. Bonroy, R. De Palma, Z. Cheng, Gustaaf Borghs. 505-512 [doi]
• The fabrication of scalable multi-sensor arrays using standard CMOS technology [chemical sensors]Mark J. Milgrew, David R. S. Cumming, Paul A. Hammond. 513-516 [doi]
• A retinal prosthesis device based on an 80×40 hybrid microelectronic-microwire glass arrayDean A. Scribner, Lee-Johnson, Richard Klein, William E. Bassett, J. Grant Howard, Perry Skeath, Lucienne Wasserman, B. Wright, F. Keith Perkins, Martin Peckerar, B. J. Finch, Robert Graham, Walter C. Trautfield, S. Taylor, Mark S. Humayun. 517-520 [doi]
• A 16-channel analog VLSI processor for bionic ears and speech-recognition front endsMichael W. Baker, Timothy Kuan-Ta Lu, Christopher D. Salthouse, Ji-Jon Sit, Serhii M. Zhak, Rahul Sarpeshkar. 521-526 [doi]
• A surface-mounted RF IC technology demonstrated with a 10 GHz LC oscillator with copper coilsJohan van der Tang, Ronald Dekker, Arthur H. M. van Roermund. 529-532 [doi]
• A new IC interconnection scheme and design architecture for high performance ICs at very low fabrication cost - post passivation interconnectionM. S. Lin, Ling Chen, J. Y. Lee, H. T. Liu, C. K. Chou, K. H. Wan, H. M. Chen, Kevin Chou, Roger Hsiao, Eric Lin. 533-536 [doi]
• Silicon-on-organic integration of a 2.4GHz VCO using high Q copper inductors and solder-bumped flip chip technologyXiao Huo, Guo-Wei Xiao, Kevin J. Chen, Philip C. H. Chan. 537-540 [doi]
• Lumped, inductorless oscillators: how far can they go? [phase noise reduction limit]Reza Navid, Thomas H. Lee, Robert W. Dutton. 543-546 [doi]
• The impact of device type and sizing on phase noise mechanisms [MOS VCOs]Albert C. Jerng, Charles G. Sodini. 547-550 [doi]
• A 0.35-V 1.46-mW low-phase-noise oscillator with transformer feedback in standard 0.18-μm CMOS processKa Chun Kwok, Howard C. Luong. 551-554 [doi]
• A wideband low-phase-noise CMOS VCOAxel D. Bemy, Ali M. Niknejad, Robert G. Meyer. 555-558 [doi]
• A 2-GHz wide band low phase noise voltage-controlled oscillator with on-chip LC tankJe-Kwang Cho, Han-Il Lee, Kyung-suc Nah, Byeong-ha Park. 559-562 [doi]
• Injection locking LC dividers for low power quadrature generationAndrea Mazzanti, Paola Uggetti, Paolo Rossi, Francesco Svelto. 563-566 [doi]
• A subharmonically-injected quadrature LO generator for 17GHz WLAN applicationsDennis K. Ma, John R. Long, D. L. Hararne. 567-570 [doi]
• Just-in-time gain estimation of an RF digitally-controlled oscillatorRobert Bogdan Staszewski, Dirk Leipold, John L. Wallberg, Paras T. Balsam. 571-574 [doi]
• A low-power 0.13μm CMOS OC-48 SONET and XAUI compliant SERDESR. Wadhwa, A. Aggarwal, J. Edwards, M. Ehlert, J. Hoehn, G. Miao, Kadaba Lakshmikumar, John M. Khoury. 577-580 [doi]
• A 39.8Gb/s to 43.1Gb/s SFI-5 compliant 16: 1 multiplexer and 1: 16 demultiplexer for optical communication systemsThomas W. Krawczyk Jr., Sam A. Steidl, Richard Alexander, James Pulver, Gary Kowalski, Craig Hornbuckle, David Rowe. 581-584 [doi]
• A 62.5 Gb/s multi-standard SerDes ICHamid Partovi, Bill Evans, Tom Wilson, Scott Shelton, Eric Naviasky, Ethiraj Sanjeevi, Yongli Wen, Karthik Gopalakrishnan, Sivaraman Chokalingam, Hugh Thompson, Mike Casas, Lingting Ye, Mike Hufford, Yujing Qiu, Michelle Williams, Jared James, Alberto Baldisserotto, Steven White, Steve Williams, Domenic Georgantas, Tom Gray. 585-588 [doi]
• Modeling and analysis of high-speed linksVladimir Stojanovic, Mark Horowitz. 589-594 [doi]
• A fully-integrated 10.5 to 13.5 Gbps transceiver in 0.13 μm CMOSG. Miao, P. Ju, D. Ng, John M. Khoury, Kadaba Lakshmikumar. 595-598 [doi]
• A universal quad AFE with integrated filters for VDSL, ADSL, and G.SHDSLN. Tan, F. Caster, C. Eichrodt, S. O. George, B. Horng, J. Zhao. 599-602 [doi]
• CMOS IC nanometer technology failure mechanismsCharles F. Hawkins, Ali Keshavarzi, Jaume Segura 0001. 605-611 [doi]
• In-system failure investigation on 0.18 μm high speed serial link ASIC using logic built-in self testJeanne Trinko Mechler, Raymond J. Bulaga, Jon Garlett. 613-616 [doi]
• Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS processPeter Hazucha, Tanay Kamik, Steven Walstra, Bradley Bloechel, James Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva Narendra, Vivek De, Shekhar Borkar. 617-620 [doi]
• A 5-channel, variable resolution, 10-GHz sampling rate coherent tester/oscilloscope IC and associated test vehiclesMohamed M. Hafed, Gordon W. Roberts. 621-624 [doi]
• Estimation of Iddq for early chip and technology design decisionsTerence Hook, Larry Wissel, David Mazgaj. 627-630 [doi]
• An ultra-low-power, radiation-tolerant Reed Solomon encoder for space applicationsJody W. Gambles, Lowell H. Miles, J. Hass, W. Smith, Sterling R. Whitaker, Brant Smith. 631-634 [doi]
• Statistical leakage current reduction by self-timed cut-off scheme for high leakage environmentsJin Hyeok Choi, Takayasu Sakurai. 635-638 [doi]
• Standby voltage scaling for reduced powerBenton H. Calhoun, Anantha P. Chandrakasan. 639-642 [doi]
• A high-speed and low-voltage associative co-processor with Hamming distance ordering using word-parallel and hierarchical search architectureYusuke Oike, Makoto Ikeda, Kunihiro Asada. 643-646 [doi]
• Resonant clocking using distributed parasitic capacitanceAlan J. Drake, Kevin J. Nowka, Tuyet Nguyen, Jeffrey L. Bums, Richard B. Brown. 647-650 [doi]
• Embedded software in the SoC world. How HdS helps to face the HW and SW design challenge [hardware dependent software]Frank Pospiech, Stephen Olsen. 653-658 [doi]
• Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignmentRanianand Venkata, Wilson Wong, Tina Tran, Vinson Chan, Tim Hoang, Henry Lui, Uinh Ton, Sergey Shomurryev, Chong Lee, Shoujun Waiig, Huy Ngo, Malik Kdhani, Victor Maruri, Tin Lai, Tam Kpuyeu, Arch Zaliziiyak, Mei Luo, Toan Nguyen, Kazi Asaduzzaman, Siniardeep Maangat, John Lam, Rakesh Patel. 659-662 [doi]
• Design challenges for system-in-package vs system-on-chipCynthia Trigas. 663-666 [doi]
• A distributed crossbar switch scheduler for on-chip networksKangmin Lee, Se-Joong Lee, Hoi-Jun Yoo. 671-674 [doi]
• Low-voltage power-efficient operational amplifier design techniques - an overviewKlaas-Jan de Langen, Johan H. Huijsing. 677-684 [doi]
• A highly linear CMOS buffer circuit with an adjustable output impedanceMasato Koutani, Yoshihisa Fujimoto, Masayuki Miyamoto. 685-688 [doi]
• High-frequency 750mV operational amplifier standard bulk CMOS processYonghui Tang, Randall L. Geiger. 689-692 [doi]
• Switching noise reduction techniques for switched-capacitor voltage doublerHoi Lee, Philip K. T. Mok. 693-696 [doi]
• A new method for multiplying the Miller capacitance using active components [voltage regulator example]G. de Cremoux, Y. Christoforou, I. van Loo. 697-700 [doi]
• An equation-based method for phase noise analysis [oscillator examples]Brian N. Limketkai, Robert W. Brodersen. 703-706 [doi]
• α noise using a multi-rate filter bankJongsun Park 0001, Khurram Muhammad, Kaushik Roy 0001. 707-710 [doi]
• Modeling of jitter in bang-bang clock and data recovery circuitsJri Lee, Kenneth S. Kundert, Behzad Razavi. 711-714 [doi]
• Theoretical study of stubs for power line noise reduction [LSI applications]Toru Nakura, Makoto Ikeda, Kunihiro Asada. 715-718 [doi]
• Noise analysis methodology for partially depleted SOI circuitsMini Nanua, David T. Blaauw. 719-722 [doi]
• On-package decoupling optimization with package macromodelsHui Zheng, Byron Krauter, Lawrence T. Pileggi. 723-726 [doi]