Gabriele Manganaro - researchr alias

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Viewing Publication 1 - 38 from 38

2024

A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFETRishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee. jssc, 59(4):1158-1170, April 2024. [doi]

2023

Generalized Sampling-Based Multi-Channel Sampling of Signals Realized With Pure Delay Analog Filters and Digital FIR Reconstruction FiltersBibhudatta Sahoo 0002, Gabriele Manganaro. tcasII, 70(9):3323-3327, September 2023. [doi]

New Year Editorial 2023Gabriele Manganaro, Nicole McFarlane. ojcands, 4:2, 2023. [doi]

A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFETRishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee. vlsit 2023: 1-2 [doi]

A 14b 16GS/s Time-Interleaving Oirect-RF Synthesis OAe with T-OEM Achieving -70dBc IM3 up to 7.8GHz in 7nmWei-Hsin Tseng, Willy Lin, Chung-Wei Hsu, Chang-Yang Huang, Yu-Sian Lin, Hung-Yi Huang, HsinWei Chen, Sheng-hui Liao, Kuan-Dar Chen, Jon Strange, Gabriele Manganaro. isscc 2023: 268-269 [doi]

2022

Editorial: Where Are We Now and Where Do We Go From HereGabriele Manganaro. ojcands, 3:1-3, 2022. [doi]

A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFETAthanasios Ramkaj, Adalberto Cantoni, Gabriele Manganaro, Siddharth Devarajan, Michiel Steyaert, Filip Tavernier. vlsit 2022: 100-101 [doi]

2021

Editorial on the Special Section on the 2021 IEEE International Symposium on Integrated Circuits and SystemsGabriele Manganaro. ojcands, 2:434-435, 2021. [doi]

New Year EditorialGabriele Manganaro. ojcands, 2:1-2, 2021. [doi]

2020

Inaugural Issue of the IEEE Open Journal of Circuits and Systems: Welcome NoteGabriele Manganaro. ojcands, 1:1-2, 2020. [doi]

2018

Emerging data converter architectures and techniquesGabriele Manganaro. cicc 2018: 1-8 [doi]

In-situ nonlinear calibration of a RF signal chainNevena Rakuljic, Carroll Speir, Eric Otte, Jeff Bray, Corey Petersen, Gabriele Manganaro. iscas 2018: 1-5 [doi]

2017

2014

A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IFHyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn. jssc, 49(2):405-415, 2014. [doi]

2013

Progress update and a look aheadGabriele Manganaro. tcas, 60-I(1):1-2, 2013. [doi]

Outgoing EditorialGabriele Manganaro. tcas, 60-I(12):3105-3106, 2013. [doi]

2012

A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IFHyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael Flynn. isscc 2012: 148-150 [doi]

Guest Editorial Special Issue on ISCAS 2011Tor Sverre Lande, Peter T. J. Liang, Gabriele Manganaro, Eduardo A. B. da Silva, Aleksandar Tasic. tcas, 59-I(5):905, 2012. [doi]

Incoming EditorialGabriele Manganaro. tcas, 59-I(1):1-2, 2012. [doi]

2011

2010

Guest Editorial Special Section on 2009 IEEE System-on-Chip ConferenceAndrew Marshall, Sakir Sezer, Gabriele Manganaro. tcas, 57-I(12):3037-3038, 2010. [doi]

Guest Editorial Special Section on 2009 IEEE Custom Integrated Circuits ConferenceShahriar Mirabbasi, John W. M. Rogers, Gabriele Manganaro. tcas, 57-I(9):2245-2247, 2010. [doi]

2008

2007

Two-path band-pass Δ∑ modulator with 40-MHz IF 72-dB DR at 1-MHz bandwidth consuming 16 mWIvano Galdi, Edoardo Bonizzoni, Franco Maloberti, Gabriele Manganaro, Piero Malcovati. esscirc 2007: 248-251 [doi]

A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without CalibrationJ. Li, Robert Leboeuf, Matthew Courcy, Gabriele Manganaro. cicc 2007: 317-320 [doi]

2004

A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizerGabriele Manganaro, Sung-Ung Kwak, Alex R. Bugeja. jssc, 39(11):1829-1838, 2004. [doi]

2003

A dual 10b 200MSPS pipeline D/A converter with DLL-based clock synthesizerGabriele Manganaro, Sung-Ung Kwak, Alex R. Bugeja. cicc 2003: 429-432 [doi]

A behavioral modeling approach to the design of a low jitter clock sourceGabriele Manganaro, Sung U. Kwak, SeongHwan Cho, Anurag Pulincherry. tcasII, 50(11):804-814, 2003. [doi]

2001

An improved phase clock generator for interleaved and double-sampled switched-capacitor circuitsGabriele Manganaro. icecsys 2001: 1553-1556 [doi]

2000

A triple 8b, 80MSPS 3.3 V graphics digitizerIrfan A. Chaudrhry, Sung U. Kwak, Gabriele Manganaro, Maher Sarraj, T. Lakshmi Viswanathan. iscas 2000: 557-560 [doi]

Nonlinear Computability Based on ChaosGabriele Manganaro, José Pineda de Gyvez. IJBC, 10(2):415-430, 2000. [doi]

1997

Cellular neural networks to explore complexityPaolo Arena, Riccardo Caponetto, Luigi Fortuna, Gabriele Manganaro. soco, 1(3):120-136, 1997. [doi]

1996

Generation of n-double scrolls via cellular neural networksPaolo Arena, Salvatore Baglio, Luigi Fortuna, Gabriele Manganaro. ijcta, 24(3):241-252, 1996. [doi]

1995

Complexity in an Industrial flyback converterSalvatore Baglio, Luigi Fortuna, Gabriele Manganaro, Rosario Cristaudo. jcsc, 5(4):627-634, 1995. [doi]

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