Table of Contents

• Technical and economical trends in microelectronicsWolfgang Ziebart. 1-10 [doi]
• Architecture approaching the atomic scaleAndré DeHon. 11-20 [doi]
• CMOS image sensors: State-of-the-art and future perspectivesAlbert Theuwissen. 21-27 [doi]
• Model to Hardware matching for nano-meter scale technologiesSani R. Nassif. 28-31 [doi]
• 45nm/32nm CMOS ˜ Challenge and Perspective ˜Kazunari Ishimaru. 32-35 [doi]
• Joining microelectronics and microionics: Nerve cells and brain tissue on semiconductor chipsPeter Fromherz. 36-45 [doi]
• Large-area molecular junctionsDago M. De Leeuw. 46 [doi]
• The future outlook of memory devicesKinam Kim, Donggun Park. 47 [doi]
• The Monte Carlo approach to transport modeling in deca-nanometer MOSFETsEnrico Sangiorgi, Pierpaolo Palestri, David Esseni, Claudio Fiegna, Luca Selmi. 48-57 [doi]
• Designing analog and RF circuits for ultra-low supply voltagesPeter R. Kinget. 58-67 [doi]
• Low-voltage limitations of memory-rich nano-scale CMOS LSIsKiyoo Itoh, Masashi Horiguchi, Masanao Yamaoka. 68-75 [doi]
• Smart sensor design: The art of compensation and cancellationKofi A. A. Makinwa, Michiel A. P. Pertijs, Jeroen C. v. d. Meer, Johan H. Huijsing. 76-82 [doi]
• Key directions and a roadmap for electrical design for manufacturabilityAndrew B. Kahng. 83-88 [doi]
• Rigorous extraction of process variations for 65nm CMOS designWei Zhao, Yu Cao 0001, Frank Liu, Kanak Agarwal, Dhruva Acharyya, Sani R. Nassif, Kevin J. Nowka. 89-92 [doi]
• The scalability of 8T-SRAM cells under the influence of intrinsic parameter fluctuationsB. Cheng, Scott Roy, A. Asenov. 93-96 [doi]
• Analog circuits for sensorsBedrich J. Hosticka. 97-102 [doi]
• Integrated sensor for light source position measurement applicable in SOI technologyChristian Koch 0004, Jürgen Oehm, Jannik Emde, Wolfram Budde. 103-106 [doi]
• Single-grain Si thin-film transistors for analog and RF circuit applicationsNitz Saputra, Mina Danesh, Alessandro Baiano, Ryoichi Ishihara, John R. Long, Wim Metselaar, C. I. M. Beenakker, Nobuo Karaki, Y. Hiroshima, Satoshi Inoue. 107-110 [doi]
• Efficiency of low-power design techniques in Multi-Gate FET CMOS CircuitsChristian Pacha, Klaus von Arnim, Florian Bauer, Thomas Schulz, Wade Xiong, K. T. San, Andrew Marshall, Thomas Baumann, C. Rinn Cleavelin, Klaus Schruefer, Jörg Berthold. 111-114 [doi]
• Impact of well edge proximity effect on timingToshiki Kanamoto, Yasuhiro Ogasahara, Keiko Natsume, Kenji Yamaguchi, Hiroyuki Amishiro, Tetsuya Watanabe, Masanori Hashimoto. 115-118 [doi]
• Impact of stress on various circuit characteristics in 65nm PDSOI technologySushant Suryagandh, Mayank Gupta, Zhiyuan Wu, Srinath Krishnan, Mario Pelella, Jung-Suk Goo, Ciby Thuruthiyil, Judy X. An, Brian Q. Chen, Niraj Subba, Luis Zamudio, James Yonemura, Ali B. Icel. 119-122 [doi]
• Analog design challenges and trade-offs using emerging materials and devicesMichael Fulde, Abdelkarim Mercha, Cedric Gustin, Bertrand Parvais, Vaidyanathan Subramanian, Klaus von Arnim, Florian Bauer, Klaus Schruefer, Doris Schmitt-Landsiedel, Gerhard Knoblinger. 123-126 [doi]
• A 1V wireless transceiver for an ultra low power SoC for biotelemetry applicationsAlan Chi Wai Wong, Ganesh Kathiresan, Chung Kei Thomas Chan, Omar El-Jamaly, Alison J. Burdett. 127-130 [doi]
• Low power UWB pulse radio transceiver front-endMuhammad Anis, Reinhard Tielert. 131-134 [doi]
• A 1 V 250 KPPS 90 NM CMOS pulse based transceiver for CM-range wireless communicationDavide Guermandi, Simone Gambini, Jan M. Rabaey. 135-138 [doi]
• An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 μm CMOSAlessio Vallese, Andrea Bevilacqua, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani. 139-142 [doi]
• A CMOS RF front-end with on-chip antenna for V-band broadband wireless communicationsChao-Shiun Wang, Juin-Wei Huang, Shon-Hang Wen, Shih-Huang Yeh, Chorng-Kuang Wang. 143-146 [doi]
• An 11-bit 45MS/s pipelined ADC with rapid calibration of DAC errors in a multi-bit pipeline stageImran Ahmed 0006, David A. Johns. 147-150 [doi]
• A 10b 200MS/s pipelined folding ADC with offset calibrationCheng-Chung Hsu, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee. 151-154 [doi]
• A 1.2V 200-MS/s 10-bit folding and interpolating ADC in 0.13-μm CMOSYihui Chen, Qiuting Huang, Thomas Burger. 155-158 [doi]
• A high bandwidth power scaleable sub-sampling 10-bit pipelined ADC with embedded sample and holdImran Ahmed 0006, David A. Johns. 159-162 [doi]
• 1-GHz Input bandwidth 6-bit under-sampling A/D converter for UWB-IR receiverTatsuo Nakagawa, Tatsuji Matsuura, Eiki Imaizumi, Junya Kudoh, Goichi Ono, Masayuki Miyazaki, Akira Maeki, Yuji Ogata, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura. 163-166 [doi]
• Power management for portable devicesMario Manninger. 167-173 [doi]
• Adaptive frequency control technique for enhancing transient performance of DC-DC convertersHong-Wei Huang, Chun-Yu Hsieh, Ke-Horng Chen, Sy-Yen Kuo. 174-177 [doi]
• A CMOS Current-mode DC-DC converter with input and output voltage-independent stability and frequency characteristics utilizing a quadratic slope compensation schemeKiyokazu Umimura, Hiroki Sakurai, Yasuhiro Sugimoto. 178-181 [doi]
• A 0.35μm 50V CMOS sliding-mode control IC for buck convertersMikkel Hoyerby, Michael A. E. Andersen, Pietro Andreani. 182-185 [doi]
• A wide-range duty-independent all-digital multiphase clock generatorHyunsoo Chae, Sangdon Jung, Chulwoo Kim. 186-189 [doi]
• Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock DistributionDavid Levacq, Muhammad Yazid, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai. 190-193 [doi]
• Variation tolerant high resolution and low latency time-to-digital converterStephan Henzler, Siegmar Koeppe, Dominik Lorenz, Winfried Kamp, Ronald Kuenemund, Doris Schmitt-Landsiedel. 194-197 [doi]
• A 90μW 15-bit ΔΣ ADC for digital audioShanthi Pavan, Nagendra Krishnapura, Ramalingam Pandarinathan, Prabu Sankar. 198-201 [doi]
• A 100KS/s 65dB DR Σ - Δ ADC with 0.65V supply voltageSimone Gambini, Jan M. Rabaey. 202-205 [doi]
• A 0.2V, 7.5 μW, 20 kHz ΣΔ modulator with 69 dB SNR in 90 nm CMOSUlrik Wismar, Dag T. Wisland, Pietro Andreani. 206-209 [doi]
• A wide tuning range Gm-C filter for multi-mode direct-conversion wireless receiversTien-Yu Lo, Chung-Chih Hung, Mohammed Ismail 0001. 210-213 [doi]
• A 40-200 MHz programmable 4th-order Gm-C filter with auto-tuning systemAránzazu Otín, Santiago Celma, Concepción Aldea. 214-217 [doi]
• Digital tuning of an analog tunable bandpass BAW-filter at GHz frequencyStephane Razafimandimby, Cyrille Tilhac, Andreia Cathelin, Andreas Kaiser, Didier Belot. 218-221 [doi]
• Exploring technology related design-space limitations of high performance network processingJohn V. McCanny, Sakir Sezer, Máire O'Neill. 222-231 [doi]
• A low-power vector processor using logarithmic arithmetic for handheld 3d graphics systemsByeong-Gyu Nam, Hoi-Jun Yoo. 232-235 [doi]
• A flexible, ultra-low power 35pJ/pulse digital back-end for a QAC UWB receiverMarian Verhelst, Wim Dehaene. 236-239 [doi]
• A 312-MHz CT Δ∑ modulator using a SC feedback DAC with reduced peak currentMartin Anderson, Lars Sundström. 240-243 [doi]
• A 14-mW, 153.6-MHz clock-rate Δ∑ modulator for WCDMA with 77-dB SFDR using constant resistance CMOS input sampling switchOlujide A. Adeniran, Andreas Demosthenous. 244-247 [doi]
• Two-path band-pass Δ∑ modulator with 40-MHz IF 72-dB DR at 1-MHz bandwidth consuming 16 mWIvano Galdi, Edoardo Bonizzoni, Franco Maloberti, Gabriele Manganaro, Piero Malcovati. 248-251 [doi]
• A single die 124dB stereo audio delta sigma ADC with 111dB THDYuQing Yang, Terry Sculley, Jacob Abraham. 252-255 [doi]
• A configurable High-Side/ low-Side DriverMichael Wendt, Lenz Thoma, Bernhard Wicht, Doris Schmitt-Landsiedel. 256-259 [doi]
• 10Gb/s 0.13µm CMOS laser drivers with extinction ratio control using thermistorsDay-Uei Li, Hsin-Chao Chen. 260-263 [doi]
• A fully integrated low EMI noise power supply technique for CMOS digital IC's in automotive applicationsJunfeng Zhou, Wim Dehaene. 264-267 [doi]
• A fully-integrated 0.18µm CMOS DC-DC step-up converter, using a bondwire spiral inductorMike Wens, Koen Cornelissens, Michiel Steyaert. 268-271 [doi]
• Power combining techniques for RF and mm-wave CMOS power amplifiersPatrick Reynaert, Ali M. Niknejad. 272-275 [doi]
• A millimeter-wave power amplifier with 25dB power gain and +8dBm saturated output powerYanyu Jin, Mihai A. T. Sanduleanu, Eduardo Alarcon Rivero, John R. Long. 276-279 [doi]
• Millimeter-wave amplifiers in 65-nm CMOSMikko Varonen, Mikko Kärkkäinen, Kari A. I. Halonen. 280-283 [doi]
• A novel architecture for inductive proximity sensors using sigma delta modulationSascha Thoss, Olaf Machul, Bedrich J. Hosticka. 284-287 [doi]
• A I-V 36-pW low-noise adaptive interface IC for portable biomedical applicationsQiang Li, Kuo Hwi Tan, T. Hui Teo, Rajinder Singh. 288-291 [doi]
• Interface electronics for a CMOS electrothermal frequency-locked-loopCheng Zhang, Kofi A. A. Makinwa. 292-295 [doi]
• A mixed-signal readout chip for a 7-cell Si-Drift detector in 0.35-μm BiCMOS technologyInge Diehl, Karsten Hansen, Christian Reckleben. 296-299 [doi]
• Gate bias circuit for an SCCMOS power switch achieving maximum leakage reductionAlexandre Valentian, Edith Beigné. 300-303 [doi]
• Ultra low power subthreshold MOS current mode logic circuits using a novel load device conceptArmin Tajalli, Eric A. Vittoz, Yusuf Leblebici, Elizabeth J. Brauer. 304-307 [doi]
• Performance improvement of embedded low-power microprocessor cores by selective flip flop replacementThomas Baumann, Jörg Berthold, T. Niedermeier, Tim Schoenauer, J. Dienstuhl, Doris Schmitt-Landsiedel, Christian Pacha. 308-311 [doi]
• A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logicHui Shao, Chi-Ying Tsui. 312-315 [doi]
• A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOSAmit Agarwal 0001, Nilanjan Banerjee, Steven K. Hsu, Ram K. Krishnamurthy, Kaushik Roy 0001. 316-319 [doi]
• A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing schemeKoh Johguchi, Yuya Mukuda, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide. 320-323 [doi]
• Visual image processing RAM for fast 2-D data location searchJoo-Young Kim 0001, Donghyun Kim, Seungjin Lee 0001, Kwanho Kim, Seonghyun Jeon, Hoi-Jun Yoo. 324-327 [doi]
• Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memoryAlexander Flocke, Tobias G. Noll. 328-331 [doi]
• An on-pixel FPN reduction method for a high dynamic range CMO S imagerEstelle Labonne, Gilles Sicard, Marc Renaudin. 332-335 [doi]
• A Wide DR and linear response CMOS image sensor with three photocurrent integrations in photodiodes, lateral overflow capacitors and column capacitorsNoriko Ide, Woonghee Lee, Nana Akahane, Shigetoshi Sugawa. 336-339 [doi]
• MOS-Capacitor based CMOS time-compression photogate pixel for time-of-flight imagingDaniel Durini, Werner Brockherde, Bedrich J. Hosticka. 340-343 [doi]
• A Sub-μA fast-settling current-programmed pixel circuit for AMOLED displaysG. Reza Chaji, Arokia Nathan. 344-347 [doi]
• 80 GHz low noise amplifiers in 65nm CMOS SOIBaudouin Martineau, Andreia Cathelin, François Danneville, Andreas Kaiser, Gilles Dambrine, Sylvie Lépilliet, Frederic Gianesello, Didier Belot. 348-351 [doi]
• A 64GHz 6.5 dB NF 15.5 dB gain LNA in 90nm CMOSStefano Pellerano, Yorgos Palaskas, Krishnamurthy Soumyanath. 352-355 [doi]
• Design considerations for low-noise, highly-linear millimeter-wave mixers in SiGe bipolar technologySaverio Trotta, Bernhard Dehlink, Herbert Knapp, Klaus Aufinger, Thomas F. Meister, Josef Bock, Werner Simbürger, Arpad L. Scholtz. 356-359 [doi]
• V-band balanced resistive mixer in 65-nm CMOSMikko Varonen, Mikko Kärkkäinen, Kari A. I. Halonen. 360-363 [doi]
• An inductorless wideband balun-LNA in 65nm CMOS with balanced outputStephan C. Blaakmeer, Eric A. M. Klumperink, Bram Nauta, Domine M. W. Leenaerts. 364-367 [doi]
• Low-noise variable-gain amplifier in 90-nm CMOS for TV on mobileLorenzo Tripodi, Hans Brekelmans. 368-371 [doi]
• A 5 GHz, 21 dBm output-IP3 resistive feedback LNA in 90-nm CMOSBevin G. Perumana, Jing-Hong Conan Zhan, Stewart S. Taylor, Joy Laskar. 372-375 [doi]
• A switchable low-area 2.4-and-5 GHz dual-band LNA in digital CMOSJonathan Borremans, Piet Wambacq, Geert Van der Plas, Yves Rolain, Maarten Kuijk. 376-379 [doi]
• A power amplifier driver using self-oscillating pulse-width modulatorsWillem Laflere, Michiel Steyaert, Jan Craninckx. 380-383 [doi]
• Embedded SRAM design in deep deep submicron technologiesWim Dehaene, Stefan Cosemans, Anselme Vignon, F. Catthoora, Peter Geens. 384-391 [doi]
• Layout options for stability tuning of SRAM cells in multi-gate-FET technologiesFlorian Bauer, Klaus von Arnim, Christian Pacha, Thomas Schulz, Michael Fulde, A. Nackaerts, M. Jurczak, Wade Xiong, K. T. San, C. Rinn Cleavelin, Klaus Schruefer, Georg Georgakos, Doris Schmitt-Landsiedel. 392-395 [doi]
• Operating-margin-improved SRAM with column-at-a-time body-bias control techniqueMasanao Yamaoka, Takayuki Kawahara. 396-399 [doi]
• Statistical modeling for the minimum standby supply voltage of a full SRAM arrayJiajing Wang, Amith Singhee, Rob A. Rutenbar, Benton H. Calhoun. 400-403 [doi]
• An integrated switched-capacitor front-end for capacitive sensors with a wide dynamic rangeAli Heidary, Gerard C. M. Meijer. 404-407 [doi]
• A clocked, regenerative comparator in 0.12μm CMOS with tunable sensitivityBernhard Goll, Horst Zimmermann. 408-411 [doi]
• A 7-μW clock generator in 0.18-μm CMOS for passive UHF RFID EPC G2 tagsL. Lincoln, K. Leung, Howard C. Luong. 412-415 [doi]
• A stable compensation scheme for low dropout regulator in the absence of ESRTsz Fai Kwok, Wing-Hung Ki. 416-419 [doi]
• An integrated DC current regulator with high EMI suppressionJean-Michel Redoute, Cedric Walravens, Steven Van Winckel, Michiel Steyaert. 420-423 [doi]
• A 65nm CMOS multi-standard, multi-band mobile TV tunerKostis Vavelidis, Iason Vassiliou, Nikos Haralabidis, Aris Kyranas, Yiannis Kokolakis, Stamatis Bouras, George Kamoulakos, Charalambos Kapnistis, Spyros Kavadias, Nikos Kanakaris, Emmanouil Metaxakis, Christos Kokozidis, Hamed Peyravi. 424-427 [doi]
• A single-chip CDMA-2000 zero-IF transceiver for band-class 4 with GPS supportSung-Gi Yang, Ji-Ho Ryu, Byoungjoong Kang, Heeseon Shin, Jinhyuck Yu, Sangsoo Ko, Won Ko, Dong-Jin Keum, Woo-Seung Choo, Byeong-ha Park. 428-431 [doi]
• A dual-mode zero-IF receiver for dual-band CDMA cellular and GPSOlivier Charlon, S. Clamagirand, V. Vathulya, C. Hritz, B. Fahs, O. Burg, C. Caumont, P. Barre, L. Guiraud, E. Chartier, V. Blanchard, Helen Waite, William Redman-White, R. Perkins, D. Brunel, E. Soudee. 432-435 [doi]
• A CMOS 100 MHz to 6 GHz software defined radio analog front-end with integrated pre-power amplifierMark Ingels, Charlotte Soens, Jan Craninckx, Vito Giannini, T. Kim, Björn Debaillie, Michael Libois, Michaël Goffioul, Joris Van Driessche. 436-439 [doi]
• A 5nV/√Hz-IRN, 78dB-gain-range, 78dB-DR multi-standard baseband chain for Bluetooth, UMTS and WLANStefano D'Amico, Marcello De Matteis, Andrea Baschirotto, Nicola Ghittori, Andrea Vigna, Piero Malcovati. 440-443 [doi]
• Clock jitter in class-D audio power amplifiersMarco Berkhout. 444-447 [doi]
• A +100dB gain, rail-to-rail output, low distortion, low noise amplifier in BiCMOS technologyPhilip Golden, Peter Mole, Barry Harvey. 448-451 [doi]
• A CMOS Operational Amplifier with Constant 68° phase margin over its whole range of noise-power trade-off programmabilityPhilipp Meier auf der Heide, Carsten Bronskowski, Jakob M. Tomasik, Dietmar Schroeder. 452-455 [doi]
• An integrated low-noise multichannel system for neural signals amplificationTommaso Borghi, Andrea Bonfanti, Guido Zambra, Riccardo Gusmeroli, Andrea L. Lacaita, Alessandro S. Spinelli, Gytis Baranauskas. 456-459 [doi]
• A fail-safe ASIC for implantable neural stimulationXiao Liu 0001, Andreas Demosthenous. 460-463 [doi]
• Design for millimeter-wave applications in silicon technologiesAndreia Cathelin, Baudouin Martineau, N. Seller, S. Douyere, Jean Gorisse, Sébastien Pruvost, Christine Raynaud, Frederic Gianesello, Sébastien Montusclat, Sorin P. Voinigescu, Ali M. Niknejad, Didier Belot, Jean-Pierre Schoellkopf. 464-471 [doi]
• A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOSHiroaki Hoshino, Ryoichi Tachibana, Toshiya Mitomo, Naoko Ono, Yoshiaki Yoshihara, Ryuichi Fujimoto. 472-475 [doi]
• Spectral PLL built-in self-test for integrated cellular transceiversChristian Muenker, Robert Weigel. 476-479 [doi]
• A multistandard Σ-Δ fractional-N frequency synthesizer for 802.11a/b/g WLANAndrea Bonfanti, Carlo Samori, Andrea L. Lacaita. 480-483 [doi]
• A fast start-up 3GHz-10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOSVincent De Heyn, Geert Van der Plas, Julien Ryckaert, Jan Craninckx. 484-487 [doi]
• An energy-efficient 1.5-Mbps wireless FSK transmitter with A ∑Δ-modulated phase rotatorYao-Hong Liu, Tsung-Hsien Lin. 488-491 [doi]
• Frequency synthesis for a low-power 2.4 GHz receiver using a BAW oscillator and a relaxation oscillatorJérémie Chabloz, David Ruffieux, Alexandre Vouilloz, Paola Tortori, Franz Pengg, Claude Müller, Christian C. Enz. 492-495 [doi]
• A novel quality factor tuning scheme for active-RC filtersShouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura. 496-499 [doi]
• A CMOS baseband complex bandpass filter with a new Automatic tuning method for PHS applicationsYoungGun Pu, Sung-Kyu Jung, Dojin Park, JinKyung Kim, Ji-Hoon Jung, Chul Nam, Kang-Yoon Lee. 500-503 [doi]
• A 550mV 8dBm IIP3 4pth order analog base band filter for WLAN receiversMarcello De Matteis, Stefano D'Amico, Vito Giannini, Andrea Baschirotto. 504-507 [doi]
• An 11.75-Gb/s combined decision feedback equalizer and clock data recovery circuit in 0.18-μm CMOSLijun Li, Michael M. Green. 508-511 [doi]
• A 10-Gb/sec unclocked current-mode logic (CML) analog decision-feedback equalizer (ADFE) in 0.18-μm CMOSSoumya Chandramouli, Franklin Bien, Hyoungsoo Kim, Edward Gebara, Joy Laskar. 512-515 [doi]
• A fully integrated CMOS burst-mode upstream transmitter for gigabit-class passive optical network applicationsYong-Hun Oh, Ho-Yong Kang, Kyoohyun Lim, Jongsik Kim, Sang-Gug Lee. 516-519 [doi]
• A 10-Gb/s CMOS fully integrated ILO-based CDROlivier Mazouffre, B. Goumballa, Michel Pignol, Claude Neveu, Yann Deval, Jean-Baptiste Begueret. 520-523 [doi]
• A 1.4-psec Jitter 2.5-Gb/s CDR with wide acquisition range in 0.18-μm CMOSM. Kumarasamy Raja, Dan Lei Yan, Aruna B. Ajjikuttira. 524-527 [doi]
• Gb/s CDR circuit for large synchronous networksSitt Tontisirin, Reinhard Tielert. 528-531 [doi]
• A low jitter clocking strategy for a 7.5-Gb/s SerDes array in 65nm CMOS technologyPaul Madeira, Marc-Andre LaCroix, John Hogeboom. 532-535 [doi]