Kinam Kim - researchr alias

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Viewing Publication 1 - 34 from 34

2016

2015

2012

Future silicon technologyKinam Kim. esscirc 2012: 1-6 [doi]

A 1920×1080 3.65μm-pixel 2D/3D image sensor with split and binning pixel structure in 0.11pm standard CMOSSeong-Jin Kim, Byongmin Kang, James D. K. Kim, KeeChang Lee, Chang-Yeong Kim, Kinam Kim. isscc 2012: 396-398 [doi]

2011

The ForgottenKinam Kim. siggrapha 2011: [doi]

2010

Correction on "A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme" [Aug 09 2222-2232]Kwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Joo-Sun Choi, Kinam Kim. jssc, 45(2):497, 2010. [doi]

2009

A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfacesKyung-Soo Ha, Lee-Sup Kim, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim. isscc 2009: 138-139 [doi]

A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSNKyung-Soo Ha, Lee-Sup Kim, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim. jssc, 44(11):3146-3162, 2009. [doi]

2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architectureYongsam Moon, Yong-Ho Cho, Hyun Bae Lee, Byung-Hoon Jeong, Seok-Hun Hyun, Byungchul Kim, In-Chul Jeong, Seong-Young Seo, Junho Shin, Seok-Woo Choi, Ho-Sung Song, Jung Hwan Choi, Kyehyun Kyung, Young-Hyun Jun, Kinam Kim. isscc 2009: 128-129 [doi]

A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression SchemeKwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Joo-Sun Choi, Kinam Kim. jssc, 44(8):2222-2232, 2009. [doi]

2008

A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory ArrayJung Sik Kim, Kyung-Woo Nam, Chi Sung Oh, Han Gu Sohn, Donghyuk Lee, Sooyoung Kim, Jong-Wook Park, Yongjun Kim, Mi-Jo Kim, Jin Guk Kim, Hocheol Lee, Jinhyoung Kwon, Dong Il Seo, Young-Hyun Jun, Kinam Kim. jssc, 43(11):2381-2389, 2008. [doi]

A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression schemeKwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Kinam Kim. cicc 2008: 639-642 [doi]

A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash MemoriesKi Tae Park, Myounggon Kang, Doogon Kim, Soonwook Hwang, Byung Yong Choi, Yeong-Taek Lee, Changhyun Kim, Kinam Kim. jssc, 43(4):919-928, 2008. [doi]

A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block RedundancyKyomin Sohn, Young-Ho Suh, Young-Jae Son, Daesik Yim, Kang-Young Kim, Dae-Gi Bae, Ted Kang, Hoon Lim, Soon-Moon Jung, Hyun-Geun Byun, Young-Hyun Jun, Kinam Kim. isscc 2008: 386-387 [doi]

2007

The future outlook of memory devicesKinam Kim, Donggun Park. esscirc 2007: 47 [doi]

2006

Enhanced write performance of a 64-mb phase-change random access memoryHyung-Rok Oh, Beak-Hyung Cho, Woo-Yeong Cho, Sangbeom Kang, Byung Gil Choi, Hye-Jin Kim, Ki-Sung Kim, Du-Eung Kim, Choong-Keun Kwak, Hyun-Geun Byun, Gitae Jeong, Hong-Sik Jeong, Kinam Kim. jssc, 41(1):122-126, 2006. [doi]

2005

A 0.18-/spl mu/m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)Woo-Yeong Cho, Beak-Hyung Cho, Byung Gil Choi, Hyung-Rok Oh, Sangbeom Kang, Ki-Sung Kim, Kyung Hee Kim, Du-Eung Kim, Choong-Keun Kwak, Hyun-Geun Byun, Youngnam Hwang, Sujin Ahn, Gwan-Hyeob Koh, Gitae Jeong, Hongsik Jeong, Kinam Kim. jssc, 40(1):293-300, 2005. [doi]

Emerging memory technologiesKinam Kim, Gitae Jeong, Hong-Sik Jeong, Sungyung Lee. cicc 2005: 423-426 [doi]

ChohonEunju Kim, Jung-Sun Choi, Junsang Yoon, Kinam Kim, Youngju Park, Youno Park. siggraph 2005: 264 [doi]

An embedded nonvolatile FRAM with electrical fuse repair scheme and one time programming scheme for high performance smart cardsByungJun Min, Kang-Woon Lee, Han-Ju Lee, So-Ra Kim, Seung-Gyu Oh, Byung-gil Jeon, Hee-Hyun Yang, Min-Kyu Kim, Sung Hee Cho, Honsik Cheong, Chilhee Chung, Kinam Kim. cicc 2005: 255-258 [doi]

2003

A 0.24-μm 2.0-V 1T1MTJ 16-kb nonvolatile magnetoresistance RAM with self-reference sensing schemeGitae Jeong, Wooyoung Cho, Sujin Ahn, Hongsik Jeong, Gwanhyeob Koh, Youngnam Hwang, Kinam Kim. jssc, 38(11):1906-1910, 2003. [doi]

Integration technology for ferroelectric memory devicesKinam Kim, Yoon J. Song. mr, 43(3):385-398, 2003. [doi]

2002

2000

A 0.4-/spl mu/m 3.3-V 1T1C 4-Mb nonvolatile ferroelectric RAM with fixed bitline reference voltage scheme and data protection circuitByung-gil Jeon, Mun-Kyu Choi, Yoonjong Song, Seung-Kyu Oh, Yeonbae Chung, Kang-Deog Suh, Kinam Kim. jssc, 35(11):1690-1694, 2000. [doi]

1999

A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAMHongil Yoon, Gi-Won Cha, Changsik Yoo, Nam-Jong Kim, Keum-Yong Kim, Chang-Ho Lee, Kyu-Nam Lim, Kyuchan Lee, Jun Young Jeon, Tae-Sung Jung, Hongsik Jeong, Tae-Young Chung, Kinam Kim, Soo-In Cho. jssc, 34(11):1589-1599, 1999. [doi]

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