Abstract is missing.
- Leaner and greener: Adapting to a changing climate of innovationRené Penning de Vries, William Redman-White, Raf Roovers, Leo Warmerdam, Ted Letavic. 8-13 [doi]
- Adaptive circuits for the 0.5-V nanoscale CMOS eraKiyoo Itoh. 14-20 [doi]
- The new era of scaling in an SoC worldMark Bohr. 23-28 [doi]
- Kids today! Engineers tomorrow?John Cohn. 29-35 [doi]
- A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensorVyshnavi Suntharalingam, Robert Berger, Stewart Clark, Jeffrey M. Knecht, Andrew Messier, Kevin Newcomb, Dennis Rathman, Richard Slattery, Antonio M. Soares, Charles Stevenson, Keith Warner, Douglas Young, Lin Ping Ang, Barmak Mansoorian, David C. Shaver. 38-39 [doi]
- A gamma, x-ray and high energy proton radiation-tolerant CIS for space applicationsLucio Carrara, Cristiano Niclass, Noémy Scheidegger, Herbert Shea, Edoardo Charbon. 40-41 [doi]
- A 4-channel 20-to300 Mpixel/s analog front-end with sampled thermal noise below kT/C for digital SLR camerasRonald Kapusta, Hiroto Shinozaki, Eitake Ibaragi, Kevin Ni, Richard Wang, Mark Sayuk, Larry Singer, Katsu Nakamura. 42-43 [doi]
- A 1/2.5-inch 8Mpixel CMOS image sensor with a staggered shared-pixel architecture and an FD-boost operationNagataka Tanaka, Junji Naruse, Akiko Mori, Ryuta Okamoto, Hirofumi Yamashita, Makoto Monoi. 44-45 [doi]
- An SoC combining a 132dB QVGA pixel array and a 32b DSP/MCU processor for vision applicationsPierre-François Ruedi, Pascal Heim, Steve Gyger, François Kaess, Claude Arm, Ricardo Caseiro, Jean-Luc Nagel, Silvio Todeschini. 46-47 [doi]
- A charge-multiplication CMOS image sensor suitable for low-light-level imagingRyu Shimizu, Mamoru Arimoto, Hayato Nakashima, Kaori Misawa, Kazuhiro Suzuki, Toshikazu Ohno, Yugo Nose, Keisuke Watanabe, Tatsushi Ohyama, Kuniyuki Tani. 50-51 [doi]
- A dual-conversion-gain video sensor with dewarping and overlay on a single chipAnthony Huggett, Chris Silsby, Sergi Cami, Jeff Beck. 52-53 [doi]
- A 45nm 8-core enterprise Xeon® processorStefan Rusu, Simon Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli. 56-57 [doi]
- A family of 45nm IA processorsRajesh Kumar, Glenn Hinton. 58-59 [doi]
- A chip-stacked memory for on-chip SRAM-rich SoCs and processorsHideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno. 60-61 [doi]
- Dynamic frequency-switching clock system on a quad-core Itanium® processorAndrew Allen, Jay Desai, Frank Verdico, Ferd Anderson, David Mulvihill, Dan Krueger. 62-63 [doi]
- Secure AES engine with a local switched-capacitor current equalizerCarlos Tokunaga, David Blaauw. 64-65 [doi]
- A 4Gb/s/ch 356fJ/b 10mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm CMOSByungsub Kim, Vladimir Stojanovic. 66-67 [doi]
- Dual-DLL-based CMOS all-digital temperature sensor for microprocessor thermal monitoringKyoungho Woo, Scott Meninger, Thucydides Xanthopoulos, Ethan Crain, Dongwan Ha, Donhee Ham. 68-69 [doi]
- Over one million TPCC with a 45nm 6-core Xeon® CPURavi Kuppuswamy, Shankar R. Sawant, Srikanth Balasubramanian, Pradeep Kaushik, Narayanan Natarajan, Jeffrey D. Gilbert. 70-71 [doi]
- A 12b 2.9GS/s DAC with IM3 ≪-60dBc beyond 1GHz in 65nm CMOSChi-Hung Lin, Frank M. L. van der Goes, Jan J. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult. 74-75 [doi]
- A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOSErkan Alpman, Hasnain Lakdawala, L. Richard Carley, Krishnamurthy Soumyanath. 76-77 [doi]
- A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequencyRobert C. Taft, Pier Andrea Francese, Maria Rosaria Tursi, Ols Hidri, Alan MacKenzie, Tobias Hoehn, Philipp Schmitz, Heinz Werker, Andrew Glenny. 78-79 [doi]
- A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOSYing-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang. 80-81 [doi]
- A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalizationWenbo Liu, Yuchun Chang, Szukang Hsien, Bo-Wei Chen, Yung-Pin Lee, Wen Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu. 82-83 [doi]
- A 10b 500MHz 55mW CMOS ADCAshutosh Verma, Behzad Razavi. 84-85 [doi]
- A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADCSiddharth Devarajan, Larry Singer, Dan Kelly, Steven Decker, Abhishek Kamath, Paul Wilkins. 86-87 [doi]
- A 7.1mW 10GHz all-digital frequency synthesizer with dynamically reconfigurable digital loop filter in 90nm CMOSSong-Yu Yang, Wei-Zen Chen. 90-91 [doi]
- Subharmonically injection-locked PLLs for ultra-low-noise clock generationJri Lee, Huaide Wang, Wen Tsao Chen, Yung-Pin Lee. 92-93 [doi]
- Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applicationsAlexander Rylyakov, José A. Tierno, Herschel A. Ainspan, Jean-Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak Deniz, Daniel J. Friedman. 94-95 [doi]
- 0.9mW 7GHz and 1.6mW 60GHz frequency dividers with locking-range enhancement in 0.13µm CMOSSujiang Rong, Alan W. L. Ng, Howard C. Luong. 96-97 [doi]
- 2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOSKyu-hyoun Kim, Daniel M. Dreps, Frank D. Ferraiolo, Paul W. Coteus, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman. 98-99 [doi]
- A 14mW 5Gb/s CMOS TIA with gain-reuse regulated cascode compensation for parallel optical interconnectsSushmit Goswami, Jason Silver, Tino Copani, Wenjian Chen, Hugh J. Barnaby, Bert Vermeire, Sayfe Kiaei. 100-101 [doi]
- A 4Gb/s current-mode optical transceiver in 0.18µm CMOSJisook Yun, Mikyung Seo, Boo-Young Choi, Jung-Won Han, Yunsung Eo, Sung Min Park. 102-103 [doi]
- Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuitJun Terada, Yusuke Ohtomo, Kazuyoshi Nishimura, Hiroaki Katsurai, Shunji Kimura, Naoto Yoshimoto. 104-105 [doi]
- CMOS optical 4-PAM VCSEL driver with modal-dispersion equalizer for 10Gb/s 500m MMF transmissionDaisuke Watanabe, Atsushi Ono, Toshiyuki Okayasu. 106-107 [doi]
- A VDSL2 CPE AFE in 0.15µm CMOS with integrated line driverGiovanni Cesura, Alessandro Bosi, Francesco Rezzi, Rinaldo Castello, Jenkin Chan, SaiBun Wong, Chi Fan Yung, Ovidiu Carnu, Thomas Cho. 108-109 [doi]
- An integrated closed-loop polar transmitter with saturation prevention and low-IF receiver for quad-band GPRS/EDGERajasekhar Pullela, Shahrzad Tadjpour, Dmitriy Rozenblit, William Domino, Thomas Obkircher, Mohamed El-Said, Bala Ramachandran, Tirdad Sowlati, Darioush Agahi, Wei-Hong Chen, Dean A. Badillo, Masoud Kahrizi, Jaleh Komaili, Stephane Wloczysiak, Utku Seckin, Yunyoung Choi, Hasan Akyol, Martin Vadkerti, Amir Mahjoob, Hamid Firouzkouhi, Dan Shum, Rajendra Suhanthan, Nooshin Vakilian, Tom Valencia, Christophe Dantec, Aaron Paff, Mona Ahooie. 112-113 [doi]
- A SAW-less multiband WEDGE receiverOlivier Gaborieau, Sven Mattisson, Nikolaus Klemmer, Bassem Fahs, Fabio T. Braz, Richard Gudmundsson, Thomas Mattsson, Carine Lascaux, Christophe Trichereau, Wen Suter, Eric Westesson, Andreas Nydahl. 114-115 [doi]
- Single-chip multiband WCDMA/HSDPA/HSUPA/EGPRS transceiver with diversity receiver and 3G DigRF interface without SAW filters in transmitter / 3G receiver pathsTirdad Sowlati, Bipul Agarwal, J. Cho, Thomas Obkircher, Mohamed El-Said, John Vasa, Bala Ramachandran, Masoud Kahrizi, Elias Dagher, Wei-Hong Chen, Martin Vadkerti, Georgi Taskov, Utku Seckin, Hamid Firouzkouhi, Behzad Saeidi, Hasan Akyol, Yunyoung Choi, Amir Mahjoob, Sandeep D'Souza, Chieh-Yu Hsieh, David Guss, Dan Shum, Dean A. Badillo, Imtiyaz Ron, Doris Ching, Feng Shi, Yong He, Jaleh Komaili, Aravind Loke, Rajasekhar Pullela, Engin Pehlivanoglu, Hossein Zarei, Shahrzad Tadjpour, Darioush Agahi, Dmitriy Rozenblit, William Domino, Gregory Williams, Nader Damavandi, Stephane Wloczysiak, Suhanthan Rajendra, Aaron Paff, Tom Valencia. 116-117 [doi]
- Single-chip RF CMOS UMTS/EGSM transceiver with integrated receive diversity and GPSAristotele Hadjichristos, Marco Cassia, Hong-sun Kim, C. H. Park, Kevin Wang, W. Zhuo, Bahman Ahrari, Roger Brockenbrough, J. Chen, C. Donovan, R. Jonnalagedda, J. Kim, Jin-Su Ko, Hee Choul Lee, Sang Oh Lee, Emilia Lei, T. Nguyen, T. Pan, S. Sridhara, W. Su, H. Yan, J. Yang, Cormac Conroy, Charles Persico, Kamal Sahota, B. Kim. 118-119 [doi]
- A 45nm low-power SAW-less WCDMA transmit modulator using direct quadrature voltage modulationXin He, Jan van Sinderen. 120-121 [doi]
- An embedded 65nm CMOS low-IF 48MHz-to-1GHz dual tuner for DOCSIS 3.0Francesco Gatta, Ray Gomez, Young Shin, Takayuki Hayashi, Hanli Zou, James Y. C. Chang, Leonard Dauphinee, Jianhong Xiao, Dave S.-H. Chang, Tai-Hong Chih, Massimo Brandolini, Dongsoo Koh, Bryan Juo-Jung Hung, Tao Wu, Mattia Introini, Giuseppe Cusmai, Loke Tan, Bruce Currivan, Lin He, Peter Cangiane, Pieter Vorenkamp. 122-123 [doi]
- 2 mobile ISDB-T tuner in 0.13µm CMOSYi-Ti Huang, C. M. Yang, S. C. Huang, H. L. Pan, T. C. Hung. 124-125 [doi]
- 2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architectureYongsam Moon, Yong-Ho Cho, Hyun Bae Lee, Byung-Hoon Jeong, Seok-Hun Hyun, Byungchul Kim, In-Chul Jeong, Seong-Young Seo, Junho Shin, Seok-Woo Choi, Ho-Sung Song, Jung Hwan Choi, Kyehyun Kyung, Young-Hyun Jun, Kinam Kim. 128-129 [doi]
- 8Gb 3D DDR3 DRAM using through-silicon-via technologyUksong Kang, Hoeju Chung, Seongmoo Heo, Soon-Hong Ahn, Hoon Lee, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jin-Ho Kim, Jaewook Lee, Han Sung Joo, Woo-Seop Kim, Hyun-Kyung Kim, Eun-Mi Lee, So-Ra Kim, Keum-Hee Ma, Dong Hyun Jang, Nam-Seog Kim, Man-Sik Choi, Sae-Jang Oh, Jung-Bae Lee, Tae-Kyung Jung, Jei-Hwan Yoo, Changhyun Kim. 130-131 [doi]
- A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile applicationBong Hwa Jeong, Jongwon Lee, Yin Jae Lee, Tae Jin Kang, Joo-Hyeon Lee, Duck Hwa Hong, Jae-Hoon Kim, Eun Ryeong Lee, Min Chang Kim, Kyung Ha Lee, Sang Il Park, Jong Ho Son, Sang-Kwon Lee, Seong Nyuh Yoo, Sung Mook Kim, Tae Woo Kwon, Jin-Hong Ahn, Yong Tak Kim. 132-133 [doi]
- 75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniquesRex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein. 134-135 [doi]
- Single-ended transceiver design techniques for 5.33Gb/s graphics applicationsHamid Partovi, Karthik Gopalakrishnan, Luca Ravezzi, Russell Homer, Otto Schumacher, Reinhold Unterricker, Werner Kederer. 136-137 [doi]
- A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfacesKyung-Soo Ha, Lee-Sup Kim, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim. 138-139 [doi]
- A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOSHyun-Woo Lee, Won-Joo Yun, Young-Kyoung Choi, Hyang-Hwa Choi, Jong Jin Lee, Ki-Han Kim, Shin-Deok Kang, Ji-Yeon Yang, Jae-Suck Kang, Hyeng-Ouk Lee, Dong Uk Lee, Sujeong Sim, Young-Ju Kim, Won Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyung-Wook Moon, Seung-Wook Kwack, Jung Woo Lee, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung. 140-141 [doi]
- Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arraysSatoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh. 142-143 [doi]
- An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supplyYu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha. 146-147 [doi]
- A versatile recognition processor employing Haar-like feature and cascaded classifierYuya Hanai, Yuichi Hori, Jun Nishimura, Tadahiro Kuroda. 148-149 [doi]
- A 201.4GOPS 496mW real-time multi-object recognition processor with bio-inspired neural perception engineJoo-Young Kim, Minsu Kim, Seungjin Lee, Jinwook Oh, Kwanho Kim, Sejong Oh, Jeong-Ho Woo, Donghyun Kim, Hoi-Jun Yoo. 150-151 [doi]
- A multi-format Blu-ray player SoC in 90nm CMOSChi-Cheng Ju, Tsu-Ming Liu, Chih-Chieh Yang, Shih-Hung Lin, Kuo-Pin Lan, Chien-Hua Wu, Ting-Hsun Wei, Chi-Chin Lien, Jiun-Yuan Wu, Chih-Hao Hsiao, Te-Wei Chen, Yeh-Lin Chu, Guan-Yi Lin, Yung-Chang Chang, Kung-Sheng Lin, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Chien-Hung Lin, Yung-Teng Lin, Shang-Ming Lee, Ya-Ching Yang, Yu-Lun Cheng, Chen-Chia Lee, Ming-Shiang Lai, Wen-Hua Wu, T. Hu, Chao-Wei Tseng, Chen-Yu Hsiao, Wei-Liang Lee, Bo-Jiun Chen, Pao-Cheng Chiu, Shang-Ping Chen, Kun-Hsien Li, Kuan-Hua Chao, Chien-Ming Chen, Chuan-Cheng Hsiao, J. Ju, Wei-Hung Huang, Chi-Hui Wang, Hung-Sung Li, E. Su, J. Chen. 152-153 [doi]
- A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applicationsLi-Fu Ding, Wei-Yin Chen, Pei-Kuei Tsung, Tzu-Der Chuang, Hsu-Kuang Chiu, Yu-Han Chen, Pai-Heng Hsiao, Shao-Yi Chien, Tung-Chien Chen, Ping-Chih Lin, Chia-Yu Chang, Liang-Gee Chen. 154-155 [doi]
- A 45nm single-chip application-and-baseband processor using an intermittent operation techniqueMotoyasu Shirasaki, Yusaku Miyazaki, Masahiro Hoshaku, Hiroo Yamamoto, Sachio Ogawa, Takuya Arimura, Hiroshi Hirai, Yasuo Iizuka, Tsutomu Sekibe, Yoichi Nishida, Toshiyuki Ishioka, Junji Michiyama. 156-157 [doi]
- A 342mW mobile application processor with full-HD multi-standard video codecKenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori. 158-159 [doi]
- A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital harmonic distortion correctionAndrea Panigada, Ian Galton. 162-163 [doi]
- A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18µm CMOS using capacitive charge-pumpsImran Ahmed, Jan Mulder, David A. Johns. 164-165 [doi]
- A 12b 50MS/s fully differential zero-crossing-based ADC without CMFBLane Brooks, Hae-Seung Lee. 166-167 [doi]
- 2 PPM ADC in 90nm digital CMOSShahrzad Naraghi, Matthew Courcy, Michael P. Flynn. 168-169 [doi]
- A 0.13µm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based integrator and quantizerMin C. Park, Michael H. Perrott. 170-171 [doi]
- 2 CT ΔΣ ADC with -97.7dBc THD and 80dB DR using low-latency DEMSheng-Jui Huang, Yung-Yu Lin. 172-173 [doi]
- A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback elementVijay Dhanasekaran, Manisha Gambhir, Mohamed M. Elsayed, Edgar Sánchez-Sinencio, José Silva-Martínez, Chinmaya Mishra, Lei Chen, Erik Pankratz. 174-175 [doi]
- A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOSLynn Bos, Gerd Vandersteen, Julien Ryckaert, Pieter Rombouts, Yves Rolain, Geert Van der Plas. 176-177 [doi]
- A Scalable 3.6-to-5.2mW 5-to-10Gb/s 4-tap DFE in 32nm CMOSLidong Chen, Xuguang Zhang, Fulvio Spagna. 180-181 [doi]
- A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOSYong Liu, Byungsub Kim, Timothy O. Dickson, John F. Bulzacchelli, Daniel J. Friedman. 182-183 [doi]
- A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rateSeon-Kyoo Lee, Young Sang Kim, Hyunsoo Ha, Young Hun Seo, Hong June Park, Jae-Yoon Sim. 184-185 [doi]
- st-order ΔΣ modulatorKoji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Tatsuya Saito. 186-187 [doi]
- A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive controlYasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone. 188-189 [doi]
- A 250Mb/s-to-3.4Gb/s HDMI receiver with adaptive loop updating frequencies and an adaptive equalizerYan-Bin Luo, Ping Chen, Qui-Ting Chen, Chih-Yong Wang, Chan-Hao Chang, Szu-Jui Fu, Chien-Ming Chen, Hung-Sung Li. 190-191 [doi]
- A 2.0Gb/s clock-embedded interface for full-HD 10b 120Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recoveryKoichi Yamaguchi, Yoshihiko Hori, Keiichi Nakajima, Kazumasa Suzuki, Masayuki Mizuno, Hiroshi Hayama. 192-193 [doi]
- A GHz spintronic-based RF oscillatorPierre Vincent, Marie-Claire Cyrille, Bernard Viala, Bertrand Delaet, Jean-Philippe Michel, Patrick Villard, Jérôme Prouvée, Dimitri Houssameddine, Ursula Ebels, Jordan A. Katine, Daniele Mauri, Sylvia Florez, Ozhan Ozatay, Liesl Folks, Bruce D. Terris, Franck Badets. 196-197 [doi]
- A remote-powered RFID tag with 10Mb/s UWB uplink and -18.5dBm sensitivity UHF downlink in 0.18µm CMOSMajid Baghaei Nejad, David S. Mendoza, Zhuo Zou, Soheil Radiom, Georges G. E. Gielen, Li-Rong Zheng, Hannu Tenhunen. 198-199 [doi]
- A pulsed UWB receiver SoC for insect motion controlDenis C. Daly, Patrick P. Mercier, Manish Bhardwaj, Alice L. Stone, Joel Voldman, Richard B. Levine, John G. Hildebrand, Anantha P. Chandrakasan. 200-201 [doi]
- Towards terahertz operation of CMOSSwaminathan Sankaran, Chuying Mao, Eunyoung Seok, Dongha Shim, Changhua Cao, Ruonan Han, Daniel J. Arenas, David B. Tanner, Stephen Hill, Chih-Ming Hung, Kenneth K. O. 202-203 [doi]
- A 2.75mW wideband correlation-based transceiver for body-coupled communicationAlberto Fazzi, Sotir Ouzounov, John van den Homberg. 204-205 [doi]
- A 128b organic RFID transponder chip, including Manchester encoding and ALOHA anti-collision protocol, operating with a data rate of 1529b/sKris Myny, Monique J. Beenhakkers, Nick A. J. M. van Aerle, Gerwin H. Gelinck, Jan Genoe, Wim Dehaene, Paul Heremans. 206-207 [doi]
- Organic CMOS circuits for RFID applicationsRobert Blache, Jürgen Krumm, Walter Fix. 208-209 [doi]
- Silicon-resonator-based, 3µA real-time clock with ±5ppm frequency accuracyDavid Ruffieux, Aurélie Pezous, Anne-Claire Pliska, François Krummenacher. 210-211 [doi]
- A 500µW neural tag with 2µVrms AFE and frequency-multiplying MICS/ISM FSK transmitterShailesh Rai, Jeremy Holleman, Jagdish Nayayan Pandey, Fan Zhang, Brian P. Otis. 212-213 [doi]
- A low-noise active balun with IM2 cancellation for multiband portable DVB-H receiversDaniele Mastantuono, Danilo Manstretta. 216-217 [doi]
- A 3.6mW differential common-gate CMOS LNA with positive-negative feedbackSanghyun Woo, Woonyun Kim, Chang-Ho Lee, Kyutae Lim, Joy Laskar. 218-219 [doi]
- A compact low-noise weighted distributed amplifier in CMOSYu-Jiu Wang, Ali Hajimiri. 220-221 [doi]
- A 0.2-to-2.0GHz 65nm CMOS receiver without LNA achieving ≫11dBm IIP3 and ≪6.5 dB NFMichiel C. M. Soer, Eric A. M. Klumperink, Zhiyu Ru, Frank E. van Vliet, Bram Nauta. 222-223 [doi]
- A 0.6V 380µW -14dBm LO-input 2.4GHz double-balanced current-reusing single-gate CMOS mixer with cyclic passive combinerJun Deguchi, Daisuke Miyashita, Mototsugu Hamada. 224-225 [doi]
- A 4.75GHz fractional frequency divider with digital spur calibration in 45nm CMOSStefano Pellerano, Paolo Madoglio, Yorgos Palaskas. 226-227 [doi]
- A 0.75V 325µW 40dB-SFDR frequency-hopping synthesizer for wireless sensor networks in 90nm CMOSEmanuele Lopelli, Johan van der Tang, Kathleen Philips, Arthur H. M. van Roermund, Bert Gyselinckx. 228-229 [doi]
- A software-defined radio receiver architecture robust to out-of-band interferenceZhiyu Ru, Eric A. M. Klumperink, Gerard Wienk, Bram Nauta. 230-231 [doi]
- A 400-to-900 MHz receiver with dual-domain harmonic rejection exploiting adaptive interference cancellationNiels A. Moseley, Zhiyu Ru, Eric A. M. Klumperink, Bram Nauta. 232-233 [doi]
- 2 32Gb MLC NAND flash memory in 34nm CMOSRaymond Zeng, Navneet Chalagalla, Dan Chu, Daniel Elmhurst, Matt Goldman, Chris Haid, Atif Huq, Takaaki Ichikawa, Joel Jorgensen, Owen Jungroth, Nishnat Kajla, Ravinder Kajley, Koichi Kawai, Jiro Kishimoto, Ali Madraswala, Tetsuji Manabe, Vikram Mehta, Midori Morooka, Katie Nguyen, Yoko Oikawa, Bharat Pathak, Rod Rozman, Tom Ryan, Andy Sendrowski, William Sheung, Martin Szwarc, Yasuhiro Takashima, Satoru Tamada, Toru Tanzawa, Tomoharu Tanaka, Mase Taub, Darshak Udeshi, Sjigekazu Yamada, Hiroyuki Yokoyama. 236-237 [doi]
- A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSDKoichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi. 238-239 [doi]
- A 48nm 32Gb 8-level NAND flash memory with 5.5MB/s program throughputSeung-Ho Chang, Sok-Kyu Lee, Seong Je Park, Min-Joong Jung, Jung-Chul Han, In-Soo Wang, Kyu-Hee Lim, Jung Hwan Lee, Ji-Hwan Kim, Won-Kyung Kang, Tai-Kyu Kang, Hee-Su Byun, Yujong Noh, Lee-Hyun Kwon, Bon-Kwang Koo, Myung Cho, Joong-Seob Yang, Yo-Hwan Koh. 240-241 [doi]
- A 113mm2 32Gb 3b/cell NAND flash memoryTakuya Futatsuyama, Norihiro Fujita, Naoya Tokiwa, Yoshihiko Shindo, Toshiaki Edahiro, Teruhiko Kamei, Hiroaki Nasu, Makoto Iwai, Koji Kato, Yasuyuki Fukuda, Naoaki Kanagawa, Naofumi Abiko, Masahide Matsumoto, Toshihiko Himeno, Toshifumi Hashimoto, Yi-Ching Liu, Hardwell Chibvongodze, Takamitsu Hori, Manabu Sakai, Hong Ding, Yoshiharu Takeuchi, Hitoshi Shiga, Norifumi Kajimura, Yasuyuki Kajitani, Kiyofumi Sakurai, Kosuke Yanagidaira, Toshihiro Suzuki, Yuko Namiki, Tomofumi Fujimura, Man Mui, Hao Nguyen, Seungpil Lee, Alex Mak, Jeffery Lutze, Tooru Maruyama, Toshiharu Watanabe, Takahiko Hara, Shigeo Ohshima. 242-243 [doi]
- A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stackingYasufumi Sugimori, Yoshinori Kohama, Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda. 244-245 [doi]
- A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOSCuong Trinh, Noboru Shibata, Takeshi Nakano, Mikio Ogawa, Jumpei Sato, Yoshikazu Takeyama, Katsuaki Isobe, Binh Le, Farookh Moogat, Nima Mokhlesi, Kenji Kozakai, Patrick Hong, Teruhiko Kamei, Kiyoaki Iwasa, J. Nakai, Takahiro Shimizu, Mitsuaki Honma, Shintaro Sakai, Toshimasa Kawaai, Satoru Hoshi, Jonghak Yuh, Cynthia Hsu, Taiyuan Tseng, Jason Li, Jayson Hu, M. Liu, Shahzad Khalid, J. Chen, Mitsuyuki Watanabe, Hung-Szu Lin, Junhui Yang, K. McKay, Khanh Nguyen, Tuan Pham, Y. Matsuda, K. Nakamura, K. Kanebako, S. Yoshikawa, W. Igarashi, A. Inoue, T. Takahashi, Y. Komatsu, C. Suzuki, K. Kanazawa, Masaaki Higashitani, Seungpil Lee, T. Murai, K. Nguyen, James Lan, Sharon Huynh, M. Murin, M. Shlick, M. Lasser, Raul Cernea, Mehrdad Mofidi, K. Schuegraf, Khandker Quader. 246-247 [doi]
- A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOSCuong Trinh, Noboru Shibata, Takeshi Nakano, Mikio Ogawa, Jumpei Sato, Yoshikazu Takeyama, Katsuaki Isobe, Binh Le, Farookh Moogat, Nima Mokhlesi, Kenji Kozakai, Patrick Hong, Teruhiko Kamei, Kiyoaki Iwasa, J. Nakai, Takahiro Shimizu, Mitsuaki Honma, Shintaro Sakai, Toshimasa Kawaai, Satoru Hoshi, Jonghak Yuh, Cynthia Hsu, Taiyuan Tseng, Jason Li, Jayson Hu, M. Liu, Shahzad Khalid, J. Chen, Mitsuyuki Watanabe, Hung-Szu Lin, Junhui Yang, K. McKay, Khanh Nguyen, Tuan Pham, Y. Matsuda, K. Nakamura, K. Kanebako, S. Yoshikawa, W. Igarashi, A. Inoue, T. Takahashi, Y. Komatsu, C. Suzuki, K. Kanazawa, Masaaki Higashitani, Seungpil Lee, T. Murai, K. Nguyen, James Lan, Sharon Huynh, M. Murin, M. Shlick, M. Lasser, Raul Cernea, Mehrdad Mofidi, K. Schuegraf, Khandker Quader. 246-247 [doi]
- A reconfigurable, 0.13µm CMOS 110pJ/pulse, fully integrated IR-UWB receiver for communication and sub-cm rangingMarian Verhelst, Nick Van Helleputte, Georges G. E. Gielen, Wim Dehaene. 250-251 [doi]
- A 0.55V 16Mb/s 1.6mW non-coherent IR-UWB digital baseband with ±1ns synchronization accuracyPatrick P. Mercier, Manish Bhardwaj, Denis C. Daly, Anantha P. Chandrakasan. 252-253 [doi]
- A 110nm RFCMOS GPS SoC with 34mW -165dBm tracking sensitivityJ.-M. Wei, C.-N. Chen, K.-T. Chen, C.-F. Kuo, B. H. Ong, C.-H. Lu, C. C. Liu, H.-C. Chiou, H. C. Yeh, J.-H. Shieh, K. S. Huang, K.-I. Li, M.-J. Wu, M.-H. Li, S.-H. Chou, S.-L. Chew, W. L. Lien, W.-G. Yau, W.-Z. Ge, W. C. Lai, W.-H. Ting, Y. J. Tsai, Y. C. Yen, Y.-C. Yeh. 254-255 [doi]
- A 0.13µm CMOS 655Mb/s 4×4 64-QAM K-Best MIMO detectorMahdi Shabany, P. Glenn Gulak. 256-257 [doi]
- A 1GHz digital channel multiplexer for satellite OutDoor Unit based on a 65nm CMOS transceiverPierre Busson, Nitin Chawla, Jérôme Bach, Stéphane Le Tual, Harvinder Singh, Vineet Gupta, Pascal Urard. 258-259 [doi]
- A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOSHimanshu Kaul, Mark Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar. 260-261 [doi]
- A piecewise-linear 10b DAC architecture with drain-current modulation for compact AMLCD driver ICsYong-Joon Jeon, Hyung-Min Lee, Sungwoo Lee, Gyu-Hyeong Cho, Hyoung-rae Kim, Yoon Kyung Choi, Myunghee Lee. 264-265 [doi]
- A 10b column driver with variable-current-control interpolation for mobile active-matrix LCDsHyung-Min Lee, Yong-Joon Jeon, Sungwoo Lee, Gyu-Hyeong Cho, Hyoung-rae Kim, Yoon Kyung Choi, Myunghee Lee. 266-267 [doi]
- A 0.1e- vertical FPN 4.7e- read noise 71dB DR CMOS image sensor with 13b column-parallel single-ended cyclic ADCsJong Ho Park, Satoshi Aoyama, Takashi Watanabe, Tomoyuki Akahori, Tomohiko Kosugi, Keigo Isobe, Yuichi Kaneko, Zheng Liu, Kazuki Muramatsu, Takeshi Matsuyama, Takeshi Kawahito. 268-269 [doi]
- A digital driving technique for an 8b QVGA AMOLED display using ΔΣ modulationJae-Hyuk Jang, Minho Kwon, Edwin Tjandranegara, Kywro Lee, Byunghoo Jung. 270-271 [doi]
- An 18Gb/s duobinary receiver with a CDR-assisted DFEKazuhisa Sunaga, Hideyuki Sugita, Koichi Yamaguchi, Kazumasa Suzuki. 274-275 [doi]
- A 43.7mW 96GHz PLL in 65nm CMOSKun-Hung Tsai, Shen-Iuan Liu. 276-277 [doi]
- An array of 4 complementary LC-VCOs with 51.4% W-Band coverage in 32nm SOI CMOSDaeik D. Kim, Jonghae Kim, Choongyeun Cho, Jean-Olivier Plouchart, Mahender Kumar, Woo-Hyeong Lee, Ken Rim. 278-279 [doi]
- A mm-wave CMOS multimode frequency dividerHsien-Ku Chen, Hsien-Jui Chen, Da-Chiang Chang, Ying-Zong Juang, Yu-Che Yang, Shey-Shi Lu. 280-281 [doi]
- A 128.24-to-137.00GHz injection-locked frequency divider in 65nm CMOSBo-Yu Lin, Kun-Hung Tsai, Shen-Iuan Liu. 282-283 [doi]
- A robust wireless sensor node for in-tire-pressure monitoringMartin Flatscher, Markus Dielacher, Thomas Herndl, Thomas Lentsch, Rainer Matischek, Josef Prainsack, Wolfgang Pribyl, Horst Theuss, Werner Weber. 286-287 [doi]
- A release-on-demand wireless CMOS drug delivery SoC based on electrothermal activation techniqueYao-Joe Yang, Yu-Jie Huang, Hsin-Hung Liao, Tao Wang, Pen-Li Huang, Chii-Wann Lin, Yao-Hong Wang, Shey-Shi Lu. 288-289 [doi]
- A 5.2mW self-configured wearable body sensor network controller and a 12µW 54.9% efficiency wirelessly powered sensor for continuous health monitoring systemJerald Yoo, Long Yan, Seulki Lee, Yongsang Kim, Hyejung Kim, Binhee Kim, Hoi-Jun Yoo. 290-291 [doi]
- An integrated power supply system for low-power 3.3V electronics using on-chip polymer electrolyte membrane (PEM) fuel cellsMirko Frank, Matthias Kuhl, Gilbert Erdler, Ingo Freund, Yiannos Manoli, Claas Müller, Holger Reinecke. 292-293 [doi]
- A mm-sized implantable power receiver with adaptive link compensationStephen O'Driscoll, Ada S. Y. Poon, Teresa H. Meng. 294-295 [doi]
- An efficient piezoelectric energy-harvesting interface circuit using a bias-flip rectifier and shared inductorYogesh K. Ramadass, Anantha P. Chandrakasan. 296-297 [doi]
- An energy-aware multiple-input power supply with charge recovery for energy harvesting applicationsNathaniel J. Guilar, Rajeevan Amirtharajah, Paul J. Hurst, Stephen H. Lewis. 298-299 [doi]
- Integrated capacitive power-management circuit for thermal harvesters with output power 10 to 1000µWInge Doms, Patrick Merken, Robert Mertens, Chris Van Hoof. 300-301 [doi]
- 3-sized microrobotRaimon Casanova, Ángel Dieguez, Anna Arbat, Oscar Alonso, Andreu Sanuy, Joan Canals, Josep Samitier. 302-303 [doi]
- A fully integrated 24GHz UWB radar sensor for automotive applicationsEgidio Ragonese, Angelo Scuderi, Vittorio Giammello, Ettore Messina, Giuseppe Palmisano. 306-307 [doi]
- A single-chip dual-band 22-to-29GHz/77-to-81GHz BiCMOS transceiver for automotive radarsVipul Jain, Fred Tzeng, Lei Zhou, Payam Heydari. 308-309 [doi]
- A 77GHz transceiver in 90nm CMOSYoichi Kawano, Toshihide Suzuki, Masaru Sato, Tatsuya Hirose, Kazukiyo Joshin. 310-311 [doi]
- A 1.1nJ/b 802.15.4a-compliant fully integrated UWB transceiver in 0.13µm CMOSDavid Lachartre, Benoît Denis, Dominique Morche, Laurent Ouvry, Manuel Pezzin, Bernard Piaget, Jérôme Prouvée, Pierre Vincent. 312-313 [doi]
- A 90nm CMOS low-power 60GHz transceiver with integrated baseband circuitryCristian Marcu, Debopriyo Chowdhury, Chintan Thakkar, Lingkai Kong, Maryam Tabesh, Jung-Dong Park, Yanjie Wang, Bagher Afshar, Abhinav Gupta, Amin Arbabian, Simone Gambini, Reza Zamani, Ali M. Niknejad, Elad Alon. 314-315 [doi]
- A low-power fully integrated 60GHz transceiver system with OOK modulation and on-board antenna assemblyJri Lee, Yenlin Huang, Yentso Chen, Hsinchia Lu, Chiajung Chang. 316-317 [doi]
- A 2.88Gb/s digital hopping UWB transceiverAkio Tanaka, Keiichi Numata, Hiroshi Kodama, Hiromu Ishikawa, Naoki Oshima, Hitoshi Yano. 318-319 [doi]
- A chopper current-feedback instrumentation amplifier with a 1mHz 1/ƒ noise corner and an AC-coupled ripple-reduction loopRong Wu, Kofi A. A. Makinwa, Johan H. Huijsing. 322-323 [doi]
- A 140dB-CMRR current-feedback instrumentation amplifier employing ping-pong auto-zeroing and choppingMichiel A. P. Pertijs, Wilko J. Kindt. 324-325 [doi]
- A 150pW program-and-hold timer for ultra-low-power sensor platformsYu-Shiang Lin, Dennis Sylvester, David T. Blaauw. 326-327 [doi]
- A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47µW at 0.6VBernhard Goll, Horst Zimmermann. 328-329 [doi]
- A 25mA 0.13µm CMOS LDO regulator with power-supply rejection better than -56dB up to 10MHz using a feedforward ripple-cancellation techniqueMohamed El-Nozahi, Ahmed Amer, Joselyn Torres, Kamran Entesari, Edgar Sánchez-Sinencio. 330-331 [doi]
- A sub-1V bandgap voltage reference in 32nm FinFET technologyAnne-Johan Annema, Paul Veldhorst, Gerben Doornbos, Bram Nauta. 332-333 [doi]
- A 90nm CMOS CT BPF for Bluetooth transceivers with DT 1b-switched-resistor cutoff-frequency controlHideaki Majima, Mototsugu Hamada. 334-335 [doi]
- A 1.25mW 75dB-SFDR CT filter with in-band noise reductionAntonio Liscidini, Alberto Pirola, Rinaldo Castello. 336-337 [doi]
- A 1.05V 1.6mW 0.45°C 3σ-resolution ΔΣ-based temperature sensor with parasitic-resistance compensation in 32nm CMOSY. William Li, Hasnain Lakdawala, Arijit Raychowdhury, Greg Taylor, K. Soumyanath. 340-341 [doi]
- A CMOS smart temperature sensor with a batch-calibrated inaccuracy of ±0.25°C (3σ) from -70°C to 130°CAndré Luiz Aita, Michiel A. P. Pertijs, Kofi A. A. Makinwa, Johan H. Huijsing. 342-343 [doi]
- An interface for a 300°/s capacitive 2-axis micro-gyroscope with pseudo-CT readoutLasse Aaltonen, Timo Speeti, Mikko Saukoski, Kari Halonen. 344-345 [doi]
- An instrument-on-chip for impedance measurements on nanobiosensors with attoFarad resoutionFabio Gozzini, Giorgio Ferrari, Marco Sampietro. 346-347 [doi]
- 20.5 A Sub-pA ΔΣ Current Amplifier for Single-Molecule NanosensorsMarco Bennati, Federico Thei, Michele Rossi, Marco Crescentini, Gennaro D'Avino, Andrea Baschirotto, Marco Tartagni. 348-349 [doi]
- A compact CMOS MEMS microphone with 66dB SNRJelena Citakovic, Per F. Hovesten, Gino Rocca, Aart van Halteren, Pirmin Rombach, Lars J. Stenberg, Pietro Andreani, Erik Bruun. 350-351 [doi]
- A 2×32 range-finding sensor array with pixel-inherent suppression of ambient light up to 120klxGerald Zach, Horst Zimmermann. 352-353 [doi]
- A 0.25µm logarithmic CMOS imager for emissivity-compensated thermographyFranz X. Hutter, Daniel Brosch, Heinz-Gerd Graf, Wolfram Klingler, Markus Strobel, Joachim N. Burghartz. 354-355 [doi]
- A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systemsYasushi Amamiya, Shunichi Kaeriyama, Hidemi Noguchi, Zin Yamazaki, Tomoyuki Yamase, Ken'ichi Hosoya, Minoru Okamoto, Shiro Tomari, Hiroshi Yamaguchi, Hiroaki Shoda, Hironobu Ikeda, Shinji Tanaka, Tsugio Takahashi, Risato Ohhira, Arihide Noda, Ken'ichiro Hijioka, Akira Tanabe, Sadao Fujita, Nobuhiro Kawahara. 358-359 [doi]
- A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOSKouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker. 360-361 [doi]
- A 40Gb/s full-rate 2: 1 MUX in 0.18µm CMOSAhmad Yazdi, M. M. Green. 362-363 [doi]
- An 80mW 40Gb/s 7-Tap T/2-Spaced FFE in 65nm CMOSAfshin Momtaz, Michael M. Green. 364-365 [doi]
- A 20Gb/s full-rate linear CDR circuit with automatic frequency acquisitionJri Lee, Ke-Chung Wu. 366-367 [doi]
- A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOSJohn F. Bulzacchelli, Timothy O. Dickson, Zeynep Toprak Deniz, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Sergey V. Rylov, Daniel J. Friedman. 368-369 [doi]
- 21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiberJun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz. 370-371 [doi]
- A 0.13µm CMOS power amplifier with ultra-wide instantaneous bandwidth for imaging applicationsJonathan Roderick, Hossein Hashemi. 374-375 [doi]
- An octave-range watt-level fully integrated CMOS switching power mixer array for linearization and back-off efficiency improvementShouhei Kousai, Ali Hajimiri. 376-377 [doi]
- A single-chip highly linear 2.4GHz 30dBm power amplifier in 90nm CMOSDebopriyo Chowdhury, Christopher D. Hull, Ofir B. Degani, Pankaj Goyal, Yanjie Wang, Ali M. Niknejad. 378-379 [doi]
- A 60GHz-band 1V 11.5dBm power amplifier with 11% PAE in 65nm CMOSWei L. Chan, John R. Long, Marco Spirito, John J. Pekarik. 380-381 [doi]
- 50-to-67GHz ESD-protected power amplifiers in digital 45nm LP CMOSKuba Raczkowski, Steven Thijs, Walter De Raedt, Bart Nauwelaers, Piet Wambacq. 382-383 [doi]
- A CMOS adaptive antenna-impedance-tuning IC operating in the 850MHz-to-2GHz bandHang Song, Bertan Bakkaloglu, James T. Aberle. 384-385 [doi]
- A tunable integrated duplexer with 50dB isolation in 40nm CMOSMohyee Mikhemar, Houshang Darabi, Asad A. Abidi. 386-387 [doi]
- A 1MHz-bandwidth type-I ΔΣ fractional-N synthesizer for WiMAX applicationsHiva Hedayati, Bertan Bakkaloglu, Waleed Khalil. 390-391 [doi]
- A 2.2GHz 7.6mW sub-sampling PLL with -126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18µm CMOSXiang Gao, Eric A. M. Klumperink, Mounir Bohsali, Bram Nauta. 392-393 [doi]
- An edge-missing compensator for fast-settling wide-locking-range PLLsTing-Hsu Chien, Chi-Sheng Lin, Ying-Zong Juang, Chun-Ming Huang, Chin-Long Wey. 394-395 [doi]
- A 975-to-1960MHz fast-locking fractional-N synthesizer with adaptive bandwidth control and 4/4.5 prescaler for digital TV tunersLei Lu, Zhichao Gong, Youchun Liao, Hao Min, Zhangwen Tang. 396-397 [doi]
- A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generationXueyi Yu, Woogeun Rhee, Zhihua Wang, Jung-Bae Lee, Changhyun Kim. 398-399 [doi]
- A leakage-suppression technique for phase-locked systems in 65nm CMOSChao-Ching Hung, Shen-Iuan Liu. 400-401 [doi]
- A precision relaxation oscillator with a self-clocked offset-cancellation scheme for implantable biomedical SoCsKunil Choe, Olivier D. Bernal, David Nuttman, Minkyu Je. 402-403 [doi]
- An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltageYusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho. 404-405 [doi]
- 2 0.1-to-5GHz SDR receiver in 45nm digital CMOSVito Giannini, Pierluigi Nuzzo, Charlotte Soens, Kameswaran Vengattaramane, Michiel Steyaert, Julien Ryckaert, Michaël Goffioul, Björn Debaillie, Joris Van Driessche, Jan Craninckx, Mark Ingels. 408-409 [doi]
- A 65nm CMOS inductorless triple-band-group WiMedia UWB PHYDomine Leenaerts, Remco van de Beek, Jos Bergervoet, Harish Kundur, Gerard Van der Weide, Ajay Kapoor, Tian Yan Pu, Yu Fang, Yu-juan Wang, Biju Joseph Mukkada, Hong Sair Lim, Madhu Kiran, Chun Swee Lim, Sorin Badiu, Alan Chang. 410-411 [doi]
- A reconfigurable demodulator with 3-to-5GHz agile synthesizer for 9-band WiMedia UWB in 65nm CMOSAndrea Mazzanti, Mohammad B. Vahidfar, Marco Sosio, Francesco Svelto. 412-413 [doi]
- A highly integrated low-power 2.4GHz transceiver using a direct-conversion diversity receiver in 0.18µm CMOS for IEEE802.15.4 WPANGuido Retz, Hyman Shanan, Kenneth Mulvaney, Kenneth O'Mahony, Miguel Chanca, Pat Crowley, Charley Billon, Kalimuddin Khan, Philip Quinlan. 414-415 [doi]
- A fully integrated 2×2 MIMO dual-band dual- mode direct-conversion CMOS transceiver for WiMAX/WLAN applicationsLi Lin, Naratip Wongkomet, David Yu, Chi-Hung Lin, Ming He, Brian Nissim, Steven Lyuee, Paul Yu, Todd Sepke, Shervin Shekarchian, Luns Tee, Paul Muller, Jonathan Tam, Thomas Cho. 416-417 [doi]
- A 1.1V 5-to-6GHz reduced-component direct-conversion transmit signal path in 45nm CMOSJacques C. Rudell, Pankaj Goyal, Christopher D. Hull, Shmuel Ravid, Adil Kidwai. 418-419 [doi]
- A 2.4GHz 2Mb/s versatile PLL-based transmitter using digital pre-emphasis and auto calibration in 0.18µm CMOS for WPANHyman Shanan, Guido Retz, Kenneth Mulvaney, Philip Quinlan. 420-421 [doi]
- A 7.2mW quadrature GPS receiver in 0.13µm CMOSKuang-Wei Cheng, Karthik Natarajan, David J. Allstot. 422-423 [doi]
- A 10.8mW body-channel-communication/MICS dual-band transceiver for a unified body-sensor-network controllerNamjun Cho, Joonsung Bae, Sunyoung Kim, Hoi-Jun Yoo. 424-425 [doi]
- A wireless and batteryless 130mg 300µW 10b implantable blood-pressure-sensing microsystem for real-time genetically engineered mice monitoringPeng Cong, Nattapon Chaimanonart, Wen H. Ko, Darrin J. Young. 428-429 [doi]
- A wireless IC for time-share chemical and electrical neural recordingMasoud Roham, Paul A. Garris, Pedram Mohseni. 430-431 [doi]
- A flexible clockless 32-ch simultaneous wireless neural recording system with adjustable resolutionMing Yin, Maysam Ghovanloo. 432-433 [doi]
- A biomedical multiprocessor SoC for closed-loop neuroprosthetic applicationsTung-Chien Chen, Kuanfu Chen, Zhi Yang, Kimberly Cockerham, Wentai Liu. 434-435 [doi]
- A CMOS fluorescent-based biosensor microarrayByungchul Jang, Peiyan Cao, Aaron Chevalier, Andrew D. Ellington, Arjang Hassibi. 436-437 [doi]
- A frequency-shift CMOS magnetic biosensor array with single-bead sensitivity and no external magnetHua Wang, Yan Chen, Arjang Hassibi, Axel Scherer, Ali Hajimiri. 438-439 [doi]
- Multiple-output step-up/down switching DC-DC converter with vestigial current controlKyoung-Sik Seol, Young-Jin Woo, Gyu-Hyeong Cho, Gyu-Ha Cho, Jae-Woo Lee, Sung-Il Kim. 442-443 [doi]
- Single-inductor dual-input dual-output buck-boost fuel-cell-li-ion charging DC-DC converter supplySuhwan Kim, Gabriel A. Rincón-Mora. 444-445 [doi]
- Digitally assisted quasi-V2 hysteretic buck converter with fixed frequency and without using large-ESR capacitorFeng Su, Wing-Hung Ki. 446-447 [doi]
- A 20W/channel Class-D amplifier with significantly reduced common-mode radiated emissionsPatrick P. Siniscalchi, Richard K. Hester. 448-449 [doi]
- Two Class-D audio amplifiers with 89/90% efficiency and 0.02/0.03% THD+N consuming less than 1mW of quiescent powerMiguel Angel Rojas González, Edgar Sánchez-Sinencio. 450-451 [doi]
- A 460W Class-D output stage with adaptive gate driveMarco Berkhout. 452-453 [doi]
- A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power managementYih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr. 456-457 [doi]
- 2 Cell in 40nm CMOS using level-programmable wordline driverOsamu Hirabayashi, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Akira Katayama, Gou Fukano, Yuki Fujimura, Takaaki Nakazato, Yasushi Shizuki, Natsuki Kushiyama, Tomoaki Yabe. 458-459 [doi]
- A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technologyAnant Singh, Michael Ciraula, Don Weiss, John Wuu, Philippe Bauser, Paul de Champs, Hamid Daghighian, David Fisch, Philippe Graber, Michel Bron. 460-461 [doi]
- A 90nm 12ns 32Mb 2T1MTJ MRAMRyusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Shinsaku Saito, Yuichi Ito, Sadahiko Miura, Yuko Kato, Kaoru Mori, Yasuaki Ozaki, Yosuke Kobayashi, Norikazu Ohshima, Keizo Kinoshita, Tetsuhiro Suzuki, Kiyokazu Nagahara, Nobuyuki Ishiwata, Katsumi Suemitsu, Shunsuke Fukami, Hiromitsu Hada, Tadahiko Sugibayashi, Naoki Kasai. 462-463 [doi]
- A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemesHidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama. 464-465 [doi]
- Optical I/O technology for tera-scale computingIan A. Young, Edris Mohammed, Jason T. S. Liao, Alexandra M. Kern, Samuel Palermo, Bruce A. Block, Miriam R. Reshotko, Peter L. D. Chang. 468-469 [doi]
- Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testingYoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Tadahiro Kuroda, Masayuki Mizuno. 470-471 [doi]
- A stretchable EMI measurement sheet with 8×8 coil array, 2V organic CMOS decoder, and -70dBm EMI detection circuits in 0.18¼m CMOSKoichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai. 472-473 [doi]
- Field-coupled nanomagnets for interconnect-free nonvolatile computingMarkus Becherer, György Csaba, Rainer Emling, Wolfgang Porod, Paolo Lugli, Doris Schmitt-Landsiedel. 474-475 [doi]
- Chip Scale Camera Module (CSCM) using Through-Silicon-Via (TSV)Hiroshi Yoshikawa, Atsuko Kawasaki, Tomoaki, Iiduka, Yasushi Nishimura, Kazumasa Tanida, Kazutaka Akiyama, Masahiro Sekiguchi, Mie Matsuo, Satoru Fukuchi, Katsutomu Takahashi. 476-477 [doi]
- A subjective-contour generation LSI system with expandable pixel-parallel architecture for vision systemsTakashi Morie, Youngjae Kim. 478-479 [doi]
- An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAMKiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda. 480-481 [doi]
- A 1.1V 150GHz amplifier with 8dB gain and +6dBm saturated output power in standard digital 65nm CMOS using dummy-prefilled microstrip linesMunkyo Seo, Basanth Jagannathan, Corrado Carta, John Pekarik, Luis Chen, C. Patrick Yue, Mark J. W. Rodwell. 484-485 [doi]
- W-band CMOS amplifiers achieving +10dBm saturated output oower and 7.5dB NFDan Sandström, Mikko Varonen, Mikko Kärkkäinen, Kari Halonen. 486-487 [doi]
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