Tomonori Sekiguchi - researchr alias

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Viewing Publication 1 - 18 from 18

2020

A 22-ng/ $\surd$ Hz 17-mW Capacitive MEMS Accelerometer With Electrically Separated Mass Structure and Digital Noise- Reduction TechniquesYuki Furubayashi, Takashi Oshima, Taizo Yamawaki, Keiki Watanabe, Keijiro Mori, Naoki Mori, Akira Matsumoto, Yudai Kamada, Atsushi Isobe, Tomonori Sekiguchi. jssc, 55(9):2539-2552, 2020. [doi]

2019

A 22ng/√Hz 17mW MEMS Accelerometer with Digital Noise-Reduction TechniquesYuki Furubayashi, Takashi Oshima, Taizo Yamawaki, Keiki Watanabe, Keijiro Mori, Naoki Mori, Akira Matsumoto, Hideto Kazama, Yudai Kamada, Atsushi Isobe, Tomonori Sekiguchi. isscc 2019: 182-184 [doi]

2018

Design of Perforated Membrane for Low-Noise Capacitive MEMS AccelerometersAtsushi Isobe, Yudai Kamada, Takashi Oshima, Yuki Furubayashi, Noriyuki Sakuma, Chisaki Takubo, Yasushi Tainaka, Keiki Watanabe, Tomonori Sekiguchi. ieeesensors 2018: 1-4 [doi]

2012

t Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point SensingSatoru Akiyama, Riichiro Takemura, Tomonori Sekiguchi, Akira Kotabe, Kiyoo Itoh. ieicet, 95-C(4):600-608, 2012. [doi]

Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM ArraysAkira Kotabe, Riichiro Takemura, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Kiyoo Itoh. ieicet, 95-C(4):594-599, 2012. [doi]

2011

1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput ComputingTomonori Sekiguchi, Kazuo Ono, Akira Kotabe, Yoshimitsu Yanagawa. jssc, 46(4):828-837, 2011. [doi]

2010

T CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM ArraysAkira Kotabe, Yoshimitsu Yanagawa, Satoru Akiyama, Tomonori Sekiguchi. jssc, 45(11):2348-2355, 2010. [doi]

2009

Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arraysSatoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh. isscc 2009: 142-143 [doi]

2008

Memory at VLSI Circuits SymposiumKiyoo Itoh, Hideaki Kurata, Kenichi Osada, Tomonori Sekiguchi. jssc, 43(4):762-768, 2008. [doi]

2007

Long-Retention-Time, High-Speed DRAM Array with 12-::::F:::::::2::: Twin Cell for Sub 1-V OperationRiichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya, Takayuki Kawahara. ieicet, 90-C(4):758-764, 2007. [doi]

2006

Concordant memory design: an integrated statistical design approach for multi-gigabit DRAMSatoru Akiyama, Tomonori Sekiguchi, Kazuhiko Kajigaya, Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara. jssc, 41(1):107-112, 2006. [doi]

A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-V::::::T:::::: sense amplifiersRiichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi. islped 2006: 123-126 [doi]

2005

A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookupSatoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Tomonori Sekiguchi, Takayuki Kawahara. icc 2005: 1048-1052 [doi]

2002

A low-impedance open-bitline array for multigigabit DRAMTomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura. jssc, 37(4):487-498, 2002. [doi]

2001

A multigigabit DRAM technology with 6F/sup 2/ open-bitline cell, distributed overdriven sensing, and stacked-flash fuseTsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh. jssc, 36(11):1721-1727, 2001. [doi]

1997

The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memoryHiroki Fujisawa, Takeshi Sakata, Tomonori Sekiguchi, Osamu Nagashima, Katsutaka Kimura, Kazuhiko Kajigaya. jssc, 32(5):655-661, 1997. [doi]

1995

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