Masakazu Aoki - researchr alias

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Viewing Publication 1 - 24 from 24

2008

Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity AnalysisMasakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda. ieicet, 91-C(4):647-654, 2008. [doi]

2005

Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an Lsi ChipMasakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda. ieicet, 88-C(5):788-795, 2005. [doi]

Approach for physical design in sub-100 nm eraHiroo Masuda, Shin-ichi Ohkawa, Masakazu Aoki. iscas 2005: 5934-5937 [doi]

Challenge: variability characterization and modeling for 65- to 90-nm processesHiroo Masuda, Shin-ichi Ohkawa, Atsushi Kurokawa, Masakazu Aoki. cicc 2005: 593-599 [doi]

1999

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line schemeHitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura. jssc, 34(8):1084-1090, 1999. [doi]

1998

Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode registerYouji Idei, Katsuhiro Shimohigashi, Masakazu Aoki, Hiromasa Noda, Hidetoshi Iwai, Katsuyuki Sato, Tadashi Tachibana. jssc, 33(2):253-259, 1998. [doi]

1995

1994

A charge recycle refresh for Gb-scale DRAM's in file applicationsTakayulu Kawahara, Yoshiki Kawajiri, Masashi Horiguchi, Takesada Akiba, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki. jssc, 29(6):715-722, June 1994. [doi]

Subthreshold-current reduction circuits for multi-gigabit DRAM'sTakeshi Sakata, Kiyoo Itoh 0001, Masashi Horiguchi, Masakazu Aoki. jssc, 29(7):761-769, July 1994. [doi]

Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM'sTakeshi Sakata, Kiyoo Itoh 0001, Masashi Horiguchi, Masakazu Aoki. jssc, 29(8):887-894, August 1994. [doi]

Sub-1-/spl mu/A dynamic reference voltage generator for battery-operated DRAMsHitoshi Tanaka, Yoshinobu Nakagome, Jun Etoh, Eiji Yamasaki, Masakazu Aoki, Kazuyuki Miyazawa. jssc, 29(4):448-453, April 1994. [doi]

1993

A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arraysTakayuki Kawahara, Takeshi Sakata, Kiyoo Itoh 0001, Yoshiki Kawajiri, Takesada Akiba, Goro Kitsukawa, Masakazu Aoki. jssc, 28(7):816-823, July 1993. [doi]

Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs)Takayuki Kawahara, Masashi Horiguchi, Yoshiki Kawajiri, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki. jssc, 28(11):1136-1144, November 1993. [doi]

Sub-1-V swing internal bus architecture for future low-power ULSIsYoshinobu Nakagome, Kiyoo Itoh 0001, Masanori Isoda, Kan Takeuchi, Masakazu Aoki. jssc, 28(4):414-419, April 1993. [doi]

6 synapse neural networkTakao Watanabe, Katsutaka Kimura, Masakazu Aoki, Takeshi Sakata, Kiyoo Ito. tnn, 4(3):387-393, 1993. [doi]

1991

Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in testMasashi Horiguchi, Masakazu Aoki, Jun Etoh, Gyoo Itoh, Kazuhiko Kajigaya, Atsushi Nozoe, Tetsuro Matsumoto. jssc, 26(11):1544-1549, November 1991. [doi]

A flexible redundancy technique for high-density DRAMsMasashi Horiguchi, Jun Etoh, Masakazu Aoki, Kiyoo Itoh 0001, Tetsuro Matsumoto. jssc, 26(1):12-17, January 1991. [doi]

Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAMYoshinobu Nakagome, Kiyoo Itoh 0001, Kan Takeuchi, Eiji Kume, Hitoshi Tanaka, Masanori Isoda, Tatsunori Musha, Toru Kaga, Teruaki Kisu, Takashi Nishida, Yoshifumi Kawamoto, Masakazu Aoki. jssc, 26(7):1003-1010, July 1991. [doi]

1990

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifierMasashi Horiguchi, Masakazu Aoki, Jun Etoh, Hitoshi Tanaka, Shin'ichi Ikenaga, Kiyoo Itoh 0001, Kazuhiko Kajigaya, Hiroaki Kotani, Kazuyoshi Ohshima, Tetsuro Matsumoto. jssc, 25(5):1129-1135, October 1990. [doi]

1989

A 1.5-V DRAM for battery-based applicationsMasakazu Aoki, Jun Etoh, Kiyoo Itoh 0001, Shin Kimura, Yoshifumi Kawamoto. jssc, 24(5):1206-1212, October 1989. [doi]

New DRAM noise generation under half-V/sub cc/ precharge and its reduction using a transposed amplifierMasakazu Aoki, Shin'ichi Ikenaga, Yoshinobu Nakagome, Masashi Horiguchi, Yasushi Kawase, Yoshifumi Kawamoto, Kiyoo Itoh 0001. jssc, 24(4):889-894, August 1989. [doi]

1988

An experimental large-capacity semiconductor file memory using 16-levels/cell storageMasashi Horiguchi, Masakazu Aoki, Yoshinobu Nakagome, Shin'ichi Ikenaga, Katsuhiro Shimohigashi. jssc, 23(1):27-33, February 1988. [doi]

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2008

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1988

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