Hiroo Masuda - researchr alias

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Viewing Publication 1 - 28 from 28

2010

2009

2008

Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity AnalysisMasakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda. ieicet, 91-C(4):647-654, 2008. [doi]

A Novel Expression of Spatial Correlation by a Random Curved Surface Model and Its Application to LSI DesignShin-ichi Ohkawa, Hiroo Masuda, Yasuaki Inoue. ieicet, 91-A(4):1062-1070, 2008. [doi]

2006

2005

Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an Lsi ChipMasakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda. ieicet, 88-C(5):788-795, 2005. [doi]

Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect ArchitectureAtsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda. isqed 2005: 153-158 [doi]

Dummy Filling Methods for Reducing Interconnect Capacitance and Number of FillsAtsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda. isqed 2005: 586-591 [doi]

Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal FillsAtsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda. ieicet, 88-A(12):3471-3478, 2005. [doi]

Second-Order Polynomial Expressions for On-Chip Interconnect CapacitanceAtsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda. ieicet, 88-A(12):3453-3462, 2005. [doi]

Approach for physical design in sub-100 nm eraHiroo Masuda, Shin-ichi Ohkawa, Masakazu Aoki. iscas 2005: 5934-5937 [doi]

Challenge: variability characterization and modeling for 65- to 90-nm processesHiroo Masuda, Shin-ichi Ohkawa, Atsushi Kurokawa, Masakazu Aoki. cicc 2005: 593-599 [doi]

2004

2003

Approximate formulae approach for efficient inductance extractionAtsushi Kurokawa, Takashi Sato, Hiroo Masuda. aspdac 2003: 143-148 [doi]

Fast On-Chip Inductance Extraction of VLSI Including Angled InterconnectsAtsushi Kurokawa, Kotaro Hachiya, Takashi Sato, Kazuya Tokumasu, Hiroo Masuda. ieiceta, 86-A(4):841-845, 2003. [doi]

Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual InductancesAtsushi Kurokawa, Takashi Sato, Hiroo Masuda. ieiceta, 86-A(12):2933-2941, 2003. [doi]

Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technologyYasuhiko Sasaki, Mitsumasa Sato, Masaru Kuramoto, Fujio Kikuchi, Tsutomu Kawashima, Hiroo Masuda, Kazuo Yano. jssc, 38(5):702-708, 2003. [doi]

Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect DelayTakashi Sato, Hiroo Masuda. isqed 2003: 395-400 [doi]

1998

TCAD/DA for MPU and ASIC DevelopmentHiroo Masuda, Katsumi Tsuneno, Hisako Sato, Kazutaka Mori. aspdac 1998: 129-134

1991

A submicrometer MOS transistor I-V model for circuit simulationHiroo Masuda, Jun ichi Mano, Ryuichi Ikematsu, Hitoshi Sugihara, Yukio Aoki. tcad, 10(2):161-170, 1991. [doi]

1988

MOSTSM: a physically based charge conservative MOSFET modelHiroo Masuda, Yukio Aoki, Jun ichi Mano, Osamu Yamashiro. tcad, 7(12):1229-1236, 1988. [doi]

1987

A New Design-Centering Methodology for VLSI Device DevelopmentYukio Aoki, Hiroo Masuda, Shozo Shimada, Shoji Sato. tcad, 6(3):452-461, 1987. [doi]

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