Yasuhiko Sasaki, Mitsumasa Sato, Masaru Kuramoto, Fujio Kikuchi, Tsutomu Kawashima, Hiroo Masuda, Kazuo Yano. Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology. J. Solid-State Circuits, 38(5):702-708, 2003. [doi]
Abstract is missing.