Table of Contents

• Asymmetric halo CMOSFET to reduce static power dissipation with improved performanceAditya Bansal, Kaushik Roy. 1-4 [doi]
• Limits to performance spread tuning using adaptive voltage and body biasingMaurice Meijer, Francesco Pessolano, José Pineda de Gyvez. 5-8 [doi]
• Adaptive circuit techniques to minimize variation impacts on microprocessor performance and powerJames Tschanz, Siva Narendra, Ali Keshavarzi, Vivek De. 9-12 [doi]
• Device technology for body biasing schemeKiyotaka Imai, Yasushi Yamagata, Sadaaki Masuoka, Naohiko Kimuzuka, Yuri Yasuda, Mitsuhiro Togo, Masahiro Ikeda, Yasutaka Nakashiba. 13-16 [doi]
• Optimum threshold-voltage tuning for low-power, high-performance microprocessorMasayuki Miyazaki, Goichi Ono, Takayuki Kawahara. 17-20 [doi]
• Minimizing power with flexible voltage islandsRuchir Puri, David S. Kung, Leon Stok. 21-24 [doi]
• Robust VLSI architecture for system-on-chip design and its implementation in Viterbi decoderYasuyuki Hatakawa, Shingo Yoshizawa, Yoshikazu Miyanaga. 25-28 [doi]
• A systematic framework for high throughput MAP decoder VLSI architecturesMahmoud Elassal, Ashok Kumar, Magdy Bayoumi. 29-32 [doi]
• System on chip FPGA design of an FM demodulator using a Kalman band-pass sigma-delta architectureSaman S. Abeysekera, Charoensak Charayaphan. 33-36 [doi]
• High level hardware/software communication estimation in shared memory architectureSujan Pandey, Heiko Zimmer, Manfred Glesner, Max Mühlhäuser. 37-40 [doi]
• A novel low-power reconfigurable FFT processorYutian Zhao, Ahmet T. Erdogan, Tughrul Arslan. 41-44 [doi]
• Concentrator access networks for programmable logic cores on SoCsBradley R. Quinton, Steven J. E. Wilton. 45-48 [doi]
• A collision-based model for multi user interference in impulse radio UWB networksMaria-Gabriella Di Benedetto, Guerino Giancola. 49-52 [doi]
• On the acquisition time for serial and parallel code search in UWB impulse radioLuca Reggiani, Gian Mario Maggio. 53-56 [doi]
• Ultra-low power UWB for real time biomedical wireless sensingChun-Yi Lee, Christofer Toumazou. 57-60 [doi]
• Digitizing of UWB signals based on frequency channelizationWon Namgoong, Lei Feng. 61-64 [doi]
• Quasi-cyclic low-density parity-check coded multi-band-OFDM UWB systemsSang-Min Kim, Jun Tang, Keshab K. Parhi. 65-68 [doi]
• A novel covalent redundant binary Booth encoderYajuan He, Chip-Hong Chang, Jiangmin Gu, Hossam A. H. Fahmy. 69-72 [doi]
• A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structureNiichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino. 73-76 [doi]
• A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurabilityJin-Fu Li, Jiunn-Der Yu, Yu-Jen Huang. 77-80 [doi]
• A framework for the design of error-aware power-efficient fixed-width Booth multipliersMin-An Song, Lan-Da Van, Chih-Chyau Yang, Shih-Chieh Chiu, Sy-Yen Kuo. 81-84 [doi]
• A novel multiplexer based truncated array multiplierChip-Hong Chang, Ravi Kumar Satzoda, Swaminathan Sekar. 85-88 [doi]
• A combined two s complement and floating-point comparatorJames E. Stine, Michael J. Schulte. 89-92 [doi]
• A global interconnect optimization algorithm under accurate delay model using solution space smoothingYici Cai, Yibo Wang, Xianlong Hong. 93-96 [doi]
• An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay modelsYiqian Zhang, Xianlong Hong, Yici Cai. 97-100 [doi]
• Zero skew clock routing with tree topology construction using simulated annealing methodXinjie Wei, Yici Cai, Xianlong Hong. 101-104 [doi]
• A sparsified vector potential equivalent circuit model for massively coupled interconnectsHao Yu, Lei He. 105-108 [doi]
• An efficient algorithm for simultaneous wire permutation, inversion, and spacingShanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn. 109-112 [doi]
• Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wiresRuiming Li, Dian Zhou, Jin Liu, Xuan Zeng. 113-116 [doi]
• An electron mobility independent pulse skipping regulator for a programmable CMOS charge pumpAlberto Saiz-Vela, Pedro Luis Miribel-Català, Manuel Puig-Vidal, Josep Samitier. 117-120 [doi]
• High-efficiency control structure for CMOS flash memory charge pumpsChiara Boffino, Alessandro Cabrini, Osama Khouri, Guido Torelli. 121-124 [doi]
• Integration of high voltage charge-pumps in a submicron standard CMOS process for programming analog floating-gate circuitsMark Hooper, Matt Kucic, Paul E. Hasler. 125-128 [doi]
• Optimum quiescent point of integrated power CMOS transistor for wireless portable applicationsHeng-Ming Hsu, Tai-Hsing Lee. 129-132 [doi]
• Design technique of an on-chip, high-voltage charge pump in SOIMohammad R. Hoque, T. Ahmad, Todd McNutt, H. Alan Mantooth, Mohommad M. Mojarradi. 133-136 [doi]
• A monolithic isolation amplifier in silicon-on-insulator CMOSEugenio Culurciello, Philippe O. Pouliquen, Andreas G. Andreou, Kim Strohbehn, Steven E. Jaskulek. 137-140 [doi]
• A specific integrated controller for nanomicroscopy and cellular manipulationRaimon Casanova, Junajo Lacort, Ángel Dieguez, Anna Arbat, Manel Puig, Josep Samitier, Marc Nierlich, Oliver Steinmetz, Oliver Scholz. 141-144 [doi]
• A distributed neural signal sensor systemChris Clarke, John Taylor, Robert Rieger, Nick Donaldson. 145-148 [doi]
• Automatic detection of region of interest and center point of left ventricle using watershed segmentationJierong Cheng, Say Wei Foo, Shankar M. Krishnan. 149-151 [doi]
• Assessment of driver s driving performance and alertness using EEG-based fuzzy neural networksChin-Teng Lin, Yu-Chieh Chen, Ruei-Cheng Wu, Sheng-Fu Liang, Teng-Yi Huang. 152-155 [doi]
• Classification of driver s cognitive responses from EEG analysisSheng-Fu Liang, Chin-Teng Lin, Ruei-Cheng Wu, Teng-Yi Huang, Wen-Hung Chao. 156-159 [doi]
• Partitioning graphs of supply and demandTakehiro Ito, Xiao Zhou, Takao Nishizeki. 160-163 [doi]
• Advances in QoS path(s) selection problemKrishnaiyan Thulasiraman, Ying Xiao, Guoliang Xue. 164-167 [doi]
• On generating elementary T-invariants of Petri nets by linear programmingTomiyuki Fukunaga, Qi-Wei Ge, Mitsuru Nakata. 168-171 [doi]
• Hierarchical extraction of a spanning planar subgraph maintaining clockwise directedness of cyclesDaisuke Takafuji, Toshimasa Watanabe. 172-175 [doi]
• Scheduling problems for a class of parallel distributed systemsHiroshi Tamura, Futoshi Tasaki, Masakazu Sengoku, Shoji Shinoda. 176-179 [doi]
• On the three-dimensional channel routingSatoshi Tayu, Patrik Hurtig, Yoshiyasu Horikawa, Shuichi Ueno. 180-183 [doi]
• An energy-efficient charge recycling approach for a SAR converter with capacitive DACBrian P. Ginsburg, Anantha P. Chandrakasan. 184-187 [doi]
• Novel successive-approximation algorithmsHarri Lampinen, Pauli Perälä, Olli Vainio. 188-191 [doi]
• A 1V supply successive approximation ADC with rail-to-rail input voltage rangeTakeshi Yoshida, Miho Akagi, Mamoru Sasaki, Atsushi Iwata. 192-195 [doi]
• . A new switch compensation technique for inverted R-2R ladder DACsD. Marche, Yves Gagnon, Yvon Savaria. 196-199 [doi]
• A new offset cancellation technique for folding ADCHamid Movahedian, Mehrdad Sharif Bakhtiar. 200-203 [doi]
• Characterization and noise analysis of a 12-bit current steering digital-to-analog converterTomás Lahoz, Enrique Barajas, José Luis González. 204-207 [doi]
• High linear digitally programmable gain amplifierBelén Calvo, Maria Teresa Sanz, Santiago Celma. 208-211 [doi]
• Impact of bias schemes on Doherty power amplifiersChih-Yun Liu, Yi-Jan Emery Chen, Deuk Hyoun Heo. 212-215 [doi]
• High current CMOS operational amplifierMikko Loikkanen, Juha Kostamovaara. 216-219 [doi]
• Design of a 0.8 Volt fully differential CMOS OTA using the bulk-driven techniqueYasutaka Haga, Hashem Zare-Hoseini, Laurence Berkovi, Izzet Kale. 220-223 [doi]
• Design and analysis of a micropower low-voltage bang-bang control class D amplifierTong Ge, Meng Tong Tan, Joseph Sylvester Chang. 224-227 [doi]
• Op amp tuning for high accuracy deep sub-micron CMOS analog circuits [voltage regulator example]Christian Falconi, Giuliano Guarino, Arnaldo D Amico. 228-231 [doi]
• Formal synthesis of circuits using linear matrix inequalitiesJeffrey Harrison. 232-235 [doi]
• Multiple resonance networks with incomplete energy transfer and operating with zero-state responseAntônio Carlos M. de Queiroz. 236-239 [doi]
• The separability, reducibility and controllability of RLCM networks over F(z)Kai-Sheng Lu, Xiao-Yu Feng, Guo-Zhang Gao. 240-243 [doi]
• Symbolic passive-RC circuit synthesis by admittance matrix expansionDavid G. Haigh, Paul M. Radmore. 244-247 [doi]
• Symbolic active-RC circuit synthesis by admittance matrix expansionDavid G. Haigh. 248-251 [doi]
• Generation of equivalent circuits by FTFN relocationRogelio Palomera-Garcia. 252-255 [doi]
• An active noise control system based on simultaneous equations method without auxiliary filtersMitsuji Muneyasu, Osamu Hisayasu, Kensaku Fujii, Takao Hinamoto. 256-259 [doi]
• A filtered-X RLS based narrowband active noise control system in the presence of frequency mismatchYegui Xiao, Liying Ma, Khashayar Khorasani, Akira Ikuta, Li Xu. 260-263 [doi]
• A method for online secondary path modeling in active noise control systemsMuhammad Tahir Akhtar, Masahide Abe, Masayuki Kawamata. 264-267 [doi]
• Active noise cancellation headsetSay Wei Foo, T. N. Senthilkumar, C. Averty. 268-271 [doi]
• A new noise reduction system based on ALE and noise reconstruction filterNaoto Sasaoka, Keisuke Sumi, Yoshio Itoh, Kensaku Fujii. 272-275 [doi]
• Adaptive noise equalizer with equal-loudness compensationWoon S. Gan, Sen M. Kuo, Jin Wei Feng. 276-279 [doi]
• Chaotic and periodic spreading dynamics in discrete small-world networksXiang Li, Hildegard Meyer-Ortmanns, Xiaofan Wang. 280-283 [doi]
• Pinning control of scale-free complex networksZhengping Fan, Guanrong Chen. 284-287 [doi]
• On-off intermittency in small-world networks of chaotic mapsChunguang Li, Jin-Qing Fang. 288-291 [doi]
• Agreement and consensus problems in groups of autonomous agents with linear dynamicsChai Wah Wu. 292-295 [doi]
• 3D dynamical networks to emulate complex neural phenomenaMaide Bucolo, Francesca Conti, Luigi Fortuna, Mattia Frasca. 296-299 [doi]
• Synchronization: a fundamental phenomenon in complex dynamical networksJinhu Lu, Henry Leung. 300-303 [doi]
• Linear transform based motion compensated prediction for luminance intensity changesDebing Liu, Yuwen He, Shipeng Li, Qingming Huang, Wen Gao. 304-307 [doi]
• A feature-based approach to fast H.264 intra/inter mode decisionChangsung Kim, C. C. Jay Kuo. 308-311 [doi]
• An improved rate control algorithm for H.264Hongtao Yu, Zhiping Lin, Feng Pan. 312-315 [doi]
• The technique of pre-scaled integer transformCixun Zhang, Jian Lou, Lu Yu, Jie Dong, Wai-kuen Cham. 316-319 [doi]
• An improved error concealment algorithm for intra-frames in H.264/AVCPanos Nasiopoulos, Lino Coria-Mendoza, Hassan Mansour, Adarsh Golikeri. 320-323 [doi]
• Quantization offsets for video codingThomas Wedi, Stefan Wittmann. 324-327 [doi]
• Iterative tri-stage decoding for turbo codes in partial response channelsMeng-Guang Tsai, Kuen-Suey Hou, Hen-Wai Tsao. 328-331 [doi]
• . Analog slice turbo decodingMatthieu Arzel, Cyril Lahuec, Fabrice Seguin, David Gnaedig, Michel Jézéquel. 332-335 [doi]
• A memory-based architecture for FPGA implementations of low-density parity-check convolutional decodersStephen Bates, Gary Block. 336-339 [doi]
• Low complexity parallel Chien search architecture for RS decoderQingsheng Hu, Zhigong Wang, Jun Zhang, Jie Xiao. 340-343 [doi]
• Area and power efficient trellis computational blocks in 0.13µm CMOSMatthias Kamuf, John B. Anderson, Viktor Öwall. 344-347 [doi]
• S-code: new distance-3 MDS array codesRajendra S. Katti, Xiaoyu Ruan. 348-351 [doi]
• Design of low complexity high-speed pulse-shaping IIR filters for mobile communication receiversA. Prasad Vinod, Edmund Ming-Kit Lai. 352-355 [doi]
• Wideband 70dB CMOS digital variable gain amplifier design for DVB-T receiver s AGCChua-Chin Wang, Ching-Li Lee, Li-Ping Lin, Yih-Long Tseng. 356-359 [doi]
• Multi-user receiver using conjugate gradient method for wideband CDMAYumi Takizawa, Cindy Bernadeth Tjitrosoewarno, Atsushi Fukasawa. 360-363 [doi]
• An ultra wideband low complexity circuit transceiver architecture for sensor networksLucian-Vasile Stoica, Sakari Tiuraniemi, Heikki Repo, Ian Oppermann. 364-367 [doi]
• A 15 mW 69 dB 2 Gsamples/s CMOS analog front-end for low-band UWB applicationsHua-Chin Lee, Chien-Chih Lin, Chia-Hsin Wu, Shen-Iuan Liu, Chorng-Kuang Wang, Hen-Wai Tsao. 368-371 [doi]
• Design of a fully integrated array of high-voltage digital-to-analog convertersEhab Shoukry, Madeleine Mony, David V. Plant. 372-375 [doi]
• A novel methodology for the design of LC tank VCO with low phase noiseLin Jia, Jianguo Ma, Kiat Seng Yeo, Manh Anh Do. 376-379 [doi]
• A novel low-power input-independent MOS AC/DC charge pumpYuan Yao, Yin Shi, Foster F. Dai. 380-383 [doi]
• Large tuning band range of high frequency filter for wireless applicationsZhiqiang Gao, Jianguo Ma, Yizheng Ye, Mingyan Yu. 384-387 [doi]
• Behavioral analysis and dimensioning of UMTS transmitters baseband blocksNicola Ghittori, Andrea Vigna, Piero Malcovati, Stefano D Amico, Andrea Baschirotto. 388-391 [doi]
• A frequency up-conversion and two-step channel selection embedded CMOS D/A interfaceKa-Hou Ao Ieong, Chong-Yin Fok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins. 392-395 [doi]
• A novel DC-offset cancelling circuit for DCRJiangnan Yan, Yuanjin Zheng, Yong Ping Xu. 396-399 [doi]
• A digitally programmable on-chip RC-oscillator in 0.25µm CMOS logic processChiara Ghidini, J. G. Aranda, Danilo Gerna, K. Kelliher, Christoph Baumhof. 400-403 [doi]
• A novel microstrip bandpass filter design using asymmetric parallel coupled-lineSi-Weng Fok, Phillip Ngai Cheong, Kam-Weng Tam, Rui Paulo Martins. 404-407 [doi]
• Pipelining Tomlinson-Harashima precodersYongru Gu, Keshab K. Parhi. 408-411 [doi]
• Low cost efficient architecture for H.264 motion estimationSebastián López, Félix Tobajas, A. Villar, V. de Armas, José Francisco López, Roberto Sarmiento. 412-415 [doi]
• Novel electrostatic discharge protection structure for a monolithic gas sensor systems-on-a-chipJavier A. Salcedo, Juin J. Liou, Muhammad Yaqub Afridi, Allen R. Hefner. 416-419 [doi]
• On-board fault-tolerant SAR processor for spaceborne imaging radar systemsWai-Chi Fang, C. Le, S. Taft. 420-423 [doi]
• Binary Taylor diagrams: an efficient implementation of Taylor expansion diagramsArash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh, Pejman Lotfi-Kamran, Mostafa Naderi, Zainalabedin Navabi. 424-427 [doi]
• Design space exploration on heterogeneous network-on-chipRodrigo Ferrugem Cardoso, Márcio Eduardo Kreutz, Luigi Carro, Altamiro Amadeu Susin. 428-431 [doi]
• A simple and cost effective video encoder with memory-reducing CAVLCYeong-Kang Lai, Chih-Chung Chou, Yu-Chieh Chung. 432-435 [doi]
• An integrated current flattening module for embedded cryptosystemsXuequn Li, Haleh Vahedi, Radu Muresan, Stefano Gregori. 436-439 [doi]
• A pseudo-differential CMOS receiver insensitive to input common mode levelNam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun. 440-443 [doi]
• Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuitsChung-Hsien Hua, Wei Hwang, Chih-Kai Chen. 444-447 [doi]
• High-speed CMOS-to-ECL pad driver in 0.18µm CMOSFrancesco Centurelli, G. Lulli, Piero Marietti, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti. 448-451 [doi]
• A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverterToshiro Akino, Kei Matsuura, Akiyoshi Yasunaga. 452-455 [doi]
• Case study of interconnect analysis for standing wave oscillator designMeigen Shen, Li-Rong Zheng, Esa Tjukanoff, Jouni Isoaho, Hannu Tenhunen. 456-459 [doi]
• Asynchronous pulse logic cell for threshold logic and Boolean networksJohan Lambie, Francesc Moll Echeto, José Luis González, Antonio Rubio. 460-463 [doi]
• Cascode buffer for monolithic voltage conversion operating at high input supply voltagesVolkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva Narendra. 464-467 [doi]
• Characteristics and programming of floating-gate pFET switches in an FPAA crossbar networkDavid N. Abramson, Jordan D. Gray, Christopher M. Twigg, Paul E. Hasler. 468-471 [doi]
• A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standardGrigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis, Athanasios Milidonis. 472-475 [doi]
• Quaternary arithmetic helix transforms based on Kronecker productBogdan J. Falkowski, Cheng Fu. 476-479 [doi]
• Generalized fastest linearly independent arithmetic transformsBogdan J. Falkowski, Cicilia C. Lozano, Susanto Rahardja. 480-483 [doi]
• Fixed sign Walsh transform and its iterative hardware architectureBogdan J. Falkowski, Shixing Yan. 484-487 [doi]
• Generation of linearly independent transforms over GF(4)Bogdan J. Falkowski, Cheng Fu. 488-491 [doi]
• A high performance architecture of EBCOT encoder in JPEG 2000Xiaolang Yan, Ying Qin, Ye Yang, Haitong Ge. 492-495 [doi]
• Comparison of the horizontal and the vertical common subexpression elimination methods for realizing digital filtersA. Prasad Vinod, Edmund Ming-Kit Lai. 496-499 [doi]
• Complex-coefficient variable filter design using successive vector-array-decompositionTian-Bo Deng. 500-503 [doi]
• Non-iterative WLS design of allpass variable fractional-delay digital filtersTian-Bo Deng. 504-507 [doi]
• Discrete optimization for error feedback network using lower bound estimationMasayoshi Nakamoto, Yuji Maejima, Takao Hinamoto. 508-511 [doi]
• Design of a square-root-raised-cosine FIR filter by a recursive methodChia-Yu Yao, Chiang-Ju Chien. 512-515 [doi]
• Pole deviation analysis for digital systems based on second order perturbation theory [digital filter example]Jinxin Hao, Gang Li, Jun Wu. 516-519 [doi]
• A hybrid GA for the design of multiplication-free frequency response masking filters [FIR digital filters]Ling Cen, Yong Lian. 520-523 [doi]
• Pulse shaping with bireciprocal wave digital lattice filtersDirk S. Waldhauser, Christoph Saas, Josef A. Nossek. 524-527 [doi]
• Design and FPGA implementation of a structure of evolutionary digital filters for hardware implementationMasahide Abe, Hiroki Arai, Masayuki Kawamata. 528-531 [doi]
• A novel 2D filter design methodologyChristos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung. 532-535 [doi]
• Synthesis of reconfigurable multiplier blocks: part I - fundamentalsSüleyman Sirri Demirsoy, Izzet Kale, Andrew G. Dempster. 536-539 [doi]
• Synthesis of reconfigurable multiplier blocks: part - II algorithmSüleyman Sirri Demirsoy, Izzet Kale, Andrew G. Dempster. 540-543 [doi]
• A hardware-efficient FIR architecture with input-data and tap foldingLi-Hsun Chen, Oscal T.-C. Chen. 544-547 [doi]
• Residue number system implementations of complex heterodyne tunable filtersGrace Y. Cho, Louis G. Johnson, Michael A. Soderstrand. 548-551 [doi]
• Low complexity decimation filter for multi-standard digital receiversAshok Kumar, J. Luis Tecpanecatl-Xihuitl, Magdy A. Bayoumi. 552-555 [doi]
• Stability of a shift-variant 2-D state-space digital filterGlen W. Mabey, Tamal Bose, Mei Chen. 556-559 [doi]
• A time-to-digital-converter-based CMOS smart temperature sensorChun-Chi Chen, Wen-Fu Lu, Chin-Chung Tsai, Poki Chen. 560-563 [doi]
• High-speed sensing system for depth estimation based on depth-from-focus by using smart imagerTakashi Yoshida, Arimitsu Yokota, Hideki Kashiyama, Takayuki Hamamoto. 564-567 [doi]
• A CMOS imager for light blobs detection and processingJ. L. D. Gonzalez, D. Sadowski, Karan V. I. S. Kaler, Martin P. Mintchev, Orly Yadid-Pecht. 568-571 [doi]
• Design of electro-optical demodulating pixel in CMOS technologyFabrizio De Nisi, David Stoppa, Mauro Scandiuzzo, Lorenzo Gonzo, Lucio Pancheri, Gian-Franco Dalla Betta. 572-575 [doi]
• Digital measurement of human proximity to electrical power circuit by a novel amplitude-shift-keying radio-frequency receiverShengke Zeng, John R. Powers, Larry L. Jackson, David L. Conover. 576-579 [doi]
• Low-power global/rolling shutter image sensors in silicon on sapphire technologyAlexander Fish, Evgeny Avner, Orly Yadid-Pecht. 580-583 [doi]
• Low power current mode ADC for CMOS sensor ICYoungbok Kim, Anuj Agarwal, Sameer R. Sonkusale. 584-587 [doi]
• A wide dynamic range CMOS active pixel sensor with frame differenceVadim Alexander Milirud, Leonid Fleshel, Wenjing Zhang, Graham A. Jullien, Orly Yadid-Pecht. 588-591 [doi]
• Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip busesYehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Vivek De. 592-595 [doi]
• Low power repeaters driving RLC interconnects with delay and bandwidth constraintsGuoqing Chen, Eby G. Friedman. 596-599 [doi]
• Low-leakage repeaters for NoC interconnectsArkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny. 600-603 [doi]
• Power-aware global signaling strategiesRahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif. 604-607 [doi]
• Designing optimized pipelined global interconnects: algorithms and methodology impactVidyasagar Nookala, Sachin S. Sapatnekar. 608-611 [doi]
• Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environmentRadu M. Secareanu, S. K. Banerjee, Olin L. Hartin, Francisco V. Fernández, Eby G. Friedman. 612-615 [doi]
• Battery-aware dynamic voltage scaling in multiprocessor embedded systemYuan Cai, Sudhakar M. Reddy, Irith Pomeranz, Bashir M. Al-Hashimi. 616-619 [doi]
• Noise coupling in multi-voltage power distribution systems with decoupling capacitorsMikhail Popovich, Eby G. Friedman. 620-623 [doi]
• A 16-bit low-power microcontroller with monolithic MEMS-LC clockingRobert M. Senger, Eric D. Marsman, Michael S. McCorquodale. 624-627 [doi]
• A fast chip-scale power estimation method for large and complex LSIs based on hierarchical analysisYuichi Nakamura, Takeshi Yoshimura. 628-631 [doi]
• An LSI system with locked in temperature insensitive state achieved by using body bias techniqueGoichi Ono, Masayuki Miyazaki, Kazuki Watanabe, Takayuki Kawahara. 632-635 [doi]
• An energy-efficient circuit technique for single event transient noise-toleranceMing Zhang, Naresh R. Shanbhag. 636-639 [doi]
• Decentralized energy-conserving and coverage-preserving protocols for wireless sensor networksChi-Fu Huang, Li-Chu Lo, Yu-Chee Tseng, Wen-Tsuen Chen. 640-643 [doi]
• Event-based imaging with active illumination in sensor networksEugenio Culurciello, Thiago Teixeira, Andreas G. Andreou. 644-647 [doi]
• On the construction of efficient data gathering tree in wireless sensor networksNiwat Thepvilojanapong, Yoshito Tobe, Kaoru Sezaki. 648-651 [doi]
• A RF map-based localization algorithm for indoor environmentsCesare Alippi, Alan Mottarella, Giovanni Vanini. 652-655 [doi]
• A new formulation of fast diminished-one multioperand modulo 2/sup n/+1 adderBin Cao, Chip-Hong Chang, Thambipillai Srikanthan. 656-659 [doi]
• Non-interleaving architecture for hardware implementation of modular multiplicationQiang Liu, Dong Tong, Xu Cheng. 660-663 [doi]
• A new design method to modulo 2/sup n/-1 squaringBin Cao, Thambipillai Srikanthan, Chip-Hong Chang. 664-667 [doi]
• Constant addition utilizing flagged prefix structuresJames E. Stine, Christopher R. Babb, Vibhuti B. Dave. 668-671 [doi]
• Efficient VLSI implementation of N/N integer divisionKei-Yong Khoo, Alan N. Willson Jr.. 672-675 [doi]
• A novel design of leading zero anticipation circuit with parallel error detectionGe Zhang, Zichu Qi, Weiwu Hu. 676-679 [doi]
• High-level synthesis under I/O timing and memory constraintsPhilippe Coussy, Gwenolé Corre, Eric Senn, Pierre Bomel, Eric Martin. 680-683 [doi]
• A low power scheduling method using dual V/sub dd/ and dual V/sub th/Kun-Lin Tsai, Szu-Wei Chaung, Feipei Lai, Shanq-Jang Ruan. 684-687 [doi]
• A synthesis scheme for simultaneous scheduling, binding, partitioning and placement with resources operating at multiple voltagesLing Wang, Yingtao Jiang, Yu Zhang, Ru Chen. 688-691 [doi]
• A heuristic approach for multiple restricted multiplicationNalin Sidahao, George A. Constantinides, Peter Y. K. Cheung. 692-695 [doi]
• Lower-bound estimation for multi-bitwidth schedulingJunjuan Xu, Jason Cong, Xu Cheng. 696-699 [doi]
• Statistical schedule length analysis in asynchronous datapath synthesisKoji Ohashi, Mineo Kaneko. 700-703 [doi]
• Comparison of two class E amplifiers for EER transmitterAntti Heiskanen, Timo Rahkonen. 704-707 [doi]
• Steady-state behavior of class E amplifier outside designed conditionsTadashi Suetsugu, Marian K. Kazimierczuk. 708-711 [doi]
• Voltage-clamped class E amplifier with transmission-line transformerTadashi Suetsugu, Marian K. Kazimierczuk. 712-715 [doi]
• Optimum design of very low distortion class E power amplifiersSiu Chung Wong, Chi K. Michael Tse. 716-719 [doi]
• Resonant DC/DC converter with class E oscillatorHiroyuki Hase, Hiroo Sekiya, Jianming Lu, Takashi Yahagi. 720-723 [doi]
• Planar inductors with interleaved conductors for integrated power applicationsAlain Salles, Bruno Estibals, David Bourrier, Corinne Alonso. 724-727 [doi]
• A novel correlated double sampling poly-Si circuit for readout systems in large area X-ray sensorsAleksandra Rankov, Esther Rodríguez-Villegas, Michael J. Lee. 728-731 [doi]
• On-chip active power rectifiers for biomedical applicationsTorsten Lehmann, Yashodhan Moghe. 732-735 [doi]
• A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applicationsHwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, Wu-Shiung Feng. 736-739 [doi]
• A 0.9-V 67-µW analog front-end using adaptive-SNR technique for digital hearing aidSunyoung Kim, Jae-Youl Lee, Seong-Jun Song, Namjun Cho, Hoi-Jun Yoo. 740-743 [doi]
• A BiCMOS ENG amplifier with high SIR outputIasonas F. Triantis, Andreas Demosthenous. 744-747 [doi]
• 10-channel very low noise ENG amplifier system using CMOS technologyRobert Rieger, Dipankar Pal, John Taylor, Chris Clarke, Peter Langlois, Nick Donaldson. 748-751 [doi]
• Minimum augmentation to bi-connect specified vertices of a graph with upper bounds on vertex-degreeToshiya Mashima, Takanori Fukuoka, Satoshi Taoka, Toshimasa Watanabe. 752-755 [doi]
• A modeling method of a rule based control system with hierarchical Petri netMamoru Sakamoto, Toshiyuki Miyamoto, Sadatoshi Kumagai. 756-759 [doi]
• Minimal time reachability problem of some subclasses of timed Petri netsAtsushi Ohta, Kohkichi Tsuji, Tomiji Hisamura. 760-763 [doi]
• The node voltage equations and structural conditions of observability for RLC networks over F(z)Kai-Sheng Lu, Guo-Zhang Gao. 764-767 [doi]
• Graph-theoretic approach to the design of four-switch DC-DC convertersTetsuo Nishi, Masato Ogata. 768-771 [doi]
• Simplified algorithm to determine break point realys and relay coordination based on network topology [for realys read relays]Sastry Mks. 772-775 [doi]
• A low-distortion 1.2 V DAC+filter for transmitters in wireless applicationsNicola Ghittori, Andrea Vigna, Piero Malcovati, Stefano D Amico, Andrea Baschirotto. 776-779 [doi]
• Adjustable gamma correction circuit for TFT LCDPo-Ming Lee, Hung-Yi Chen. 780-783 [doi]
• A segmented thermometer coded DAC with deterministic dynamic element matching for high resolution ADC testBeatriz Olleta, Hanjun Jiang, Degang Chen, Randall L. Geiger. 784-787 [doi]
• A start-up calibration method for generic current-steering D/A converters with optimal area solutionGeorgi I. Radulov, Patrick J. Quinn, J. A. Hegt, Arthur H. M. van Roermund. 788-791 [doi]
• Pipeline ADC linearity testing with dramatically reduced data capture timeZhongjun Yu, Degang Chen, Randall L. Geiger, Ioannis Papantonopoulos. 792-795 [doi]
• On-chip built-in self-test of video-rate ADCs using Gaussian noiseJoão Goes, Nuno F. Paulino, Guiomar Evans. 796-799 [doi]
• A 0.18µm CMOS low-noise elliptic low-pass continuous-time filterJuan Francisco Fernández-Bootello, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez. 800-803 [doi]
• Low sensitivity single-ended-input OTA and grounded capacitor elliptic filter structure with the minimum componentsShu-Hui Tu, J. Neil Ross. 804-807 [doi]
• Low-sensitivity active-RC filters using impedance tapering of symmetrical bridged-T and twin-T networksDrazen Jurisic, Neven Mijat, George S. Moschytz. 808-811 [doi]
• A widely tunable Gm-C filter using tail current offset in two differential pairsTomoyuki Tanaka, Sungwoo Cha, Shinsaku Shimizu, Tsukasa Ida, Hiroaki Ishihara, Toshimasa Matsuoka, Kenji Taniguchi, Akashi Sugimori, Hiroki Hihara. 812-815 [doi]
• A comparison approach of lowpass type wave active filter using unified circuit blockS. Hirano, A. Sato, T. Kitamura. 816-819 [doi]
• Single amplifier bi-quadratic filter topologies in transimpedance configurationG. Chandra, Preetam Tadeparthy, P. Easwaran. 820-823 [doi]
• Quantum circuit design of discrete Hartley transform using recursive decomposition formulaChien-Cheng Tseng, Tsung-Ming Hwang. 824-827 [doi]
• Quantum circuit design of 8×8 discrete cosine transform using its fast computation flow graphChien-Cheng Tseng, Tsung-Ming Hwang. 828-831 [doi]
• Hermite-Gaussian-like eigenvectors of the DFT matrix generated by the eigenanalysis of an almost tridiagonal matrixMagdy T. Hanna, Nabila P. Attalla Seif, M. Waleed Abd El Maguid Ahmed. 832-835 [doi]
• An approach for computing the radix-2/4 DIT FHT and FFT algorithms using a unified structureSaad Bouguezel, M. Omair Ahmad, M. N. S. Swamy. 836-839 [doi]
• Design of wavelet filters based on digital complex allpass filtersAlfonso Fernández-Vázquez, Gordana Jovanovic-Dolecek. 840-843 [doi]
• Block time-recursive discrete Gabor transform implemented by unified parallel lattice structuresLiang Tao, Hon Keung Kwan. 844-847 [doi]
• Rate determination based on perceptual loudnessAndreas Spanias, Venkatraman Atti. 848-851 [doi]
• A mixed analog-digital hybrid for speech enhancement purposesBenny Sallberg, Mattias Dahl, Henrik Akesson, Ingvar Claesson. 852-855 [doi]
• Adaptive beamformer for hands-free communication system in noisy environmentsHai Quang Dam, Sven Nordholm, Hai Huyen Dam, Siow Yong Low. 856-859 [doi]
• Audio classification and scene recognition and for hearing aidsSourabh Ravindran, David V. Anderson. 860-863 [doi]
• A versatile speech enhancement system based on perceptual wavelet denoisingYu Shao, Chip-Hong Chang. 864-867 [doi]
• Improved voice activity detection via contextual information and noise suppressionAbhijeet Sangwan, Wei-Ping Zhu, M. Omair Ahmad. 868-871 [doi]
• Approximations for bit error probabilities in SSMA communication systems using spreading sequences of Markov chainsHiroshi Fujisaki, Gerhard Keller. 872-875 [doi]
• Optimal spreading in multi-user non-coherent binary chaos-shift-keying communication systemsJi Yao, Anthony J. Lawrance. 876-879 [doi]
• Cryptanalysis of a multistage encryption systemChengqing Li, Xinxiao Li, Shujun Li, Guanrong Chen. 880-883 [doi]
• Design of code-matched receiver for DS/CDMA communicationsYutaka Jitsumatsu, Tohru Kohda. 884-887 [doi]
• Coded modulation based on higher dimensional chaotic mapsSlobodan Kozic, Thomas Schimming. 888-891 [doi]
• Long period pseudo random bit generators derived from a discretized chaotic mapTommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli. 892-895 [doi]
• Frame size selection in video downsizing transcoding applicationHaiyan Shu, Lap-Pui Chau. 896-899 [doi]
• A novel algorithm for reducing computational complexity of MC-DCT in frequency-domain video transcodersDeepak P. Nayak, Dipan B. Mehta, Uday B. Desai. 900-903 [doi]
• Efficient video transcoding between H.263 and H.264/AVC standardsViet Anh Nguyen, Yap-Peng Tan. 904-907 [doi]
• Low complexity H.263 to H.264 video transcoding using motion vector decompositionKai-Tat Fung, Wan-Chi Siu. 908-911 [doi]
• Consideration of transcoding using updatable scalability for selective quality video content delivery methodMei Kodama, Shunya Suzuki. 912-915 [doi]
• Flexible resizing algorithms for video transcodingCarlos Salazar-Lazaro, Trac D. Tran. 916-919 [doi]
• A low-power, 20-Gb/s continuous-time adaptive passive equalizerRuifeng Sun, Jaejin Park, Frank O Mahony, C. Patrick Yue. 920-923 [doi]
• Adaptive decision-feedback equalization for band-limited high-speed serial linksNorbert Neurohr, Matthias Schoebinger, Edoardo Prete, Anthony Sanders. 924-927 [doi]
• Joint carrier recovery and adaptive equalization for high-order QAMJunhua Tian, Bo Shen, Zheng Li, Jianing Su, Qianling Zhang. 928-931 [doi]
• Hardware realization of fuzzy adaptive filters for non linear channel equalizationMiguel A. Melgarejo, Fredy Olarte, Pedro Ladino. 932-935 [doi]
• Jitter equalization for binary baseband communicationAnthony Chan Carusone. 936-939 [doi]
• Predictive equalizer design for DVB-T systemTing-An Lin, Chen-Yi Lee. 940-943 [doi]
• Progressive coding of 3D dynamic mesh sequences using spatiotemporal decompositionJeong-Hyu Yang, Chang-Su Kim, Sang Uk Lee. 944-947 [doi]
• Progressive lossless 3D mesh encoder with octree-based space partitioningJingliang Peng, Sheng Yang, C. C. Jay Kuo. 948-951 [doi]
• Fast region-of-interest transcoding for JPEG 2000 imagesHao-Song Kong, Anthony Vetro, Toshihiko Hata, Naoki Kuwahara. 952-955 [doi]
• Construction of regular 3D point clouds using octree partitioning and resamplingJae-Young Sim, Sang Uk Lee, Chang-Su Kim. 956-959 [doi]
• Slice group based multiple description video coding with three motion compensation loopsDong Wang, Cedric Nishan Canagarajah, David R. Bull. 960-963 [doi]
• Improving classification of video shots using information-theoretic co-clusteringPeng Wang, Rui Cai, Shi-Qiang Yang. 964-967 [doi]
• The upper bound of the second-order modes of linear state-space systems [digital filter example]Shunsuke Koshita, Masahide Abe, Masayuki Kawamata. 968-971 [doi]
• A novel property of the second-order modes of discrete-time systems under variable transformationShunsuke Koshita, Masahide Abe, Masayuki Kawamata. 972-975 [doi]
• Special singularity integrals encountered in electric circuits [RLC circuit examples]Aziz S. Inan, Peter M. Osterberg. 976-979 [doi]
• Identification of electric circuits: problems and methods of solution accuracy enhancementAlexei S. Adalev, Nikolai V. Korovkin, Masashi Hayakawa. 980-983 [doi]
• On the effect of time delays in negative feedback amplifiersLuis Nero Alves, Rui L. Aguiar. 984-987 [doi]
• Jittered uniform sampling - examplesSvante Signell. 988-991 [doi]
• Testability evaluation for analog linear circuits via transfer function analysisBarbara Cannas, Alessandra Fanni, Augusto Montisci. 992-995 [doi]
• Synthesis of MITE log-domain filters with unique operating pointsShyam Subramanian, David V. Anderson, Paul E. Hasler, Bradley A. Minch. 996-999 [doi]
• Low voltage high current gain CMOS digitally controlled fully differential CCII [variable gain amplifier application example]Soliman A. Mahmoud. 1000-1003 [doi]
• A new NMOS four-quadrant analog multiplierBoonchai Boonchu, Wanlop Surakampontorn. 1004-1007 [doi]
• Class-AB rail-to-rail CMOS analog bufferJuan M. Carrillo, J. Francisco Duque-Carrillo, Antonio B. Torralba, Ramón González Carvajal. 1008-1011 [doi]
• IC design of an analog tunable crossover networkEduardo Rapoport, Fernando Antonio Pinto Baruqui, Antonio Petraglia. 1012-1015 [doi]
• A ± 1.5 V high frequency four quadrant current multiplierVarakorn Kasemsuwan, Teerawat Arthansiri, Hyung Keun Ahn. 1016-1019 [doi]
• CMOS analog current-mode multiplier based on the advanced compact MOSFET modelFábio A. Pereira, Mário C. G. de Oliveira, Ana Isabela Araújo Cunha. 1020-1023 [doi]
• On-chip temperature sensor with high tolerance for process and temperature variationT. Yasuda. 1024-1027 [doi]
• A current mode Palmo cell for programmable analogue signal processingYaxiong Zhang, Alister Hamilton. 1028-1031 [doi]
• A memory-reduced log-MAP kernel for turbo decoderTsung-Han Tsai, Cheng-Hung Lin, An-Yeu Wu. 1032-1035 [doi]
• An ultra high-speed Reed-Solomon decoderHanho Lee. 1036-1039 [doi]
• A new low-power turbo decoder using HDA-DHDD stopping iterationWen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, Yuh-Shyan Hwang. 1040-1043 [doi]
• Communication subsystem synthesis and analysis tool using bus architecture generation and stochastic arbitration policiesSankalp Kallakuri, Nattawut Thepayasuwan, Alex Doboli, Simona Doboli. 1044-1047 [doi]
• Efficient implementation of trace-back unit in a reconfigurable Viterbi decoder fabricCheng Zhan, Tughrul Arslan, Sami Khawam, Iain Lindsay. 1048-1050 [doi]
• A new reconfigurable modem architecture for 3G multi-standard wireless communication systemsJung Ho Kim, Dong Sam Ha, Jeffrey H. Reed. 1051-1054 [doi]
• A 12.5 Gbps CMOS input sampler for serial link receiver front endShyh-Jye Jou, Chih-Hsien Lin, Yen-I Wang. 1055-1058 [doi]
• Low-power current mode logic for improved DPA-resistance in embedded systemsZeynep Toprak Deniz, Yusuf Leblebici. 1059-1062 [doi]
• A new level-up shifter for high speed and wide range interface in ultra deep sub-micronKyoung-Hoi Koo, Jin-Ho Seo, Myeong-Lyong Ko, Jae-Whui Kim. 1063-1065 [doi]
• A novel CMOS logic style with data independent power consumptionManfred Josef Aigner, Stefan Mangard, Renato Menicocci, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti. 1066-1069 [doi]
• A phase-detect synchronous mirror delay for clock skew-compensation circuitsKuo-Hsing Cheng, Chen-Lung Wu, Yu-lung Lo, Chia-Wei Su. 1070-1073 [doi]
• A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applicationsI-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu. 1074-1077 [doi]
• A linear model for high-level delay estimation in VDSM on-chip interconnectsAlberto García Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner. 1078-1081 [doi]
• A closed-form delay formula for on-chip RLC interconnects in current-mode signalingMingcui Zhou, Wentai Liu, Mohanasankar Sivaprakasam. 1082-1085 [doi]
• Two dimensional nonuniform perfect reconstruction filter bank with irrational down-sampling matricesSoo-Chang Pei, Meng-Ping Kao. 1086-1089 [doi]
• Multidimensional filter banks design by direct optimizationTruong T. Nguyen, Soontorn Oraintara. 1090-1093 [doi]
• On the theory and design of a class of PR causal-stable IIR non-uniform recombination cosine modulated filter banksS. C. Chan, S. S. Yin. 1094-1097 [doi]
• Design of two-channels FIR filterbanks with rational sampling factors using the FRM techniqueRobert Bregovic, Tapio Saramäki. 1098-1101 [doi]
• Programmable power-of-two RNS scaler and its application to a QRNS polyphase filterGian-Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re. 1102-1105 [doi]
• : Optimized transmultiplexers for multirate systemsPilar Martín-Martín, Fernando Cruz-Roldán, Tapio Saramäki. 1106-1109 [doi]
• A class of directional filter banks [image processing applications]Truong T. Nguyen, Soontorn Oraintara. 1110-1113 [doi]
• Filter bank design for an adaptive subband structure with critical sampling using a new adaptation schemeMariane R. Petraglia, Paulo B. Batalheiro. 1114-1117 [doi]
• Architectural design of fractal image coder based on kick-out conditionHau-Jie Liang, Shuenn-Shyang Wang. 1118-1121 [doi]
• Dictionary-based program compression on transport triggered architecturesJari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, Henk Corporaal. 1122-1125 [doi]
• Techniques for efficient DCT/IDCT implementation on generic GPUBo Fang, Guobin Shen, Shipeng Li, Huifang Chen. 1126-1129 [doi]
• High-performance systolic arrays for band matrix multiplicationYun Yang, Wenqing Zhao, Yasuaki Inoue. 1130-1133 [doi]
• Block-level parallel processing for scaling evenly divisible framesEero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo Hämäläinen. 1134-1137 [doi]
• Parallel FFT computation with a CDMA-based network-on-chipDaewook Kim, Manho Kim, Gerald E. Sobelman. 1138-1141 [doi]
• Hardware accelerator design for video segmentation with multi-modal background modellingHongtu Jiang, Håkan Ardö, Viktor Öwall. 1142-1145 [doi]
• Multiplier-free structures for exact generation of natural powers of integersSaed Samadi, M. Omair Ahmad, M. N. S. Swamy. 1146-1149 [doi]
• A 0.18-µm CMOS 1-Gb/s serial link transceiver by using PWM and PAM techniquesChing-Yuan Yang, Yu Lee. 1150-1153 [doi]
• 3.125 Gb/s power efficient line driver with 2-level pre-emphasis and 2 kV HBM ESD protectionKrzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Sebastian Magierowski, Rafal Dlugosz, A. Dabrowski. 1154-1157 [doi]
• A 0.18µm CMOS transceiver design for high-speed backplane data communicationsMiao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang. 1158-1161 [doi]
• A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICsJaejin Park, Ruifeng Sun, L. Rick Carley, C. Patrick Yue. 1162-1165 [doi]
• An electrically adjustable distributed pulse shaping filter for 40 Gbit/s optical linksMiguel Ângelo M. Madureira, Paulo M. P. Monteiro, Rui L. Aguiar, Manuel Violas. 1166-1169 [doi]
• Dual-loop control of laser drivers for 3.125GHz optical transceiversMona M. Hella, Richard Panock. 1170-1173 [doi]
• A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuitKuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang. 1174-1177 [doi]
• An high speed integrated equalizer for dispersion compensation in 10Gb/s fiber networksVasanth Kakani, Foster F. Dai, Richard C. Jaeger. 1178-1181 [doi]
• ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structureKun-Hsien Lin, Ming-Dou Ker. 1182-1185 [doi]
• A novel substrate-triggered ESD protection structure for a bus switch IC with on-chip substrate-pumpPaul C. F. Tong, Ping-Ping Xu, Wensong Chen, John Hui, Patty Z. Q. Liu. 1190-1193 [doi]
• ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologiesMarkus P. J. Mergens, Geert Wybo, Bart Keppens, Benjamin Van Camp, Frederic De Ranter, Koen G. Verhaege, John Armer, Phillip Jozwiak, Christian C. Russ. 1194-1197 [doi]
• A new pre-driver design for improving the ESD performance of the high voltage tolerant I/OJian-Hsing Lee, Jiaw-Ren Shih, Yi-Hsun Wu, Kuo-Feng Yu, Tong-Chern Ong. 1198-1201 [doi]
• On-chip ESD protection for RF I/Os: devices, circuits and modelsElyse Rosenbaum, Sami Hyvonen. 1202-1205 [doi]
• A methodology for partitioning DSP applications in hybrid reconfigurable systemsMichalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis. 1206-1209 [doi]
• A new approach based on LFF for optimization of dynamic hardware reconfigurationsZhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani. 1210-1213 [doi]
• A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technologyMinoru Watanabe, Fuminori Kobayashi. 1214-1217 [doi]
• Pipelining technique for energy-aware datapathsWei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen. 1218-1221 [doi]
• A low power FPGA routing architectureSomsubhra Mondal, Seda Ogrenci Memik. 1222-1225 [doi]
• Efficient high radix modular multiplication for high-speed computing in re-configurable hardware [cryptographic applications]Yi Wang, Jussipekka Leiwo, Thambipillai Srikanthan. 1226-1229 [doi]
• Motion information and coding mode reuse for MPEG-2 to H.264 transcodingZhi Zhou, Shijun Sun, Shawmin Lei, Ming-Ting Sun. 1230-1233 [doi]
• Efficient MPEG-2 to H.264/AVC intra transcoding in transform-domainYeping Su, Jun Xin, Anthony Vetro, Huifang Sun. 1234-1237 [doi]
• Efficient rate control for MPEG-2 to H.264/AVC transcodingYou-Neng Xiao, Hong Lu, Xiangyang Xue, Viet Anh Nguyen, Yap-Peng Tan. 1238-1241 [doi]
• R-D optimized quantization of H.264 SP-frames for bitstream switching under storage constraintsChen-Po Chang, Chia-Wen Lin. 1242-1245 [doi]
• Fast mode decision and motion estimation for H.264 with a focus on MPEG-2/H.264 transcodingXiaoan Lu, Alexis Michael Tourapis, Peng Yin, Jill M. Boyce. 1246-1249 [doi]
• Optimizing user expectations for video semantic filtering and abstractionChing-Yung Lin, Belle L. Tseng. 1250-1253 [doi]
• Analytical crosstalk noise and its induced-delay estimation for distributed RLC interconnects under ramp excitationLacina M. Coulibaly, H. J. Kadim. 1254-1257 [doi]
• An all-digital pulsewidth control loopYi-Ming Wang, Chang-Fen Hu, Yi-Jen Chen, Jinn-Shyan Wang. 1258-1261 [doi]
• Design of a new sense amplifier flip-flop with improved power-delay-productHui Zhang, Pinaki Mazumder. 1262-1265 [doi]
• A 1.2 V sense amplifier for high-performance embeddable NOR flash memoriesDavide Baderna, Alessandro Cabrini, Guido De Sandre, Francesco De Santis, Marco Pasotti, Andrea Rossini, Guido Torelli. 1266-1269 [doi]
• SET and RESET pulse characterization in BJT-selected phase-change memoriesFerdinando Bedeschi, Edoardo Bonizzoni, Giulio Casagrande, Roberto Gastaldi, Claudio Resta, Guido Torelli, Daniele Zella. 1270-1273 [doi]
• Decision feedback equalization for high-speed backplane data communicationsJing Chen, Miao Li, Tad A. Kwasniewski. 1274-1277 [doi]
• Interconnect model reductions by using the AORA algorithm with considering the adjoint networkChia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng, Ming-Hong Lai. 1278-1281 [doi]
• Parameter domain pruning for improving convergence of synthesis algorithmsHua Tang, Alex Doboli. 1282-1285 [doi]
• Enriching an analog platform for analog-to-digital converter designFernando De Bernardinis, Pierluigi Nuzzo, Pierangelo Terreni, Alberto L. Sangiovanni-Vincentelli. 1286-1289 [doi]
• Parametric model order reduction technique for design optimizationAlfred Tze-Mun Leung, Roni Khazaka. 1290-1293 [doi]
• Design automation of single-ended LNAs using symbolic analysisGülin Tulunay, Sina Balkir. 1294-1297 [doi]
• Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimizationTrent McConaghy, Georges G. E. Gielen. 1298-1301 [doi]
• Efficiency optimization in linear-assisted switching power converters for envelope tracking in RF power amplifiersVahid Yousefzadeh, Eduard Alarcón, Dragan Maksimovic. 1302-1305 [doi]
• Hybrid trigonometric differential evolution for optimizing harmonic distributionShiyan Hu, Han Huang, Dariusz Czarkowski. 1306-1309 [doi]
• Hybrid switched-capacitor-Cuk/Zeta/Sepic converters in step-up modeBoris Axelrod, Yefim Berkovich, Adrian Ioinovici. 1310-1313 [doi]
• High efficiency wide bandwidth power supplies for GSM and EDGE RF power amplifiersYuShan Li, Dragan Maksimovic. 1314-1317 [doi]
• Boost-buck inverter variable structure control for grid-connected photovoltaic systemsCarlos Meza, Domingo Biel, Luis Martinez-Salamero, Francisco Guinjoan. 1318-1321 [doi]
• Thinned-out controlled class D inverter with delta-sigma modulated 1-bit driving pulsesHirotaka Koizumi, Kosuke Kurokawa, Shinsaku Mori. 1322-1325 [doi]
• Modeling external feedback path of an ITE digital hearing instrument for acoustic feedback cancellationJingbo Yang, Meng Tong Tan, Joseph Sylvester Chang. 1326-1329 [doi]
• A dual-mode wavelet based R-wave detector using single-V::t:: for leakage reduction [cardiac pacemaker applications]Joachim Neves Rodrigues, Thomas Olsson, Leif Sörnmo, Viktor Öwall. 1330-1333 [doi]
• An efficient ECG data compression technique based on predefined signature and envelope vector banksHakan Gürkan, Ümit Güz, B. Siddik Yarman. 1334-1337 [doi]
• The CRLB for bilinear systems and its biomedical applicationsQiyue Zou, Zhiping Lin, Raimund J. Ober. 1338-1341 [doi]
• Scalable architecture for streaming neural information from implantable multichannel neuroprosthetic devicesKyle E. Thomson, Theo Shlien, Yasir Suhail, Karim G. Oweiss. 1342-1345 [doi]
• A novel CMOS lab-on-a-chip for biomedical applicationsYehya H. Ghallab, Wael M. Badawy. 1346-1349 [doi]
• Probabilistic congestion prediction in hierarchical quad-grid modelJin-Tai Yan, Yen-Hsiang Chen, Chia-Wei Wu. 1350-1353 [doi]
• Small congestion embedding of separable graphs into grids of the same sizeAkira Matsubayashi. 1354-1357 [doi]
• On VLSI decompositions for d-ary de Bruijn graphs (extended abstract)Toshinori Yamada, Hiroyuki Kawakita, Tadashi Nishiyama, Shuichi Ueno. 1358-1361 [doi]
• Approximation algorithms for the rectilinear Steiner tree problem with obstaclesMakoto Fujimoto, Daisuke Takafuji, Toshimasa Watanabe. 1362-1365 [doi]
• Wiring area optimization in floorplan-aware hierarchical power gridsJin-Tai Yan, Chia-Wei Wu, Yen-Hsiang Chen. 1366-1369 [doi]
• Timing-driven Steiner tree construction based on feasible assignment of hidden Steiner pointsJin-Tai Yan, Tzu-Ya Wang, Yu-Cheng Lee. 1370-1373 [doi]
• A robust background calibration technique for switched-capacitor pipelined ADCsJen-Lin Fan, Jieh-Tsorng Wu. 1374-1377 [doi]
• A digital self-calibration algorithm for ADCs based on histogram test using low-linearity input signalsLe Jin, Degang Chen, Randall L. Geiger. 1378-1381 [doi]
• A linear-approximation technique for digitally-calibrated pipelined A/D convertersDing-Lan Shen, Tai-Cheng Lee. 1382-1385 [doi]
• Design of a 2-GS/s 8-b self-calibrating ADC in 0.18µm CMOS technologyCristiano Azzolini, Andrea Boni, Alessio Facen, Matteo Parenti, Davide Vecchi. 1386-1389 [doi]
• Background calibration of interleaved analog to digital converters for high-speed communications using interleaved timing recovery techniquesOscar E. Agazzi, Venu Gopinathan. 1390-1393 [doi]
• Spectral shaping of timing mismatches in time-interleaved analog-to-digital convertersChristian Vogel, Dieter Draxelmayr, Gernot Kubin. 1394-1397 [doi]
• Programmable switched-current floating-gate cellsPhil Corbishley, Esther Rodríguez-Villegas. 1398-1401 [doi]
• Time-interleaved switched-capacitor filter for reconfigurable triple-band delta-sigma converterDaeik D. Kim, Martin A. Brooke. 1402-1405 [doi]
• A novel current-conveyor-based switched-capacitor integratorHooman Kaabi, Mohammad-Reza Jahed Motlagh, Ahmad Ayatollahi. 1406-1408 [doi]
• A new multiply-by-two gain-stage with enhanced immunity to capacitor-mismatchHashem Zare-Hoseini, Omid Shoaei, Izzet Kale. 1409-1412 [doi]
• Inverter-based switched current circuit for very low-voltage and low-power applicationsFathi A. Farag, Carlos Galup-Montoro, Márcio C. Schneider. 1413-1416 [doi]
• A high speed, high resolution, low voltage current mode sample and holdHold Omid Rajaee, Mehrdad Sharif Bakhtiar. 1417-1420 [doi]
• An improved algorithm for maximum-likelihood based approach for a multitarget tracking problemLiang Chen, Qiang Hua, H. K. Kwan. 1421-1424 [doi]
• Optimal periodic sampling sequences for nearly-alias-free digital signal processingAndrzej Tarczynski, Dongdong Qu. 1425-1428 [doi]
• Normalized confidence factors for robust direction of arrival estimationTuomo W. Pirinen. 1429-1432 [doi]
• An efficient method for estimation of autoregressive signals in noiseWei Xing Zheng. 1433-1436 [doi]
• Symbol-rate estimation based on filter bankZaihe Yu, Yun Q. Shi, Wei Su. 1437-1440 [doi]
• Pilot-aided DOA estimation for CDMA communication systemsNanyan Y. Wang, Panajotis Agathoklis, Andreas Antoniou. 1441-1444 [doi]
• New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression eliminationYasuhiro Takahashi, Michio Yokoyama. 1445-1448 [doi]
• Implementation of low-complexity FIR filters using serial arithmeticKenny Johansson, Oscar Gustafsson, Lars Wanhammar. 1449-1452 [doi]
• A low power decimation filter architecture for high-speed single-bit sigma-delta modulationOscar Gustafsson, Henrik Ohlsson. 1453-1456 [doi]
• A high performance distributed-parallel-processor architecture for 3D IIR digital filtersArjuna Madanayake, Leonard T. Bruton. 1457-1460 [doi]
• A VLSI architecture for a high-speed computation of the 1D discrete wavelet transformChengjun Zhang, Chunyan Wang, M. Omair Ahmad. 1461-1464 [doi]
• Memory access overhead reduction for a digital color copier implementation using a VLIW digital signal processorMoonseok Kang, Wonyong Sung. 1465-1468 [doi]
• Horseshoes, homoclinic connections and global chaos in current-mode controlled DC/DC convertersDong Dai, Yue Ma, Chi K. Michael Tse. 1469-1472 [doi]
• N-scroll chaotic attractors from a general jerk circuitSimin Yu, Jinhu Lu, Henry Leung, Guanrong Chen. 1473-1476 [doi]
• Solvable 2-dimensional rational chaotic map defined by Jacobian elliptic functionsA. Kato, T. Kohda. 1477-1480 [doi]
• Back propagation learning of neural networks with chaotically-selected affordable neuronsYoko Uwate, Yoshifumi Nishio. 1481-1484 [doi]
• On two-parameter non-smooth bifurcations in power convertersFabiola Angulo, Mario di Bernardo. 1485-1488 [doi]
• Experimental performance evaluation of a low-EMI chaos-based current-programmed DC/DC boost converterM. Balestra, Marco Lazzarini, Gianluca Setti, Riccardo Rovatti. 1489-1492 [doi]
• An adaptive fast full search motion estimation algorithm for H.264Chen-Fu Lin, Jin-Jang Leou. 1493-1496 [doi]
• Transform-domain intra prediction for H.264Chen Chen, Ping-Hao Wu, Homer H. Chen. 1497-1500 [doi]
• An improved frame and macroblock layer bit allocation scheme for H.264 rate controlMinqiang Jiang, Nam Ling. 1501-1504 [doi]
• Fast multi-frame motion estimation for H.264 and its applications to complexity-aware streamingShu-Fa Lin, Meng-Ting Lu, Ming-Yu Chen, Chia-Ho Pan. 1505-1508 [doi]
• Fast three step intra prediction algorithm for 4×4 blocks in H.264Chao-Chung Cheng, Tian-Sheuan Chang. 1509-1512 [doi]
• Fast block motion estimation with early acceptance technique in H.264/JVTChi-Wai Lam, Lai-Man Po. 1513-1516 [doi]
• Development of a microwave receiving and transmission system using an optical modulatorTakayuki Yamashita, Kazuhisa Haeiwa, Toshihiro Negishi, Izuru Murasaki, Yoshikazu Toba, Masatoshi Onizawa. 1517-1520 [doi]
• A comparison of equalizers for compensating polarization-mode dispersion in 40-Gb/s optical systemsJonathan Sewter, Anthony Chan Carusone. 1521-1524 [doi]
• A 0.18-µm 10-GHz CMOS ring oscillator for optical transceiversHai Qi Liu, Wang Ling Goh, L. Siek. 1525-1528 [doi]
• Four-channel CMOS photoreceiver array for parallel optical interconnectsJu-Hyoung Mun, Sung Min Park, Myung-Ryong Nam. 1529-1532 [doi]
• A switched delay line based optical switch architecture with a bypass lineHo-Ting Wu, Kai-Wei Ke, Wang-Rong Chang, Hui-Tang Lin. 1533-1536 [doi]
• A 400Mbps CMOS spatially-modulated photoreceiver for optical storageEuhan Chong, Khoman Phang. 1537-1540 [doi]
• MIRROR: an interactive content based image retrieval systemKa-Man Wong, Kwok-Wai Cheung, Lai-Man Po. 1541-1544 [doi]
• Scheduling design for distributed video-on-demand serversYinqing Zhao, C. C. Jay Kuo. 1545-1548 [doi]
• Program segmentation for TV videosLiuhong Liang, Hong Lu, Xiangyang Xue, Yap-Peng Tan. 1549-1552 [doi]
• Content-based scalable sports video retrieval systemHuang-Chia Shih, Chung-Lin Huang. 1553-1556 [doi]
• A novel BP-based image retrieval systemJun-Hua Han, De-Shuang Huang. 1557-1560 [doi]
• A 110 dB CMRR/PSRR/gain CMOS operational amplifierVadim Ivanov, Igor M. Filanovsky. 1561-1564 [doi]
• Hybrid cascode compensation for two-stage CMOS operational amplifiersMohammad Yavari, Omid Shoaei, Francesco Svelto. 1565-1568 [doi]
• High-performance CMOS pseudo-differential amplifierA. D. Grasso, Salvatore Pennisi. 1569-1572 [doi]
• High-performance CMOS current feedback operational amplifierSalvatore Pennisi. 1573-1576 [doi]
• A design of controllableKhanittha Kaewdang, Wanlop Surakampontorn, Nobuo Fujii. 1577-1580 [doi]
• A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuitsSai-Weng Sin, Seng-Pan U., Rui Paulo Martins. 1581-1584 [doi]
• A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuitsSai-Weng Sin, Seng-Pan U., Rui Paulo Martins. 1585-1588 [doi]
• Current-mode universal biquad circuit using MO-OTAs and DO-CCIITakao Tsukutani, Yasuaki Sumi, Masami Higashimura, Yutaka Fukui. 1589-1592 [doi]
• A low-power method adding continuous variable gain to amplifiersT. Halvorsrod, O. Birkenes, C. Eichrodt. 1593-1596 [doi]
• Design consideration for lowering sensitivity to out of band interference of negative feedback amplifiersE. D. Totev, Chris J. M. Verhoeven. 1597-1600 [doi]
• A 2.4 GHz 82 dB-Omega fully differential CMOS transimpedance amplifier for optical receiver based on wide-swing cascode topologyYanjie Wang, Rabin Raut. 1601-1605 [doi]
• Cascaded double-stage configuration for high-performance broadband amplification in CMOSApisak Worapishet, I. Roopkom. 1606-1609 [doi]
• Influence of frequency compensation on the linearity of negative feedback amplifiersKoen van Hartingsveldt, Chris J. M. Verhoeven, J. Willms. 1610-1613 [doi]
• A 3 Gb/s 80 dB CMOS differential transimpedance amplifier for optical communication systemsWacharapol Pongpalit, Varakorn Kasemsuwan, Hyung Keun Ahn. 1614-1617 [doi]
• Power dependence of feedback amplifiers on opamp architectureYu Lin, Vipul Katyal, Randall L. Geiger. 1618-1621 [doi]
• Digitally controlled fully differential current conveyor: CMOS realization and applicationsSoliman A. Mahmoud, Mohammed A. Hashiesh, Ahmed M. Soliman. 1622-1625 [doi]
• A sub-word-parallel Galois field multiply-accumulate unit for digital signal processorsSubhadeep Roy. 1626-1629 [doi]
• A configurable dual moduli multi-operand modulo adderChip-Hong Chang, Shibu Menon, Bin Cao, Thambipillai Srikanthan. 1630-1633 [doi]
• An MCML four-bit ripple-carry adder design in 1 GHz rangeShahnam Khabiri, Maitham Shams. 1634-1637 [doi]
• Low power parallel multiplier with column bypassingMing-Chen Wen, Sying-Jyan Wang, Yen-Nan Lin. 1638-1641 [doi]
• Design of power-aware multiplier with graceful quality-power trade-offsJieh-Hwang Yen, Lan-Rong Dung, Chi-Yuan Shen. 1642-1645 [doi]
• Equalizing data-path for processing speed determination in block level pipeliningXiaoyao Liang, Akshay Athalye, Sangjin Hong. 1646-1649 [doi]
• Dual sense amplified bit lines (DSABL) architecture for low-power SRAM designRamy E. Aly, Mohamed A. Elgamel, Magdy A. Bayoumi. 1650-1653 [doi]
• A low-leakage twin-precision multiplier using reconfigurable power gatingMagnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, Henrik Eriksson. 1654-1657 [doi]
• An energy-efficient skew compensation technique for high-speed skew-sensitive signalingLei Wang. 1658-1661 [doi]
• Area, power, and pin efficient bus transceiver using multi-bit-differential signalingDonald M. Chiarulli, Jason D. Bakos, Joel R. Martin, Steven P. Levitan. 1662-1665 [doi]
• Enhancing the efficiency of cluster voltage scaling technique for low-power applicationBehnam Amelifard, Ali Afzali-Kusha, Ahmad Khademzadeh. 1666-1669 [doi]
• A low-power high-SFDR CMOS direct digital frequency synthesizerJinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh. 1670-1673 [doi]
• Domino logic with an efficient variable threshold voltage keeperA. Amirabadi, Y. Mortazavi, Nariman Moezzi Madani, Ali Afzali-Kusha, Mehrdad Nourani. 1674-1677 [doi]
• A low dynamic power and low leakage power CMOS square-root circuitTadayoshi Enomoto, Nobuaki Kobayashi. 1678-1681 [doi]
• A robust adaptive cross microphone arrayJianfeng Chen, Koksoon Phua, Louis Shue, Hanwu Sun. 1682-1685 [doi]
• A combined TDA/FDA adaptive schema for stereophonic acoustic echo cancellationMohammed A. Khasawneh, Khaled A. Mayyas, R. M. Shalabi, Monther I. Haddad. 1686-1689 [doi]
• Image encryption using progressive cellular automata substitution and SCANRong-Jian Chen, Wen-Kai Lu, Jui-Lin Lai. 1690-1693 [doi]
• Study of a least-squares type method for noisy FIR filteringWei Xing Zheng. 1694-1697 [doi]
• Optimal user weighting fusion in DWT domain on-line signature verificationIsao Nakanishi, Hiroyuki Sakamoto, Yoshio Itoh, Yutaka Fukui. 1698-1701 [doi]
• A hardware generator for multi-point distributed random variablesNicola Bruti Liberati, Eckhard Platen, Filippo Martini, Massimo Piccardi. 1702-1705 [doi]
• Direct-digital synthesis using delta-sigma modulated signalsYuichiro Orino, Minoru Kuribayashi Kurosawa, Takashi Katagiri. 1706-1709 [doi]
• Performance of a type-based digital predistorter for solid-state power amplifier linearizationXinping Huang, Mario Caron. 1710-1713 [doi]
• Diversity gain s influence on MIMO s detectionHui Zhao, Kan Zheng, Wenbo Wang. 1714-1717 [doi]
• Multiuser scheduling for downlink in multi-antenna wireless systemsDeepali Arora, Panajotis Agathoklis. 1718-1721 [doi]
• Robust adaptive channel estimation of OFDM systems in time-varying narrowband interferenceZhiguo Zhang, Shing-Chow Chan, Hui Cheng. 1722-1725 [doi]
• Joint frequency offset estimation and multiuser detection using genetic algorithm in MC-CDMAHoang-Yang Lu, Wen-Hsien Fang. 1726-1729 [doi]
• Reduced-rank antenna selection for MIMO DS-CDMA channelsYu-Hao Chang, Xiaoli Yu. 1730-1733 [doi]
• Performance of the pulse pair method with an optimal lag value for frequency estimation in fading channelsSaman S. Abeysekera, Zhi Wang. 1734-1737 [doi]
• Integrated mixed-signal optoelectronic system-on-a-chip sensorDae-Ik Kim, Mikkel A. Thomas, Jeffrey J. Lillie, Karla S. Dennis, Benita M. Comeau, Martin A. Brooke, Nan M. Jokerst, Stephen E. Ralph, Clifford L. Henderson. 1738-1741 [doi]
• A 60 ns 500×12 0.35µm CMOS low-power scanning read-out IC for cryogenic infra-red sensorsFrancisco Serra-Graells, Bertrand Misischi, Eduardo Casanueva, César Méndez, Lluís Terés. 1742-1745 [doi]
• Instrumentation of YSZ oxygen sensor calibration in liquid lead-bismuth eutecticXiaolong Wu, Jian Ma, Yingtao Jiang, Bingmei Fu, Wei Hang, Jinsuo Zhang, Ning Li. 1746-1749 [doi]
• An automatic acoustic bathroom monitoring systemJianfeng Chen, Jianmin Zhang, Alvin Harvey Kam, Louis Shue. 1750-1753 [doi]
• A PWM DPS with pixel-level reconfigurable 4/8-bit counter/SRAMYat-Fong Yung, Amine Bermak. 1754-1757 [doi]
• Sensor array for multiple emission gas measurementsMatti Kutila, Jouko Viitanen. 1758-1761 [doi]
• Pulse-based interface circuits for SPR sensing systems [analyte concentration measurement]Lisa E. Hansen, Matthew M. W. Johnston, Denise M. Wilson. 1762-1765 [doi]
• Network-on-chip-centric approach to interleaving in high throughput channel decodersChristian Neeb, Michael J. Thul, Norbert Wehn. 1766-1769 [doi]
• Power analysis of link level and end-to-end data protection in networks on chipAxel Jantsch, Robert Lauter, Arseni Vitkovski. 1770-1773 [doi]
• Effect of traffic localization on energy dissipation in NoC-based interconnectPartha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Res Saleh. 1774-1777 [doi]
• A methodology for design, modeling, and analysis of networks-on-chipJiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar. 1778-1781 [doi]
• Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chipMehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne. 1782-1785 [doi]
• VLSI architecture based on packet data transfer scheme and its applicationYuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi. 1786-1789 [doi]
• Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVCTung-Chien Chen, Yu-Wen Huang, Chuan-Yung Tsai, Chao-Tsung Huang, Liang-Gee Chen. 1790-1793 [doi]
• A novel VLSI architecture for VBSME in MPEG-4 AVC/H.264Cao Wei, Mao Zhi-gang. 1794-1797 [doi]
• Architecture of global motion compensation for MPEG-4 advanced simple profileYi-Hau Chen, Ching-Yeh Chen, Liang-Gee Chen. 1798-1801 [doi]
• Combined 2-D transform and quantization architectures for H.264 video codersHeng-Yao Lin, Yi-Chih Chao, Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang. 1802-1805 [doi]
• Combined frame memory architecture for motion compensation in video decodingNelson Yen-Chung Chang, Tian-Sheuan Chang. 1806-1809 [doi]
• An H.264/AVC decoder with 4×4-block level pipelineTing-An Lin, Sheng-Zen Wang, Tsu-Ming Liu, Chen-Yi Lee. 1810-1813 [doi]
• Multiplication by two integers using the minimum number of addersAndrew G. Dempster, Malcolm D. Macleod. 1814-1817 [doi]
• Signed power-of-two allocation scheme for the design of lattice orthogonal filter banksYa Jun Yu, Yong Ching Lim. 1819-1822 [doi]
• I/sup 2/CRA: contention resolution algorithm for intra- and inter-coefficient common subexpression eliminationFei Xu, Chip-Hong Chang, Ching-Chuen Jong. 1823-1826 [doi]
• Design and implementation of multiplierless adjustable fractional-delay all-pass filtersJuha Yli-Kaakinen, Tapio Saramäki. 1827-1830 [doi]
• Design of FIR digital filters with discrete coefficients via convex relaxationWu-Sheng Lu. 1831-1834 [doi]
• Further complexity reduction of parallel FIR filtersChao Cheng, Keshab K. Parhi. 1835-1838 [doi]
• Glitch-free discretely programmable clock generation on chipMaurice Meijer, Francesco Pessolano, José Pineda de Gyvez. 1839-1842 [doi]
• A three-level toggle-avoid bus signaling schemeYan Zhang, Travis N. Blalock, Mircea R. Stan. 1843-1846 [doi]
• A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatchTae-Hyoung Kim, Uk-Rae Cho, Hyun-Geun Byun. 1847-1850 [doi]
• A distributed FIFO scheme for on chip communicationRay Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias. 1851-1854 [doi]
• A multifunctional high-voltage driver chip for low-power mobile display systemsJan Doutreloigne, Miguel Vermandel, Herbert De Smet, André Van Calster. 1855-1858 [doi]
• Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applicationsMing-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai. 1859-1862 [doi]
• Performance constrained floorplanning based on partial clustering [IC layout]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng. 1863-1866 [doi]
• Wire-driven microarchitectural design space explorationMongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee. 1867-1870 [doi]
• Integrated routing resource assignment for RLC crosstalk minimizationYici Cai, Bin Liu, Qiang Zhou, Xianlong Hong. 1871-1874 [doi]
• Placement for the reconfigurable datapath architectureYen-Tai Lai, Hsin-Ya Lai, Chia-Nan Yeh. 1875-1878 [doi]
• Simple yet effective algorithms for block and I/O buffer placement in flip-chip designHao-Yueh Hsieh, Ting-Chi Wang. 1879-1882 [doi]
• Fixed-outline floorplanning with constraints through instance augmentationRong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani. 1883-1886 [doi]
• High light-load efficiency charge pumpsChristian Falconi, Giancarlo Savone, Arnaldo D Amico. 1887-1890 [doi]
• Efficiency comparison between doubler and Dickson charge pumpsDavide Baderna, Alessandro Cabrini, Guido Torelli, Marco Pasotti. 1891-1894 [doi]
• Charge redistribution loss consideration in optimal charge pump designWing-Hung Ki, Feng Su, Chi-Ying Tsui. 1895-1898 [doi]
• A 5V charge pump in a standard 1.8-V 0.18-µm CMOS processT. Hasan, Torsten Lehmann, Chee Yee Kwok. 1899-1902 [doi]
• Heap charge pump optimisation by a tapered architectureR. Arona, Edoardo Bonizzoni, Franco Maloberti, Guido Torelli. 1903-1906 [doi]
• Gate control strategies for high efficiency charge pumpsFeng Su, Wing-Hung Ki, Chi-Ying Tsui. 1907-1910 [doi]
• Quantization errors in committee machine for gas sensor applicationsMinghua Shi, Amine Bermak, Sofiane Brahim-Belhouari. 1911-1914 [doi]
• A 100×100 pixels orientation-selective multi-chip vision systemKazuhiro Shimonomura, Tetsuya Yagi. 1915-1918 [doi]
• A real-time spike-domain sensory information processing system [image processing applications]R. Jacob Vogelstein, Udayan Mallik, Eugenio Culurciello, Gert Cauwenberghs, Ralph Etienne-Cummings. 1919-1922 [doi]
• Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filtersKazuki Nakada, Tetsuya Asai, Yoshihito Amemiya. 1923-1926 [doi]
• Rich spike-synchronization phenomena of pulse-coupled bifurcating neuronsYoshio Kon no, Toshimichi Saito, Hiroyuki Torikai. 1927-1931 [doi]
• Novel µ-power log-domain integratorsW. Aly-Mekawi, Ezz I. El-Masry. 1932-1935 [doi]
• A low voltage CMOS multiplier for high frequency equalizationJustin P. Abbott, Calvin Plett, John W. M. Rogers. 1936-1939 [doi]
• A low current consumption CMOS latched comparator for body-implanted chipM. Kiyoyama, Michihisa Onoda, Yoshinobu Tanaka. 1940-1943 [doi]
• On the analog generation of pink noise from white noiseA. L. Dalcastangê, Sidnei Noceti Filho. 1944-1947 [doi]
• Integrating lumped networks into full wave TLM/FDTD methods using passive discrete circuit modelsBaohua Wang, Pinaki Mazumder. 1948-1951 [doi]
• Field programmable Gm-C array for wide frequency range bandpass filter applicationsEric Lebel, Ali Assi, Mohamad Sawan. 1952-1955 [doi]
• Accuracy limitations of pipelined ADCsPatrick J. Quinn, Arthur H. M. van Roermund. 1956-1959 [doi]
• A new ratio-independent A/D conversion technique for high-resolution pipeline A/D convertersByung Geun Lee, Shouli Yan. 1960-1963 [doi]
• Design and optimization of multi-bit front-end stage and scaled back-end stages of pipelined ADCsPatrick J. Quinn, Arthur H. M. van Roermund. 1964-1967 [doi]
• kT/C constrained optimization of power in pipeline ADCsYu Lin, Vipul Katyal, Mark Schlarmann, Randall L. Geiger. 1968-1971 [doi]
• A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniquesHsin-Hung Ou, Bin-Da Liu. 1972-1975 [doi]
• Full calibration digital techniques for pipeline ADCsAntonio J. Ginés, Eduardo J. Peralías, Adoración Rueda. 1976-1979 [doi]
• A low-power, programmable bandpass filter section for higher-order filter-bank applicationsDavid W. Graham, Paul D. Smith, Richard Ellis, Ravi Chawla, Paul E. Hasler. 1980-1983 [doi]
• Low-voltage programmable g::m::-C filter for hearing aids using dynamic gate biasingLouie Pylarinos, Khoman Phang. 1984-1987 [doi]
• A compact nA/V CMOS triode-transconductor and its application to very-low frequency filtersJader A. De Lima, Wouter A. Serdijn. 1988-1991 [doi]
• Wave log-domain filtersMykhaylo A. Teplechuk, John I. Sewell. 1992-1995 [doi]
• Complex wave filters and wave group-delay equalisers in log-domainMykhaylo A. Teplechuk, John I. Sewell. 1996-1999 [doi]
• 1 V compact class-AB CMOS log filtersFrancisco Serra-Graells, Xavier Redondo. 2000-2003 [doi]
• Symmetry-based analytically closed-form design of variable fractional-delay FIR digital filtersTian-Bo Deng, Yong Lian. 2004-2007 [doi]
• A decomposition technique for cascaded IIR-like filter blocks generating linear-phase FIR filtersPeyman Arian, Tapio Saramäki, Adly T. Fam. 2008-2011 [doi]
• Synthesis of narrowband linear-phase FIR filters with a piecewise-polynomial impulse responseRaija Lehto, Tapio Saramäki, Olli Vainio. 2012-2015 [doi]
• Interpolation factor analysis for jointly optimized frequency-response masking filtersJianghong Yu, Yong Lian. 2016-2019 [doi]
• A novel low-complexity method for parallel multiplierless implementation of digital FIR filtersYongtao Wang, Kaushik Roy. 2020-2023 [doi]
• Design of complex FIR filters using the frequency-response masking approachYongzhi Liu, Zhiping Lin. 2024-2027 [doi]
• A new minimax design for 2D FIR filters with low group delayWu-Sheng Lu, Takao Hinamoto. 2028-2031 [doi]
• A low-complexity scanned-array 3D IIR frequency-planar filterArjuna Madanayake, Leonard T. Bruton. 2032-2035 [doi]
• A perfect reconstruction filter bank with irrational down-sampling factorsSoo-Chang Pei, Meng-Ping Kao, Jian-Jiun Ding. 2036-2039 [doi]
• Fractional polynomials and nD systemsKrzysztof Galkowski, Anton Kummert. 2040-2043 [doi]
• A constructive procedure for multidimensional realization and LFR uncertainty modellingLi Xu, Huijin Fan, Zhiping Lin, Yegui Xiao, Yoshihisa Anazawa. 2044-2047 [doi]
• Demosaicing with improved edge direction detectionXiaomeng Wang, Weisi Lin, Ping Xue. 2048-2051 [doi]
• Approximate optimal demodulation for multi-user binary coherent chaos-shift-keying communication systemsJi Yao, Anthony J. Lawrance. 2052-2055 [doi]
• A novel code acquisition algorithm and its application to Markov spreading codesTohru A. Khan, Nobuoki Eshima, Yutaka Jitsumatsu, Tohru Kohda. 2056-2059 [doi]
• Stroboscopic model and bifurcations in TCP/REDMingjian Liu, Hui Zhang, Ljiljana Trajkovic. 2060-2063 [doi]
• An analog-to-digital converter with dynamic window for optimal rational number approximationMasaaki Naka, Toshimichi Saito, Aya Tanaka. 2064-2067 [doi]
• Wavelet-based estimation of long-range dependence in MPEG video tracesNikola Cackov, Zelimir Lucic, Momcilo Bogdanov, Ljiljana Trajkovic. 2068-2071 [doi]
• Nonlinear output feedback control of TCP/AQM networksYi Fan, Zhong-Ping Jiang, Shivendra S. Panwar, Hao Zhang. 2072-2075 [doi]
• Reduced latency arithmetic decoder for JPEG2000 block decodingMichael Dyer, David Taubman, Saeid Nooshabadi. 2076-2079 [doi]
• Matching pursuits using slant patterns and its dictionary design [video coding applications]Shinya Kako, Kousuke Imamura, Hideo Hashimoto. 2080-2083 [doi]
• Image compression with interpolation in wavelet-transform domainWei-Pin Lin, Chih-Ming Chen, Yung-Chang Chen. 2084-2087 [doi]
• An image compression scheme based on parametric Haar-like transformSusanna Minasyan, Jaakko Astola, David Guevorkian. 2088-2091 [doi]
• Lifting-based multi-view image codingNantheera Anantrasirichai, Cedric Nishan Canagarajah, David R. Bull. 2092-2095 [doi]
• High quality Motion JPEG2000 coding scheme based on the human visual systemRyusuke Miyamoto, Hiroaki Sugita, Yoshiteru Hayashi, Hiroshi Tsutsui, Takahiko Masuzaki, Takao Onoye, Yukihiro Nakamura. 2096-2099 [doi]
• A full-range all-pass variable phase shifter for multiple antenna receiversHossein Zarei, Allan Ecker, Jinho Park, David J. Allstot. 2100-2103 [doi]
• Design considerations for a 10 GHz CMOS transmit-receive switchK. M. Naegle, Subhanshu Gupta, David J. Allstot. 2104-2107 [doi]
• A gain/phase mismatch calibration procedure for RF I/Q downconvertersStefano Vitali, Eleonora Franchi, Antonio Gnudi. 2108-2111 [doi]
• 8 GHz tunable CMOS quadrature generator using differential active inductorsFarsheed Mahmoudi, C. Andre T. Salama. 2112-2115 [doi]
• A 5.25 GHz CMOS even harmonic mixer with an enhancing inductanceMing-Feng Huang, Shuenn-Yuh Lee, Chung J. Kuo. 2116-2119 [doi]
• A new CMOS wideband RF front-end for multistandard low-IF wireless receiversIgor M. Filanovsky, Md. Mahbub Reja, Ahmed Allam. 2120-2123 [doi]
• An integrated rate control scheme for TCP-friendly MPEG-4 video transmissionJun-Yao Wang, Wen-Shyang Hwang, Wen-Fong Wang, Ce-Kuen Shieh. 2124-2127 [doi]
• Improved and fast algorithms for intra 4×4 mode decision in H.264/AVCChao-Hsuing Tseng, Hung-Ming Wang, Jar-Ferr Yang. 2128-2131 [doi]
• Tightly-coupled MPEG-4 video encoder framework on asymmetric dual-core platformsCheng-Nan Chiu, Chien-Tang Tseng, Chun-Jen Tsai. 2132-2135 [doi]
• Hardware-efficient computing architecture for motion compensation interpolation in H.264 video codingWen-Nung Lie, Han-Ching Yeh, Tom C.-I. Lin, Chien-Fa Chen. 2136-2139 [doi]
• A memory-efficient deblocking filter for H.264/AVC video codingTsu-Ming Liu, Wen-Ping Lee, Ting-An Lin, Chen-Yi Lee. 2140-2143 [doi]
• Variable frame rate transcoding considering motion information [video transcoding]Haiyan Shu, Lap-Pui Chau. 2144-2147 [doi]
• Programming analog computational memory elements to 0.2 accuracy over 3.5 decades using a predictive methodAbhishek Bandyopadhyay, Guillermo J. Serrano, Paul E. Hasler. 2148-2151 [doi]
• Ramp voltage supply using adiabatic charging principlePui-Tak So, Cheong-fat Chan, Chiu-sing Choy, Kong-Pang Pun. 2152-2155 [doi]
• A 0.8 V, 360 nW Gm-C biquad based on FGMOS transistors [biquadratic filter]Esther Rodríguez-Villegas. 2156-2159 [doi]
• A 0.9 V offset compensated FGMOS comparatorEsther Rodríguez-Villegas. 2160-2163 [doi]
• Biasing techniques for subthreshold MOS resistive gridsKeng Hoong Wee, Ji-Jon Sit, Rahul Sarpeshkar. 2164-2167 [doi]
• Programmable floating-gate CMOS resistorsErhan Ozalevli, Paul E. Hasler. 2168-2171 [doi]
• Indirect programming of floating-gate transistorsDavid W. Graham, Ethan Farquhar, Brian P. Degnan, Christal Gordon, Paul E. Hasler. 2172-2175 [doi]
• A fully differential line driver with on-chip calibrated source termination for gigabit and fast Ethernet in a standard 0.13µ CMOS processDan Stiurca. 2176-2179 [doi]
• Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interfaceGunjan Mandal, Pradip Mandal. 2180-2183 [doi]
• A CMOS front-end architecture for hard-disk drive read-channel equalizerTertulien Ndjountche, Fa-Long Luo, Christophe Bobda. 2184-2187 [doi]
• Soft fault test and diagnosis for analog circuitsPeng Wang, Shiyuan Yang. 2188-2191 [doi]
• A clock recovery circuit using half-rate 4×-oversampling PDHyung-Wook Jang, Sung-Sop Lee, Jin-Ku Kang. 2192-2195 [doi]
• Built-in current sensor with reduced voltage drop using thin-film transistorsAlkis A. Hatzopoulos, Stelios Siskos, Charalambos A. Dimitriadis, Nikolaos P. Papadopoulos. 2196-2199 [doi]
• Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterizationChristian Jesús B. Fayomi, Gordon W. Roberts, Mohamad Sawan. 2200-2203 [doi]
• Digital built-in self-test of CMOS analog iterative decodersMimi Yiu, Chris Winstead, Vincent C. Gaudet, Christian Schlegel. 2204-2207 [doi]
• Built-in self-test for automatic analog frequency response measurementDayu Yang, Foster F. Dai, Charles E. Stroud. 2208-2211 [doi]
• Linear-time algorithm for computing minimum checkpoint sets for simulation-based verification of HDL programsElena Dubrova. 2212-2215 [doi]
• The chaotic numbers of the bipartite and tripartite graphsNam-Po Chiang. 2216-2218 [doi]
• Decoupling capacitance allocation in noise-aware floorplanning based on DBL representationJin-Tai Yan, Kai-Ping Lin, Yen-Hsiang Chen. 2219-2222 [doi]
• Efficient computation of dominators in multiple-output circuit graphsRené Krenz. 2223-2226 [doi]
• Hardware reduction using a 6-connectivity interconnection network over a 4-connectivity VLSI asynchronous array processorValentin Gies, Thierry M. Bernard, Alain Mérigot. 2227-2230 [doi]
• Maximum weight matching-based algorithms for k-edge-connectivity augmentation of a graphToshimasa Watanabe, Satoshi Taoka, Toshiya Mashima. 2231-2234 [doi]
• An AQM routing control for reducing congestion in communication networksSabato Manfredi. 2235-2238 [doi]
• GA-based applications for routing with an upper bound constraintJun Inagaki, Miki Haseyama. 2239-2242 [doi]
• Analyses of intermodulation effects in fractional-N frequency synthesisPaul V. Brennan, Dai Jiang, Jianxin Zhang. 2243-2246 [doi]
• Behavioral modeling and simulation of weakly nonlinear sampled-data systemsEwout Martens, Georges G. E. Gielen. 2247-2250 [doi]
• Analytical expression of HD3 due to non-linear MOS switch in MOSFET-C sample and hold circuitsSomnath Sengupta. 2251-2254 [doi]
• Analysis of jitter peaking and jitter accumulation in re-circulating delay-locked loopsPooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi. 2255-2258 [doi]
• Root iterations and the computation of minimum and maximum zeros of polynomialsMohammed A. Hasan. 2259-2262 [doi]
• Phase noise spectra analysis for LC oscillatorsHua Zhang, Dian Zhou, Yi Hu, Ruiming Li, Jianzhong Zhang. 2263-2266 [doi]
• A model-based approach for the development of LMS algorithms [adaptive filter applications]Guang Deng, Wai-Yin Ng. 2267-2270 [doi]
• A new approach for non-uniform subband adaptive filteringYoshinori Ichikawa, Toshihiro Furukawa. 2271-2274 [doi]
• Adaptive filtering using constrained subband updatesWoon S. Gan, Kong A. Lee. 2275-2278 [doi]
• Performance of two novel fast affine projection adaptation algorithmsHeping Ding. 2279-2282 [doi]
• Coordinate descent iterations in pseudo affine projection algorithmFelix Albu, Constantine Kotropoulos. 2283-2286 [doi]
• Adaptive IIR notch filters: state-space approachAloys Mvuma, Shotaro Nishimura, Takao Hinamoto. 2287-2290 [doi]
• Structured stochastic optimization strategies for problems with ill-conditioned error surfacesS. Pal, D. J. Krusienski, W. Kenneth Jenkins. 2291-2294 [doi]
• Modified Taylor-series method for source and receiver localization using TDOA measurements with erroneous receiver positionsDominic K. C. Ho, La-or Kovavisaruch. 2295-2298 [doi]
• Generalized n-dimensional k-order systems: computing the transfer functionGeorge E. Antoniou, Marinos T. Michael. 2299-2302 [doi]
• Hilbert pair of wavelets via the matching design technique [matched filters]David B. H. Tay, Marimuthu Palaniswami. 2303-2306 [doi]
• The missing observations theorem and a new proof of Levinson s recursionCharles W. Therrien. 2307-2308 [doi]
• On the time-frequency content of Weyl-Heisenberg frames generated from odd and even functions [signal representation applications]Lisandro Lovisolo, M. G. de Pinho, Eduardo A. B. da Silva, Paulo S. R. Diniz. 2309-2312 [doi]
• Image compression using texture modelingLahouari Ghouti, Ahmed Bouridane, Mohammad K. Ibrahim. 2313-2316 [doi]
• Unconstrained functional criteria for canonical correlation analysisM. A. Hasan. 2317-2320 [doi]
• Some properties of generalized 2-D mirror image and anti mirror image polynomialsVenkat Ramachandran, Majid Ahmadi, Christian S. Gargour. 2321-2324 [doi]
• Simulation of quantum cellular automaton circuits based on genetic simulated annealing algorithmWang Sen, Cai Li. 2325-2328 [doi]
• Why area might reduce power in nanoscale CMOSPaul Beckett, S. C. Goldstein. 2329-2332 [doi]
• Quantum circuits for stabilizer codesChien-Hsing Wu, Yan-Chr Tsai, Hwa-Long Tsai. 2333-2336 [doi]
• Exact noise analysis of a CMOS BDJ APSSylvain Feruglio, Victor Fouad Hanna, Georges Alquié, Gabriel Vasilescu. 2337-2340 [doi]
• A novel oscillation circuit using a resonant-tunneling diodeNaokazu Muramatsu, Hiroshi Okazaki, Takao Waho. 2341-2344 [doi]
• Low-power spatial computing using dynamic threshold devicesPaul Beckett. 2345-2348 [doi]
• On the impact of traffic statistics on quality of service for networks on chipStefano Santi, Bill Lin, Ljupco Kocarev, Gian Mario Maggio, Riccardo Rovatti, Gianluca Setti. 2349-2352 [doi]
• Slack-time aware routing in NoC systemsDaniel Andreasson, Shashi Kumar. 2353-2356 [doi]
• An arbitration look-ahead scheme for reducing end-to-end latency in networks on chipKwanho Kim, Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo. 2357-2360 [doi]
• Self-calibrating networks-on-chipFrederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli. 2361-2364 [doi]
• A novel approach for network on chip emulationNicolas Genko, David Atienza, Giovanni De Micheli, Luca Benini, Jose Manuel Mendias, Román Hermida, Francky Catthoor. 2365-2368 [doi]
• A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chipDonghyun Kim, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo. 2369-2372 [doi]
• VLSI architectures for stereoscopic video disparity matching and object extractionJian-Hung Lin, Keshab K. Parhi. 2373-2376 [doi]
• Parallel algorithm for hardware implementation of inverse halftoningUmair F. Siddiqi, Sadiq M. Sait, Aamir A. Farooqui. 2377-2380 [doi]
• Real-time image compression based on wavelet vector quantization, algorithm and VLSI architectureSafar Hatami, Shervin Sharifi, Mahmoud Kamarei, Hossein Ahmadi. 2381-2384 [doi]
• Partial encryption of compressed images employing FPGAMamun Bin Ibne Reaz, Faisal Mohd-Yasin, S. L. Tan, H. Y. Tan, Muhammad I. Ibrahimy. 2385-2388 [doi]
• A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filteringBenjamas Tongprasit, Kiyoto Ito, Tadashi Shibata. 2389-2392 [doi]
• VLSI architecture design for a fast parallel label assignment in binary imageShyue-Wen Yang, Ming-Hwa Sheu, Hsien-Huang P. Wu, Hung-En Chien, Ping-Kuo Weng, Ying-Yih Wu. 2393-2396 [doi]
• A novel low-complexity spatio-temporal ultra wide-angle polyphase cone filter bank applied to sub-pixel motion discriminationBernhard Kuenzle, Leonard T. Bruton. 2397-2400 [doi]
• Minimization of L/sub 2/-sensitivity for a class of 2D state-space digital filters subject to L/sub 2/-scaling constraintsTakao Hinamoto, Ken-ichi Iwata, Wu-Sheng Lu. 2401-2404 [doi]
• An efficient multidimensional decimation-in-frequency FHT algorithm based on the radix-2/4 approachSaad Bouguezel, M. Omair Ahmad, M. N. S. Swamy. 2405-2408 [doi]
• Generalized alpha-VSH polynomials and stability of delta-operator based 2D discrete-time systemsHari C. Reddy, P. K. Rajan. 2409-2412 [doi]
• High-resolution DOA estimation by algebraic phase unwrapping algorithmIsao Yamada. 2413-2416 [doi]
• Optimal construction of compactly-supported multidimensional waveletsHyungju Park. 2417-2420 [doi]
• Pre-capturing static pulsed flip-flopsAliakbar Ghadiri, Hamid Mahmoodi-Meimand. 2421-2424 [doi]
• A mathematical programming approach to designing MOS current-mode logic circuitsShahnam Khabiri, Maitham Shams. 2425-2428 [doi]
• A low-power static dual edge-triggered flip-flop using an output-controlled discharge configurationMyint Wai Phyu, Wang Ling Goh, Kiat Seng Yeo. 2429-2432 [doi]
• An efficient pass-transistor-logic synthesizer using multiplexers and inverters onlyShen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen. 2433-2436 [doi]
• An approach to the design of PFSCL gatesMassimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli. 2437-2440 [doi]
• Programmable floating-gate techniques for CMOS invertersBrian P. Degnan, Richard B. Wunderlich, Paul E. Hasler. 2441-2444 [doi]
• Transition time bounded low-power clock tree constructionMin Pan, Chris C. N. Chu, J. Morris Chang. 2445-2448 [doi]
• Timing-driven global routing with efficient buffer insertionJingyu Xu, Xianlong Hong, Tong Jing. 2449-2452 [doi]
• Explicit delay metric for interconnect optimizationMin Ma, Mourad Oulmane, Nicholas C. Rumin. 2453-2456 [doi]
• Uncertainty modeling of gate delay considering multiple input switchingSatish K. Yanamanamanda, Jun Li, Janet Meiling Wang. 2457-2460 [doi]
• Timing yield estimation using statistical static timing analysisMin Pan, Chris C. N. Chu, Hai Zhou. 2461-2464 [doi]
• A non-iterative equivalent waveform model for timing analysis in presence of crosstalkKishore Kumar Muchherla, Pinhong Chen, Janet Meiling Wang. 2465-2468 [doi]
• A theoretical solution for PWM with non-ideal transient responseBin Zhou, Wing Hong Lau, Henry Shu-Hung Chung. 2469-2472 [doi]
• Efficiency-oriented switching frequency tuning for a buck switching power converterGerard Villar, Eduard Alarcón, Francesc Guinjoan, Alberto Poveda. 2473-2476 [doi]
• Fast-scale instability of single-stage power-factor-correction power suppliesXiaoqun Wu, Chi Kong Tse, Octavian Dranga, Junan Lu. 2477-2480 [doi]
• Controlling chaos in DC/DC converters using optimal resonant parametric perturbationYufei Zhou, Herbert H. C. Iu, Chi Kong Tse, Jun-Ning Chen. 2481-2484 [doi]
• Generalized analysis of integrated magnetic component based low voltage interleaved DC-DC buck converter for efficiency improvementH. N. Nagaraja, Amit Patra, Debaprasad Kastha. 2485-2489 [doi]
• Wavelet-based piecewise approximation of steady-state waveforms for power electronics circuits [power converter examples]K. C. Tam, Siu Chung Wong, Chi Kong Tse. 2490-2493 [doi]
• A new architecture for analog sampled-data neural filtersBehnam Sedighi, Behnam Analui, Mehrdad Sharif Bakhtiar. 2494-2497 [doi]
• Annealing robust Walsh function networks for modeling with outliers and digital implementationJin-Tsong Jeng, Chen-Chia Chuang. 2498-2501 [doi]
• Self-organizing neural grove: effective multiple classifier system with pruned self-generating neural treesHirotaka Inoue, Hiroyuki Narihisa. 2502-2505 [doi]
• Self organizing map based channel prediction for OFDMAH. M. S. B. Senevirathna, Katsumi Yamashita, Hai Lin. 2506-2509 [doi]
• Probabilistic computing with future deep sub-micrometer devices: a modelling approachNor H. Hamid, Alan F. Murray, David Laurenson, Scott Roy, Binjie Cheng. 2510-2513 [doi]
• Electrical and optical on-chip interconnects in scaled microprocessorsGuoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi. 2514-2517 [doi]
• A stepwise constant conductance approach for simulating resonant tunneling diodesBharat B. Sukhwani, Janet Meiling Wang. 2518-2521 [doi]
• Performance comparison of quantum-dot cellular automata addersRumi Zhang, Wei Wang, Konrad Walus, Graham A. Jullien. 2522-2526 [doi]
• QCA-based nano circuits design [adder design example]Rui Tang, Fengming Zhang, Yong-Bin Kim. 2527-2530 [doi]
• On the functional failure and switching time analysis of the MOBILE circuit [monostable-bistable logic element]Sing-Rong Li, Pinaki Mazumder, Kyounghoon Yang. 2531-2534 [doi]
• Single-electron circuit for inhibitory spiking neural network with fault-tolerant architectureTakahide Oya, Tetsuya Asai, Yoshihito Amemiya, Alexandre Schmid, Yusuf Leblebici. 2535-2538 [doi]
• A new technique for automatic error correction in Sigma-Delta modulatorsFriedel Gerfers, Maurits Ortmanns, Yiannos Manoli. 2539-2542 [doi]
• Increased jitter sensitivity in continuous- and discrete-time Sigma-Delta modulators due to finite opamp settling speedFriedel Gerfers, Maurits Ortmanns, Yiannos Manoli. 2543-2546 [doi]
• On the effects of finite and nonlinear DC-gain of the amplifiers in switched-capacitor Delta-Sigma modulatorsHashem Zare-Hoseini, Izzet Kale. 2547-2550 [doi]
• A multi-mode Sigma-Delta analog-to-digital converter for GSM, UMTS and WLANAndrea Xotta, Andrea Gerosa, Andrea Neviani. 2551-2554 [doi]
• On reducing leakage quantization noise of multistage Sigma-Delta modulator using nonlinear oscillationTeng-Hung Chang, Lan-Rong Dung, Jwin-Yen Guo. 2555-2558 [doi]
• Design of a high-frequency second-order Delta-Sigma modulatorFa-Long Luo, Rolf Unbehauen, Tertulien Ndjountche. 2559-2562 [doi]
• Novel and robust constant-g/sub m/ technique for rail-to-rail CMOS amplifier input stagesShouli Yan, Jingyu Hu, Tongyu Song. 2563-2566 [doi]
• A constant-g/sub m/ rail-to-rail op amp input stage using dynamic current scaling techniqueShouli Yan, Jingyu Hu, Tongyu Song, Edgar Sánchez-Sinencio. 2567-2570 [doi]
• Constant-g/sub m/ techniques for rail-to-rail CMOS amplifier input stages: a comparative studyShouli Yan, Jingyu Hu, Tongyu Song, Edgar Sánchez-Sinencio. 2571-2574 [doi]
• Feedforward reversed nested Miller compensation techniques for three-stage amplifiersFeng Zhu, Shouli Yan, Jingyu Hu, Edgar Sánchez-Sinencio. 2575-2578 [doi]
• Well-defined design procedure for a three-stage CMOS OTARosario Mita, Gaetano Palumbo, Salvatore Pennisi. 2579-2582 [doi]
• CMOS single-to-differential current amplifierSalvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti. 2583-2586 [doi]
• Efficient digital filter structures with minimum roundoff noise gainZixue Zhao, Gang Li, Jiong Zhou. 2587-2590 [doi]
• Design of multiplier-free state-space digital filtersTamal Bose, Zhongkai Zhang, O. Chauhan, Miloje S. Radenkovic. 2591-2594 [doi]
• Multi-output passive digital filtersH. K. Kwan. 2595-2598 [doi]
• Fourth-order structures for multiplierless realizations of bandpass and bandstop digital filters transformed from all-pole lowpass filtersMrinmoy Bhattacharya, Tapio Saramäki. 2599-2602 [doi]
• Design of two-dimensional recursive filters by using a novel genetic algorithmJinn-Tsong Tsai, Jyh-Horng Chou, Tung-Kuan Liu, Chien-Han Chen. 2603-2606 [doi]
• Wordlength determination algorithms for hardware implementation of linear time invariant systems with prescribed output accuracyS. C. Chan, K. M. Tsui. 2607-2610 [doi]
• Blind I/Q imbalance compensation in OFDM receivers based on adaptive I/Q signal decorrelationMikko Valkama, Markku Renfors, Visa Koivunen. 2611-2614 [doi]
• Peak-to-average power-ratio reduction algorithms for OFDM systems via constellation extensionYajun Kou, Wu-Sheng Lu, Andreas Antoniou. 2615-2618 [doi]
• Decision feedback IBI mitigation in OFDM systemsWen-Rong Wu, Chao-Yuan Hsu. 2619-2622 [doi]
• Fine timing synchronization using power delay profile for OFDM systemsHao Zhou, Yih-Fang Huang. 2623-2626 [doi]
• A preamble-aided symbol and frequency synchronization scheme for OFDM systemsMeng Wu, Wei-Ping Zhu. 2627-2630 [doi]
• New approximate QR-LS algorithms for minimum output energy (MOE) receivers in DS-CDMA commu