Valery Axelrad - researchr alias

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Viewing Publication 1 - 8 from 8

2013

Design and simulation of ESD-resistant ICsValery Axelrad. mixdes 2013: 29-40 [doi]

2006

Novel gate and substrate triggering techniques for deep sub-micron ESD protection devicesOleg Semenov, H. Sarbishaei, Valery Axelrad, Manoj Sachdev. mj, 37(6):526-533, 2006. [doi]

2005

3.125 Gb/s power efficient line driver with 2-level pre-emphasis and 2 kV HBM ESD protectionKrzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Sebastian Magierowski, Rafal Dlugosz, A. Dabrowski. iscas 2005: 1154-1157 [doi]

2004

Design Strategies for ESD Protection in SOCKrzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Marek Syrzycki. iwsoc 2004: 210-214 [doi]

The Impact of CMOS technology scaling on MOSFETs second breakdown: Evaluation of ESD robustnessOleg Semenov, Hossein Sarbishaei, Valery Axelrad, Manoj Sachdev. mr, 44(9-11):1817-1822, 2004. [doi]

2000

Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI DesignsValery Axelrad, Nicolas B. Cobb, M. O Brien, Thuy Do, Tom Donnelly, Yuri Granik, Emile Y. Sahouria, Victor Boksha, Artur Balasinski. isqed 2000: 461-466 [doi]

1998

Grid quality and its influence on accuracy and convergence in device simulationValery Axelrad. tcad, 17(2):149-157, 1998. [doi]

1990

Fourier method modeling of semiconductor devicesValery Axelrad. tcad, 9(11):1225-1237, 1990. [doi]

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