Chia-Sheng Wen - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 13 from 13

2017

Hierarchical Multipartite Function EvaluationShen-Fu Hsiao, Chia-Sheng Wen, Yi-Hau Chen, Kuei-Chun Huang. TC, 66(1):89-99, 2017. [doi]

2015

Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function EvaluationShen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Pramod Kumar Meher. tcas, 62(5):466-470, 2015. [doi]

2014

Compression of Lookup Table for Piecewise Polynomial Function EvaluationShen-Fu Hsiao, Chia-Sheng Wen, Po-Han Wu. dsd 2014: 279-284 [doi]

2013

Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address RemappingShen-Fu Hsiao, Hou-Jen Ko, Yu-Ling Tseng, Wen-Liang Huang, Shin-Hung Lin, Chia-Sheng Wen. tvlsi, 21(5):875-886, 2013. [doi]

Design of a programmable vertex processor in OpenGL ES 2.0 mobile graphics processing unitsShen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Li-Yao Chen. vlsi-dat 2013: 1-4 [doi]

2012

2010

Design of table-based function evaluators with reduced memory size Using a bottom-up non-uniform segmentation methodShen-Fu Hsiao, Chia-Sheng Wen, Kun-Chih Chen. apccas 2010: 1079-1082 [doi]

Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design EnvironmentShen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen. tcas, 57-II(1):21-25, 2010. [doi]

2008

Area oriented pass-transistor logic synthesis using buffer elimination and layout compactionShen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen. iscas 2008: 2022-2025 [doi]

2006

Efficient Pass-Transistor-Logic Synthesis for Sequential CircuitsShen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen. apccas 2006: 1631-1634 [doi]

2005

An efficient pass-transistor-logic synthesizer using multiplexers and inverters onlyShen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen. iscas 2005: 2433-2436 [doi]

Sign in or sign up to see more results.

runs on WebDSL