Abstract is missing.
- A distributed thread scheduler for dynamic multithreading on throughput processorsTa-Kan Yen, Hsien-Kai Kuo, Bo-Cheng Charles Lai. 1-4 [doi]
- A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6VHung-Chang Yu, Ku-Feng Lin, Kai-Chun Lin, Yu-Der Chih, Sreedhar Natarajan. 1-4 [doi]
- Current-mirror miller compensation: An improved frequency compensation technique for two-stage amplifiersMin Tan, Wing-Hung Ki. 1-4 [doi]
- An efficient deadlock-free multicast routing algorithm for mesh-based networks-on-chipKuen-Jong Lee, Chin-Yao Chang, Hung-Yang Yang. 1-4 [doi]
- Multi-processor debug in SoC and processor designsBill Penner. 1 [doi]
- Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technologyFederico A. Altolaguirre, Ming-Dou Ker. 1-4 [doi]
- Sensorless dead-time exploration for digitally controlled switching convertersBo-Ting Yeh, Chun-Hung Yang, Kai-Cheung Juang, Chien-Hung Tsai. 1-4 [doi]
- Jitter error cancellation technique in digital domain for ADCChin-Yu Lin, Tai-Cheng Lee. 1-4 [doi]
- A real-time parallel scalable video encoder for multimedia streaming systemsGuo-An Jian, Jui-Sheng Lee, Kheng-Joo Tan, Peng-Sheng Chen, Jiun-In Guo. 1-4 [doi]
- A practical NoC design for parallel DES computationR. Yuan, S.-J. Ruan, J. Gotze. 1-4 [doi]
- Enabling inter-die co-optimization in 3-D IC with TSVsChang-Tzu Lin, Tsu-Wei Tseng, Yung-Fa Chou, Chia-Hsin Lee, Ding-Ming Kwai. 1-4 [doi]
- Case study of yield learning through in-house flow of volume diagnosisPei-Ying Hsueh, Shuo-Fen Kuo, Chao-Wen Tzeng, Jih-Nung Lee, Chi-Feng Wu. 1-4 [doi]
- A low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations toleranceChing-Che Chung, Chang-Jun Li. 1-4 [doi]
- Low-cost testing of TSVs in 3D stacks with pre-bond testable diesSying-Jyan Wang, Yu-Siao Chen, Katherine Shu-Min Li. 1-4 [doi]
- Innovations in healthcare and semiconductor progressDiego Olego. 1 [doi]
- Design of a programmable vertex processor in OpenGL ES 2.0 mobile graphics processing unitsShen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Li-Yao Chen. 1-4 [doi]
- Hybrid path-diversity-aware adaptive routing with latency prediction model in Network-on-Chip systemsPo-An Tsai, Yu-Hsin Kuo, En-Jui Chang, Hsien-Kai Hsin, An-Yeu Wu. 1-4 [doi]
- Novel test analysis to improve structural coverage - A commercial experimentWen Chen, Li-C. Wang, Jayanta Bhadra, Magdy S. Abadir. 1-4 [doi]
- A fast and accurate instruction-oriented processor simulation approachPei-Chia Patty Lin, Evason Du, Ren-Song Tsay. 1-5 [doi]
- MIMO fingerprinting-based particle filter for mobile positioning systemsMu-Hsuan Chuang, Yi-Hao Lo, Bo-Yi Wu, Yuan-Hao Huang. 1-4 [doi]
- A novel on-chip current-sensing structure for current-mode DC-DC converterHongyi Wang, Xi Hu, Quanfeng Liu, Gangdong Zhao, Dongzhe Luo. 1-4 [doi]
- Microscopic degradation models for advanced technologyGennadi Bersuker. 1 [doi]
- An online recursive ICA based real-time multichannel EEG system on chip design with automatic eye blink artifact rejectionJui-Chieh Liao, Wei-Yeh Shih, Kuan-Ju Huang, Wai-Chi Fang. 1-4 [doi]
- Analysis of the leakage effect in a pipelined ADC with nanoscale CMOS technologiesChin-Yu Lin, Yen-Chuan Huang, Tai-Cheng Lee. 1-4 [doi]
- Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuitsHui-Wen Tsai, Ming-Dou Ker, Yi-Sheng Liu, Ming-Nan Chuang. 1-4 [doi]
- Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICsShu-Han Wei, Yu-Min Lee, Chia-Tung Ho, Chih-Ting Sun, Liang-Chia Cheng. 1-4 [doi]
- A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifierJunya Matsuno, Masahiro Hosoya, Masanori Furuta, Tetsuro Itakura. 1-4 [doi]
- A process-scalable RF transmitter using 90nm and 65nm Si CMOSAtsushi Shirane, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu. 1-4 [doi]
- Power and area reduction in multi-stage addition using operand segmentationChing-Da Chan, Wei-Chang Liu, Chia-Hsiang Yang, Shyh-Jye Jou. 1-4 [doi]
- An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltagesShin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa. 1-4 [doi]
- A sub-GHz mostly digital impulse radio UWB transceiver for wireless body sensor networksLei Wang, Chun-Huat Heng, Yong Lian. 1-4 [doi]
- A versatile data cache for trace buffer supportChun-Hung Lai, Yun-Chung Yang, Ing-Jer Huang. 1-4 [doi]
- A novel processor design flow using processor description language applied to a vector coprocessorMakiko Ito, Mitsuru Tomono, Yi Ge, Yoshimasa Takebe, Masahiko Toichi, Makoto Mouri, Yoshio Hirose. 1-4 [doi]
- A high effieciency DC/DC boost regulator with adaptive off/on-time controlChen-Yu Wang, Jhih-Sian Guo, Chi-Yuan Huang, Chien-Hung Tsai. 1-4 [doi]
- Efficient test and repair architectures for 3D TSV-based random access memoriesShyue-Kung Lu, Uang-Chang Lu, Seng-Wen Pong, Hao-Cheng Cheng. 1-4 [doi]
- What happens when circuits grow old: Aging issues in CMOS designSachin S. Sapatnekar. 1-2 [doi]
- A 5.2-11.8MHz octa-phase relaxation oscillator for 8-PSK FM-UWB transceiver systemsHang Lv, Bo Zhou, Dang Liu, Woogeun Rhee, Yongming Li, Zhihua Wang. 1-4 [doi]
- Design of thermal management unit with vertical throttling scheme for proactive thermal-aware 3D NoC systemsKun-Chih Chen, Shu-Yen Lin, An-Yeu Wu. 1-4 [doi]
- A low-power design methodology for sigma-delta modulators with relaxation of required circuit specificationsJia-Hua Hong, Ming-Chun Liang, Jing-Yi Wong, Shuenn-Yuh Lee. 1-4 [doi]
- RF and signal processing technologies for 4G mobile networksShingo Yamanouchi, Kazuaki Kunihiro, Shinich Hori, Masao Ikekawa, Naoki Nishi. 1-2 [doi]
- A low-power high-radix switch fabric based on low-swing signaling and partially-activated input linesDo-Gyoon Song, Jaeha Kim. 1-4 [doi]
- A low-power dual-mode continuous-time delta-sigma modulator with a folded quantizerChen-Chien Lin, Chan-Hsiang Weng, Tsung-Hsien Lin. 1-4 [doi]
- A configurable bus-tracer for error reproduction in post-silicon validationShing-Yu Chen, Ming-Yi Hsiao, Wen-Ben Jone, Tien-Fu Chen. 1-4 [doi]
- A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOSKunzhi Yu, Xuqiang Zheng, Ke Huang, Ma Xuan, Ziqiang Wang, Chun Zhang, Zhihua Wang. 1-4 [doi]
- To 4G mobile communication and beyondJiann-Ching Guey. 1-2 [doi]
- A 55-nm, 0.86-Volt operation, 75MHz high speed, 96uA/MHz low power, wide voltage supply range 2M-bit split-gate embedded FlashCaleb Y.-S. Cho, J. C. Wang, Lion Huang, Milo Weng, Y.-F. Lin, C. F. Lee, C. W. Lien, H. C. Feng, Tassa Yang, S. P. Liao, J.-J. Wu, Y. D. Chih, Sreedhar Natarajan. 1-4 [doi]
- An information hub for implantable wireless brain machine interfaceChun-Yi Yeh, Hung-Chih Chiu, Hsi-Pin Ma. 1-4 [doi]
- A case study: 3-D stacked memory system architecture exploration by ESL virtual platformHsien-Ching Hsieh, Shr-Je Lin, Chun-Nan Liu, Jen-Chieh Yeh, Shing-Wu Tung, Ding-Ming Kwai. 1-4 [doi]
- On the futility of thermal through-silicon-viasChung-Han Chou, Nien-Yu Tsai, Hao Yu, Yiyu Shi, Jui-Hung Chien, Shih-Chieh Chang. 1-6 [doi]
- A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devicesChing-Che Chung, Duo Sheng, Wei-Siang Su. 1-4 [doi]
- A low-error and Rom-free logarithmic arithmetic unit for embedded 3D graphics applicationsTsung-Ching Lin, Shin-Kai Chen, Chih-Wei Liu. 1-4 [doi]
- Electromigration- and obstacle-avoiding routing tree constructionYun-Chih Tsai, Tai-Hung Li, Tai-Chen Chen, Chung-Wei Yeh. 1-4 [doi]
- ARM next generation 64bit processors for power efficient computeJohn Goodacre. 1 [doi]
- ® technology for high-performance switch paths and tunable componentsRodd Novak. 1 [doi]
- Time-domain analog-to-digital converters with domino delay linesChang-Ming Lai, Yi-Chung Chen, Po-Chiun Huang. 1-4 [doi]
- In and out of the cloudTed Chang. 1 [doi]
- Terahertz electronics: Opportunities, challenges and technologiesThomas Lee. 1 [doi]
- A background calibration technique for fully dynamic flash ADCsYun-Shiang Shu, Jui-Yuan Tsai, Ping Chen, Tien-Yu Lo, Pao-Cheng Chiu. 1-4 [doi]
- Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS processChih-Ting Yeh, Ming-Dou Ker. 1-4 [doi]
- An FPGA-based test platform for analyzing data retention time distribution of DRAMsChih-Sheng Hou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu. 1-4 [doi]
- Energy-efficient architecture for word-based Montgomery modular multiplication algorithmJheng-Hao Ye, Tsung-Wei Hung, Ming-Der Shieh. 1-4 [doi]
- A Cycle Count Accurate TLM bus modeling approachMao Lin Li, Chen Kang Lo, Li-Chun Chen, Jen-Chieh Yeh, Ren-Song Tsay. 1-4 [doi]
- A wideband programmable-gain amplifier for 60GHz applications in 65nm CMOSYi-Keng Hsieh, Hsieh-Hung Hsieh, Liang-Hung Lu. 1-4 [doi]
- Timing-aware clock gating of pulsed-latch circuits for low power designZong-Han Yang, Tsung-Yi Ho. 1-4 [doi]
- The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3Ryohei Hori, Taisuke Ueoka, Taku Otani, Masaya Yoshikawa, Takeshi Fujino. 1-4 [doi]
- Creating options for 3D-SIC testingErik Jan Marinissen. 1-7 [doi]
- A fast-locking wide-range all-digital delay-locked loop with a starting SAR-bit prediction mechanismChia-Yu Yao, Yung-Hsiang Ho. 1-4 [doi]
- A 4.0/7.5-GHz dual-band LC VCO in 0.18-μm SiGe BiCMOS technologySanjeev Jain, Sheng-Lyang Jang, Miin-Horng Juang. 1-4 [doi]
- Real-time salient object detection engine for high definition videosYu-Jie Fu, Guan-Lin Wu, Shao-Yi Chien. 1-4 [doi]
- Thermal coupling aware task migration using neighboring core search for many-core systemsHitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang. 1-4 [doi]
- A layout-aware automatic sizing approach for retargeting analog integrated circuitsYen-Lung Chen, Yi-Ching Ding, Yu-Ching Liao, Hsin-Ju Chang, Chien-Nan Jimmy Liu. 1-4 [doi]
- Improving and optimizing reliability in future technologies with high-κ dielectricsBarry P. Linder, E. Cartier, S. Krishnan, E. Wu. 1-4 [doi]
- Reducing computation redundancy for high-efficiency view synthesisKuan-Hung Chen. 1-4 [doi]
- A 0.3 V low-power temperature-insensitive ring oscillator in 90 nm CMOS processYingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang. 1-4 [doi]
- Silicon-package-board co-design for the eye diagram prediction of a 3Gbps HDMI transmitterChung-Ming Huang, Wei-Da Guo, Chia-Re Shen, Chih-Chung Tsai. 1-3 [doi]
- A 1V 14kfps smart CMOS imager with tracking and edge-detection modes for biomedical monitoringChin Yin, Chih-Cheng Hsieh. 1-4 [doi]
- Cross-layer dynamic prefetching allocation strategies for high-performance multicoresYin-Chi Peng, Chien-Chih Chen, Chia-Jung Chang, Tien-Fu Chen, Pen-Chung Yew. 1-4 [doi]
- A successive approximation ADC with resistor-capacitor hybrid structureTing-Zi Chen, Soon-Jyh Chang, Guan-Ying Huang. 1-4 [doi]
- Automatic adaptive multi-point moment matching for descriptor system model order reductionWenhui Zhao, Grantham K. H. Pang, Ngai Wong. 1-4 [doi]
- Design challenges for analog & mixed signal designsJeong-Tyng Li. 1-2 [doi]
- Ultrasonic telemetry and neural stimulator with FSK-PWM signalingYe-Sing Luo, Jiun-Ru Wang, Wei-Jen Huang, Je-Yu Tsai, I.-Chin Wu, Yi-Fang Liao, Wan-Ting Tseng, Chen-Tung Yen, Pai-Chi Li, Shen-Iuan Liu. 1-4 [doi]
- Efficient techniques for canceling transceiver noiseEric Chang, Frankie Liu, Philip Amberg, Jon K. Lexau, Ron Ho. 1-4 [doi]
- Multimode multiband power amplifier optimization for mobile applicationsJames P. Young, Nick Cheng. 1-3 [doi]
- Aging-aware statistical soft-error-rate analysis for nano-scaled CMOS designsCosette Y. H. Lin, Ryan H.-M. Huang, Charles H.-P. Wen, Austin C.-C. Chang. 1-4 [doi]
- MVSE: A Multi-core Video decoder System level analytics EngineDing-Yun Chen, Chi-Cheng Ju, Chen-Tsai Ho, Chung-Hung Tsai. 1-4 [doi]
- Graph-based optimal reactant minimization for sample preparation on digital microfluidic biochipsTing Wei Chiang, Chia-Hung Liu, Juinn-Dar Huang. 1-4 [doi]
- CMOS reliability: From discrete device degradation to circuit agingTanya Nigam. 1 [doi]
- A view scalable multi-view video decoder systemJui-Sheng Lee, Yuan-Hsiang Miao, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo. 1-4 [doi]
- Improve speed path identification with suspect path expressionsJiun-Lang Huang, Kun-Han Tsai, Yu-Ping Liu, Ruifeng Guo, Manish Sharma, Wu-Tung Cheng. 1-4 [doi]
- Worst-case IR-drop monitoring with 1GHz sampling rateChen-Hsiang Hsu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou. 1-4 [doi]
- M2M: Challenges and opportunitiesVida Ilderem. 1 [doi]
- The quest for a new dimension of system integrationHsien-Hsin Sean Lee. 16 [doi]
- FDSOI: A differentiator for application processors in consumer and mobile marketsLaurent Le-Pailleur. 64 [doi]