Chia-Yu Yao, Yung-Hsiang Ho. A fast-locking wide-range all-digital delay-locked loop with a starting SAR-bit prediction mechanism. In 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013. pages 1-4, IEEE, 2013. [doi]
Abstract is missing.