Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology - researchr publication

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Federico A. Altolaguirre, Ming-Dou Ker. Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology. In 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013. pages 1-4, IEEE, 2013. [doi]

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