Ren-Song Tsay - researchr alias

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Viewing Publication 1 - 57 from 57

2023

A Secure and Reliable Private Key Recovery MethodWei-Hsin Chang, Ren-Song Tsay. icce-tw 2023: 535-536 [doi]

Ureka: A Decentralized and Secure System for Managing Personal IoT DevicesYi-Chun Yang, Ren-Song Tsay. icce-tw 2023: 141-142 [doi]

A Decentralized Solution for Secure Management of IoT Access RightsYi-Chun Yang, Ren-Song Tsay. icr2 2023: 213-224 [doi]

2022

An Adaptive High-Performance Quantization Approach for Resource-Constrained CNN InferenceHsu-Hsun Chin, Ren-Song Tsay, Hsin-I Wu. aicas 2022: 336-339 [doi]

An Embedded CNN Design for Edge Devices Based on Logarithmic ComputingChong-Yin Lu, Ren-Song Tsay, Weyshin Chang. vlsi-dat 2022: 1-4 [doi]

2020

A Heuristic Region-based Concurrency Bug Testing ApproachKuo-Cheng Chin, Ren-Song Tsay, Hsin-I Wu. ispa 2020: 1126-1135 [doi]

Designing A Compact Convolutional Neural Network Processor on Embedded FPGAsYin-Chun Ling, Hsu-Hsun Chin, Hsin-I Wu, Ren-Song Tsay. gcaiot 2020: 1-7 [doi]

An Optimal Slack-Based Course Scheduling Algorithm for Personalised Study PlansAsheen Lateilla Richards, Ren-Song Tsay. iceit 2020: 1-7 [doi]

A Pipeline-Based Scheduler for Optimizing Latency of Convolution Neural Network Inference over Heterogeneous Multicore SystemsHsin-I Wu, Da-Yi Guo, Hsu-Hsun Chin, Ren-Song Tsay. aicas 2020: 46-49 [doi]

VIRA: a virtualization assisted deterministic system-level simulationsHsin-I Wu, Ren-Song Tsay, Hsu-Hsun Chin. SAC 2020: 596-598 [doi]

CORONA: A k-COnnected RObust Interconnection Network Generation AlgorithmHsin-I Wu, Ren-Song Tsay, Fong-Yuan Chang. vlsi-dat 2020: 1-4 [doi]

A Virtualization-Assisted Full-System Simulation Approach for the Verification of System Intercomponent InteractionsHsin-I Wu, Da-Yi Guo, Ren-Song Tsay. tcad, 39(12):5211-5224, 2020. [doi]

2018

A highly efficient full-system virtual prototype based on virtualization-assisted approachHsin-I Wu, Chi-Kang Chen, Tsung-ying Lu, Ren-Song Tsay. date 2018: 285-288 [doi]

2016

2015

2014

An activity-sensitive contention delay model for highly efficient deterministic full-system simulationsShu-Yung Chen, Chien-Hao Chen, Ren-Song Tsay. date 2014: 1-6 [doi]

2013

A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rulesFong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen. aspdac 2013: 175-180 [doi]

MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer RulesFong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen. tcad, 32(10):1557-1568, 2013. [doi]

A basic-block power annotation approach for fast and accurate embedded software power estimationChien-Min Lee, Chi-Kang Chen, Ren-Song Tsay. vlsi 2013: 118-123 [doi]

A Cycle Count Accurate TLM bus modeling approachMao Lin Li, Chen Kang Lo, Li-Chun Chen, Jen-Chieh Yeh, Ren-Song Tsay. vlsi-dat 2013: 1-4 [doi]

A fast and accurate instruction-oriented processor simulation approachPei-Chia Patty Lin, Evason Du, Ren-Song Tsay. vlsi-dat 2013: 1-5 [doi]

Automatic generation of high-speed accurate TLM models for out-of-order pipelined busChen Kang Lo, Mao Lin Li, Li-Chun Chen, Yi-Shan Lu, Ren-Song Tsay, Hsu-Yao Huang, Jen-Chieh Yeh. tecs, 13(1s):37, 2013. [doi]

A distributed timing synchronization technique for parallel multi-core instruction-set simulationMeng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay. tecs, 12(1s):54, 2013. [doi]

A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulationsFan-Wei Yu, Bo-Han Zeng, Yu-Hung Huang, Hsin-I. Wu, Che-Rung Lee, Ren-Song Tsay. date 2013: 643-648 [doi]

An efficient hybrid synchronization technique for scalable multi-core instruction set simulationsBo-Han Zeng, Ren-Song Tsay, Ting-Chi Wang. aspdac 2013: 588-593 [doi]

2012

A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulationYu-Hung Huang, Yi-Shan Lu, Hsin-I. Wu, Ren-Song Tsay. dac 2012: 127-132 [doi]

An Extended SystemC Framework for Efficient HW/SW Co-SimulationMeng-Huan Wu, Peng-Chih Wang, Cheng-Yang Fu, Ren-Song Tsay. todaes, 17(2):11, 2012. [doi]

2011

Cut-demand based routing resource allocation and consolidation for routability enhancementFong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak. aspdac 2011: 533-538 [doi]

Real-Time Tone-Mapping Processor with Integrated Photographic and Gradient Compression using 0.13 μm Technology on an Arm Soc PlatformChing-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, Ren-Song Tsay, Cyuan-Jhe Wu. vlsisp, 64(1):93-107, 2011. [doi]

A shared-variable-based synchronization approach to efficient cache coherence simulation for multi-core systemsCheng-Yang Fu, Meng-Huan Wu, Ren-Song Tsay. date 2011: 347-352 [doi]

Cycle-count-accurate processor modeling for fast and accurate system-level simulationChen Kang Lo, Li-Chun Chen, Meng-Huan Wu, Ren-Song Tsay. date 2011: 341-346 [doi]

From academic ideas to practical physical design toolsRen-Song Tsay. ispd 2011: 9-12 [doi]

DOM: A Data-dependency-Oriented Modeling approach for efficient simulation of OS preemptive schedulingPeng-Chih Wang, Meng-Huan Wu, Ren-Song Tsay. date 2011: 335-340 [doi]

A high-parallelism distributed scheduling mechanism for multi-core instruction-set simulationMeng-Huan Wu, Peng-Chih Wang, Cheng-Yang Fu, Ren-Song Tsay. dac 2011: 339-344 [doi]

2010

Source-level timing annotation for fast and accurate TLM computation model generationKai-Li Lin, Chen Kang Lo, Ren-Song Tsay. aspdac 2010: 235-240 [doi]

Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulationMeng-Huan Wu, Wen-Chuan Lee, Chen-Yu Chuang, Ren-Song Tsay. date 2010: 1177-1182 [doi]

2009

2008

2007

An Entrepreneurship Emulation PlatformRen-Song Tsay. mse 2007: 63-64 [doi]

1993

An exact zero-skew clock routing algorithmRen-Song Tsay. tcad, 12(2):242-249, 1993. [doi]

1992

Clock tree regenerationJan-Ming Ho, Ren-Song Tsay. glvlsi 1992: 198-203 [doi]

Performance-Driven System Partitioning on Multi-Chip ModulesMinshine Shih, Ernest S. Kuh, Ren-Song Tsay. dac 1992: 53-56 [doi]

1991

Exact Zero SkewRen-Song Tsay. iccad 1991: 336-339

An Analytic Net Weighting Approach for Performance Optimization in Circuit PlacementRen-Song Tsay, Jürgen Koehl. dac 1991: 620-625 [doi]

A new method for floor planning using topological constraint reductionGopalakrishnan Vijayan, Ren-Song Tsay. tcad, 10(12):1494-1501, 1991. [doi]

1990

Floorplanning by Topological Constraint ReductionGopalakrishnan Vijayan, Ren-Song Tsay. iccad 1990: 106-109

1989

A new approach to sea-of-gates global routingTai-Ming Parng, Ren-Song Tsay. iccad 1989: 52-55 [doi]

1988

Proud: A Fast Sea-of-Gates Placement AlgorithmRen-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu. dac 1988: 318-323 [doi]

PROUD: a sea-of-gates placement algorithmRen-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu. dt, 5(6):44-56, 1988. [doi]

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