Table of Contents

• Technology Challenges to IC Industry for Next DecadeK. Lawrence Loh. 1 [doi]
• Bio-Chips for Fast Medial Tests NetworksChen-Yi Lee. 1 [doi]
• SlewFTA: Functional Timing Analysis Considering Slew PropagationZong-Hua Tsai, Aaron C.-W. Liang, Charles H.-P. Wen. 1-4 [doi]
• Hardware Root-of-Trust Design Based on on-chip PUF for AIoT ApplicationsMeng-Yi Wu. 1 [doi]
• An Embedded CNN Design for Edge Devices Based on Logarithmic ComputingChong-Yin Lu, Ren-Song Tsay, Weyshin Chang. 1-4 [doi]
• Improving IJTAG Test Efficiency and SecuritySying-Jyan Wang, Yen-Chang Shih, Katherine Shu-Min Li, Chen-Yeh Lin, Song-Kong Chong. 1-4 [doi]
• Hardware-Friendly Progressive Pruning Framework for CNN Model Compression using Universal Pattern SetsWei-Cheng Chou, Cheng-Wei Huang, Juinn-Dar Huang. 1-4 [doi]
• Semiconductor Evolution for Chip and System Design- From 2D Scaling to 3D Heterogeneous IntegrationL. C. Lu. 1 [doi]
• Circuit Routing Using Monte Carlo Tree Search and Deep Reinforcement LearningYoubiao He, Hebi Li, Jin Tian, Forrest Sheng Bao. 1-5 [doi]
• Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation StrategyKang-Yi Fan, Jyun-Hua Chen, Chien-Nan Liu, Juinn-Dar Huang. 1-4 [doi]
• Non-Uniform Sampling Data Converters: A Journey to Uncharted Circuits and SystemsShuo-Wei Chen. 1 [doi]
• Challenges and Opportunities in Building Secure IoT PlatformsTung-Yi Chan. 1 [doi]
• Bridging the Physical and Digital Worlds in Data-Driven SystemsBoris Murmann. 1 [doi]
• A64FX: 52 Core Processor Designed for the Supercomputer FugakTakekazu Tabata. 1 [doi]
• Variational Channel Distribution Pruning and Mixed-Precision Quantization for Neural Network Model CompressionWan-Ting Chang, Chih-Hung Kuo, Li-Chun Fang. 1-3 [doi]
• 28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing SystemYuji Yano, Hisashi Iwamoto, Takuma Yoshimura, Yoshihiro Nishida, Tatsuya Mori, Kiyotaka Komoku, Hidekuni Takao, Kazutami Arimoto. 1-4 [doi]
• A 0.116pJ/bit Latch-Based True Random Number Generator with Static Inverter Selection and Noise EnhancementXingyu Wang, Ruilin Zhang, Yuxin Wang, Kunyang Liu, Xuanzhen Wang, Hirofumi Shinohara. 1-4 [doi]
• Substrate Signal Routing Solution Exploration for High-Density Packages with Machine LearningYeu-Haw Yeh, Simon Yi-Hung Chen, Hung-Ming Chen, Deng-Yao Tu, Guan-Qi Fang, Yun-Chih Kuo, Po-Yang Chen. 1-4 [doi]
• ML-based Fast On-Chip Transient Thermal Simulation for Heterogeneous 2.5D/3D IC DesignsAkhilesh Kumar, Norman Chang, David Geb, Haiyang He, Stephen H. Pan, Jimin Wen, Saeed Asgari, Mehdi Abarham, Chris Ortiz. 1-8 [doi]
• Fast and efficient ResNN and Genetic optimization for PVT aware performance enhancement in digital circuitsKushagra Agarwal, Aryamaan Jain, Deepthi Amuru, Zia Abbas. 1-4 [doi]
• Product level design considerations and solutions for RF GaN applicationsChih-Wen Huang. 1-2 [doi]
• Configurable Deep Learning Accelerator with Bitwise-accurate Training and VerificationShien-Chun Luo, Kuo-Chiang Chang, Po-Wei Chen, Zhao-Hong Chen. 1-4 [doi]
• Practical Considerations of In-Memory Computing in the Deep Learning Accelerator ApplicationsJen-Wei Liang. 1 [doi]
• Single Chip of Electrostatic Discharge Detector for IC Manufacturing Field ControlI-Hsuan Wu, Ming-Dou Ker. 1-4 [doi]
• The Applications of SiC Power Devices in Renewable Energy and EVKung-Yen Lee. 1 [doi]
• Efficient Segment-wise Pruning for DCNN Inference AcceleratorsChe-Chang Yang, Yung-Tai Shih, Chun-Chen Chen, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen, Juin-Ming Lu. 1-4 [doi]
• Distributed Sorting Architecture on Multiple FPGAYi-Da Hsin, Yen-Shi Kuo, Bo-Cheng Lai. 1-4 [doi]
• Low-power Continuous-time Delta-sigma ADCsYoungcheol Chae. 1 [doi]
• Robust CNFET Circuit Sizing OptimizationZahra Heshmatpour, Lihong Zhang, Howard M. Heys. 1-4 [doi]
• Introduction of Noise-Shaping SAR ADCsYun-Shiang Shu. 1 [doi]
• A Silicon Photonics Technology for 400 Gbit/s ApplicationsMing-Wei Lin. 1 [doi]
• A Thermal Quorum Sensing Scheme for Enhancement of Integrated-Circuit Reliability and LifetimeHong-Hao Wang, Po-Yao Chuang, Cheng-Wen Wu. 1-4 [doi]
• An Injection-Locked Clock Multiplier With Injection Strength CalibrationYen-Min Tseng, Yu-Chi Yen, Shen-Iuan Liu. 1-4 [doi]
• 2.5D & 3DIC Advanced Packaging: An EDA PerspectiveVincent Hsu. 1-2 [doi]
• Composite Fault Diagnosis of Rotating Machinery With Collaborative LearningM. P. Pavan Kumar, Cheng-Jyun Tang, Kun-Chih Jimmy Chen. 1-4 [doi]
• A 5-GHz Sub-Sampling Phase-Locked Loop With Pulse-Width to Current ConversionShao-Yu Shu, Chun-Hung Lin, Ching-Yuan Yang. 1-4 [doi]
• Wide Band Gap Devices for Power SystemTaiKang Shing. 1-2 [doi]
• Silicon Photonics for Scaling the Cloud and Enabling AIYoojin Ban. 1 [doi]
• An Adaptive Digital PLL Based on BBPFD Transition ProbabilityZhi-Heng Kang, Yu-Chi Yen, Guan-Yu Su, Shen-Iuan Liu. 1-4 [doi]
• How FPGA can contribute to HPC ?Taisuke Boku. 1 [doi]
• AIoT Security - from the Perspective of a MicrocontrollerMing-Nan Cheng. 1 [doi]
• The Supercomputer "Fugaku"Mitsuhisa Sato. 1 [doi]
• An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN ApplicationsChi Liu, Shao-Tzu Li, Tong-Lin Pan, Cheng-En Ni, Yun Sung, Chia-Lin Hu, Kang-Yu Chang, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou. 1-4 [doi]
• Circuits and Architectures for Next-generation Attentive & Intelligent SystemsMassimo Alioto. 1 [doi]
• A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor ArrayPai-Yu Tan, Chih-Hsuan Tung, Cheng-Wen Wu, Mincent Lee, Gordon Liao. 1-4 [doi]
• A Body Channel Communication Transceiver with a 16x Oversampling CDR and Convolutional CodesChing-Che Chung, Yi-Ting Tsai. 1-4 [doi]
• An FPGA-Based High-Frequency Trading System for 10 Gigabit Ethernet with a Latency of 433 nsYi-Chieh Kao, Hung-An Chen, Hsi-Pin Ma. 1-4 [doi]
• An Asynchronous Zero-Crossing-Based Incremental Delta-Sigma ConverterYen-Po Lai, Hao-Hsuan Chang, Tai-Cheng Lee. 1-4 [doi]
• Design of ultra-high-speed Transmitters Beyond 100Gb/s in CMOS TechnologyPen-Jui Peng. 1 [doi]