Chi Liu, Shao-Tzu Li, Tong-Lin Pan, Cheng-En Ni, Yun Sung, Chia-Lin Hu, Kang-Yu Chang, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou. An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. In 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022, Hsinchu, Taiwan, April 18-21, 2022. pages 1-4, IEEE, 2022. [doi]
Abstract is missing.