Abstract is missing.
- MATIC: Learning around errors for efficient low-voltage neural network acceleratorsSung Kim, Patrick Howe, Thierry Moreau, Armin Alaghi, Luis Ceze, Visvesh Sathe. 1-6 [doi]
- Maximizing system performance by balancing computation loads in LSTM acceleratorsJunki Park, Jaeha Kung, Wooseok Yi, Jae-Joon Kim. 7-12 [doi]
- moDNN: Memory optimal DNN training on GPUsXiaoming Chen, Danny Z. Chen, Xiaobo Sharon Hu. 13-18 [doi]
- HyperPower: Power- and memory-constrained hyper-parameter optimization for neural networksDimitrios Stamoulis, Ermao Cai, Da-Cheng Juan, Diana Marculescu. 19-24 [doi]
- Sensei: An area-reduction advisor for FPGA high-level synthesisHsuan Hsiao, Jason Helge Anderson. 25-30 [doi]
- A fast and effective lookahead and fractional search based scheduling algorithm for high-level synthesisShantanu Dutt, Ouwen Shi. 31-36 [doi]
- High-level synthesis of software-customizable floating-point coresSamridhi Bansal, Hsuan Hsiao, Tomasz S. Czajkowski, Jason Helge Anderson. 37-42 [doi]
- Efficient verification of multi-property designs (The benefit of wrong assumptions)Eugene Goldberg, Matthias Güdemann, Daniel Kroening, Rajdeep Mukherjee. 43-48 [doi]
- Combining PDR and reverse PDR for hardware model checkingTobias Seufert, Christoph Scholl. 49-54 [doi]
- Symbolic quick error detection using symbolic initial state for pre-silicon verificationMohammad Rahmani Fadiheh, Joakim Urdahl, Srinivas Shashank Nuthakki, Subhasish Mitra, Clark Barrett, Dominik Stoffel, Wolfgang Kunz. 55-60 [doi]
- Verification of tree-based hierarchical read-copy update in the Linux kernelLihao Liang, Paul E. McKenney, Daniel Kroening, Tom Melham. 61-66 [doi]
- HVSM: Hardware-variability aware streaming processors' management policy in GPUsJingweijia Tan, Kaige Yan. 67-72 [doi]
- Throughput optimization and resource allocation on GPUs under multi-application executionSrinivasa Reddy Punyala, Theodoros Marinakis, Arash Komaee, Iraklis Anagnostopoulos. 73-78 [doi]
- Set variation-aware shared LLC management for CPU-GPU heterogeneous architectureZhaoying Li, Lei Ju, Hongjun Dai, Xin Li, Mengying Zhao, Zhiping Jia. 79-84 [doi]
- Cyclic locking and memristor-based obfuscation against CycSAT and inside foundry attacksAmin Rezaei, Yuanqi Shen, Shuyu Kong, Jie Gu, Hai Zhou. 85-90 [doi]
- TimingCamouflage: Improving circuit security against counterfeiting by unconventional timingGrace Li Zhang, Bing Li, Bei Yu, David Z. Pan, Ulf Schlichtmann. 91-96 [doi]
- Advancing hardware security using polymorphic and stochastic spin-hall effect devicesSatwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja. 97-102 [doi]
- Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworksManu Komalan, Oh Hyung Rock, Matthias Hartmann, Sushil Sakhare, Christian Tenllado, José Ignacio Gómez, Gouri Sankar Kar, Arnaud Furnemont, Francky Catthoor, Sophiane Senni, David Novo, Abdoulaye Gamatié, Lionel Torres. 103-108 [doi]
- Exploring the opportunity of implementing neuromorphic computing systems with spintronic devicesBonan Yan, Fan Chen, Yaojun Zhang, Chang Song, Hai Li, Yiran Chen. 109-112 [doi]
- Spintronic normally-off heterogeneous system-on-chip designAnteneh Gebregiorgis, Rajendra Bishnoi, Mehdi Baradaran Tahoori. 113-118 [doi]
- Magnetic skyrmions for future potential memory and logic applications: Alternative information carriersWang Kang, Xing Chen, Daoqian Zhu, Sai Li, Yangqi Huang, Youguang Zhang, Weisheng Zhao. 119-124 [doi]
- Novel application of spintronics in computing, sensing, storage and cybersecuritySeyedhamidreza Motaman, Mohammad Nasim Imtiaz Khan, Swaroop Ghosh. 125-130 [doi]
- Large scale, high density integration of all spin logicQi An, Sébastien Le Beux, Ian O'Connor, Jacques-Olivier Klein. 131-136 [doi]
- Programming quantum computers using design automationMathias Soeken, Thomas Häner, Martin Roetteler. 137-146 [doi]
- Energy proportionality in near-threshold computing servers and cloud data centers: Consolidating or Not?Ali Pahlevan, Yasir Mahmood Qureshi, Marina Zapater, Andrea Bartolini, Davide Rossi, Luca Benini, David Atienza. 147-152 [doi]
- Lookup table allocation for approximate computing with memory under quality constraintsYe Tian, Qian Zhang, Ting Wang, Qiang Xu. 153-158 [doi]
- Accelerating biophysical neural network simulation with region of interest based approximationYun Long, Xueyuan She, Saibal Mukhopadhyay. 159-164 [doi]
- DS-DSE: Domain-specific design space exploration for streaming applicationsJinghan Zhang, Hamed Tabkhi, Gunar Schirner. 165-170 [doi]
- Variation-aware task allocation and scheduling for improving reliability of real-time MPSoCsJunlong Zhou, Tongquan Wei, Mingsong Chen, Xiaobo Sharon Hu, Yue Ma, Gongxuan Zhang, Jianming Yan. 171-176 [doi]
- Topology-aware virtual resource management for heterogeneous multicore systemsJianmin Qian, Jian Li, Ruhui Ma. 177-182 [doi]
- Structure optimizations of neuromorphic computing architectures for deep neural networkHeechun Park, Taewhan Kim. 183-188 [doi]
- CCR: A concise convolution rule for sparse neural network acceleratorsJiajun Li, Guihai Yan, Wenyan Lu, Shuhao Jiang, Shijun Gong, Jingya Wu, Xiao-Wei Li. 189-194 [doi]
- Gradient importance sampling: An efficient statistical extraction methodology of high-sigma SRAM dynamic characteristicsThomas Haine, Johan Segers, Denis Flandre, David Bol. 195-200 [doi]
- Degradation analysis of high performance 14nm FinFET SRAMDaniel Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor. 201-206 [doi]
- Investigating power outage effects on reliability of solid-state drivesSaba Ahmadian, Farhad Taheri, Mehrshad Lotfi, Maryam Karimi, Hossein Asadi. 207-212 [doi]
- Workload-aware harmonic partitioned scheduling for probabilistic real-time systemsJiankang Ren, Ran Bi, Xiaoyan Su, Qian Liu, Guowei Wu, Guozhen Tan. 213-218 [doi]
- Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCsLeandro Soares Indrusiak, Alan Burns, Borislav Nikolic. 219-224 [doi]
- A design-space exploration for allocating security tasks in multicore real-time systemsMonowar Hasan, Sibin Mohan, Rodolfo Pellizzoni, Rakesh B. Bobba. 225-230 [doi]
- Design and analysis of semaphore precedence constraints: A model-based approach for deterministic communicationsThanh-Dat Nguyen, Yassine Ouhammou, Emmanuel Grolleau, Julien Forget, Claire Pagetti, Pascal Richard. 231-236 [doi]
- ReCom: An efficient resistive accelerator for compressed deep neural networksHouxiang Ji, Linghao Song, Li Jiang, Hai Helen Li, Yiran Chen. 237-240 [doi]
- SparseNN: An energy-efficient neural network accelerator exploiting input and output sparsityJingyang Zhu, Jingbo Jiang, Xizi Chen, Chi-Ying Tsui. 241-244 [doi]
- ACCLIB: Accelerators as librariesJacob R. Stevens, Yue Du, Vivek Kozhikkott, Anand Raghunathan. 245-248 [doi]
- HPXA: A highly parallel XML parserIsaar Ahmad, Sanjog Patil, Smruti R. Sarangi. 249-252 [doi]
- QoR-aware power capping for approximate big data processingSeyed Morteza Nabavinejad, Xin Zhan, Reza Azimi, Maziar Goudarzi, Sherief Reda. 253-256 [doi]
- Exact multi-objective design space exploration using ASPmTKai Neubauer, Philipp Wanko, Torsten Schaub, Christian Haubelt. 257-260 [doi]
- HIPE: HMC instruction predication extension applied on database processingDiego G. Tome, Paulo C. Santos, Luigi Carro, Eduardo Cunha de Almeida, Marco Antonio Zanata Alves. 261-264 [doi]
- Parametric failure modeling and yield analysis for STT-MRAMSarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori. 265-268 [doi]
- One-way shared memoryMartin Schoeberl. 269-272 [doi]
- An efficient resource-optimized learning prefetcher for solid state drivesRui Xu, Xi Jin, Linfeng Tao, Shuaizhi Guo, Zikun Xiang, Teng Tian. 273-276 [doi]
- Bridging discrete and continuous time models with atomsGeorge Ungureanu, José Edil G. de Medeiros, Ingo Sander. 277-280 [doi]
- OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulationRobert Lajos Bücs, Maximilian Fricke, Rainer Leupers, Gerd Ascheid, Stephan Tobies, Andreas Hoffmann 0002. 281-284 [doi]
- A highly efficient full-system virtual prototype based on virtualization-assisted approachHsin-I Wu, Chi-Kang Chen, Tsung-ying Lu, Ren-Song Tsay. 285-288 [doi]
- Industrial evaluation of transition fault testing for cost effective offline adaptive voltage scalingMahroo Zandrahimi, Philippe Debaud, Armand Castillejo, Zaid Al-Ars. 289-292 [doi]
- An analysis on retention error behavior and power consumption of recent DDR4 DRAMsDeepak M. Mathew, Martin Schultheis, Carl Christian Rheinländer, Chirag Sudarshan, Christian Weis, Norbert Wehn, Matthias Jung 0001. 293-296 [doi]
- A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devicesMarcello Dalpasso, Davide Bertozzi, Michele Favalli. 297-300 [doi]
- ATPG power guards: On limiting the test power below thresholdRohini Gulve, Virendra Singh. 301-304 [doi]
- Improving circuit size upper bounds using SAT-solversAlexander S. Kulikov. 305-308 [doi]
- Practical exact synthesisMathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amarù, Robert K. Brayton, Giovanni De Micheli. 309-314 [doi]
- SAT-based redundancy removalKrishanu Debnath, Rajeev Murgai, Mayank Jain, Janet Olson. 315-318 [doi]
- Approximate computing for biometrie security systems: A case study on iris scanningSoheil Hashemi, Hokchhay Tann, Francesco Buttafuoco, Sherief Reda. 319-324 [doi]
- Flash read disturb management using adaptive cell bit-density with in-place reprogrammingTai-Chou Wu, Yu-ping Ma, Li-Pin Chang. 325-330 [doi]
- HTF-MPR: A heterogeneous TensorFlow mapper targeting performance using genetic algorithms and gradient boosting regressorsAhmad Albaqsami, Maryam S. Hosseini, Nader Bagherzadeh. 331-336 [doi]
- CAMP: Accurate modeling of core and memory locality for proxy generation of big-data applicationsReena Panda, Xinnian Zheng, Andreas Gerstlauer, Lizy Kurian John. 337-342 [doi]
- SmartShuttle: Optimizing off-chip memory accesses for deep learning acceleratorsJiajun Li, Guihai Yan, Wenyan Lu, Shuhao Jiang, Shijun Gong, Jingya Wu, Xiaowei Li. 343-348 [doi]
- Port call path sensitive conflict analysis for instance-aware parallel SystemC simulationTim Schmidt, Zhongqi Cheng, Rainer Dömer. 349-354 [doi]
- Trident: A comprehensive timing error resilient technique against choke points at NTCAatreyi Bal, Sanghamitra Roy, Koushik Chakraborty. 355-360 [doi]
- Bayesian theory based switching probability calculation method of critical timing path for on-chip timing slack monitoringByung-Su Kim, Joon-Sung Yang. 361-366 [doi]
- Performance based tuning of an inductive integrated voltage regulator driving a digital core against process and passive variationsVenakata Chaitanya Krishna Chekuri, Monodeep Kar, Arvind Singh, Saibal Mukhopadhyay. 367-372 [doi]
- Pre-assembly testing of interconnects in embedded multi-die interconnect bridge (EMIB) diesSudipta Mondal, Krishnendu Chakrabarty. 373-378 [doi]
- On the reuse of timing resilient architecture for testing path delay faults in critical pathsFelipe A. Kuentzer, Leonardo Rezende Juracy, Alexandre M. Amory. 379-384 [doi]
- Characterization of possibly detected faults by accurately computing their detection probabilityJan Burchard, Dominik Erb, Bernd Becker 0001. 385-390 [doi]
- Ultra-low energy circuit building blocks for security technologiesSanu Mathew, Sudhir Satpathy, Vikram Suresh, Ram Krishnamurthy. 391-394 [doi]
- Embedded randomness and data dependencies design paradigm: Advantages and challengesItamar Levi, Yehuda Rudin, Alexander Fish, Osnat Keren. 395-400 [doi]
- Exploiting on-chip power management for side-channel securityArvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay. 401-406 [doi]
- Rescuing memristor-based computing with non-linear resistance levelsJilan Lin, Lixue Xia, Zhenhua Zhu, Hanbo Sun, Yi Cai, Hui Gao, Ming Cheng, Xiaoming Chen, Yu Wang, Huazhong Yang. 407-412 [doi]
- PX-CGRA: Polymorphic approximate coarse-grained reconfigurable architectureOmid Akbari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, Muhammad Shafique. 413-418 [doi]
- Multi-precision convolutional neural networks on heterogeneous hardwareSam Amiri, Mohammad Hosseinabady, Simon McIntosh-Smith, José Núñez-Yáñez. 419-424 [doi]
- Logic synthesis and defect tolerance for memristive crossbar arraysOnur Tunali, Mustafa Altun. 425-430 [doi]
- SOH-aware active cell balancing strategy for high power battery packsAlma Pröbstl, Sangyoung Park, Swaminathan Narayanaswamy, Sebastian Steinhorst, Samarjit Chakraborty. 431-436 [doi]
- GIS-based optimal photovoltaic panel floorplanning for residential installationsSara Vinco, Lorenzo Bottaccioli, Edoardo Patti, Andrea Acquaviva, Enrico Macii, Massimo Poncino. 437-442 [doi]
- Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUsJorg Fickenscher, Jens Schlumberger, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa. 443-448 [doi]
- WALL: A writeback-aware LLC management for PCM-based main memory systemsBahareh Pourshirazi, Majed Valad Beigi, Zhichun Zhu, Gokhan Memik. 449-454 [doi]
- Design and integration of hierarchical-placement multi-level caches for real-time systemsPedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla. 455-460 [doi]
- LARS: Logically adaptable retention time STT-RAM cache for embedded systemsKyle Kuan, Tosiron Adegbija. 461-466 [doi]
- Cost-efficient design for modeling attacks resistant PUFsMohd Syafiq Mispan, Haibo Su, Mark Zwolinski, Basel Halak. 467-472 [doi]
- Device attestation: Past, present, and futureOrlando Arias, Fahim Rahman, Mark Tehranipoor, Yier Jin. 473-478 [doi]
- A reconfigurable scan network based IC identification for embedded devicesOmid Aramoon, Xi Chen, Gang Qu. 479-484 [doi]
- Early detection of system-level anomalous behaviour using hardware performance countersLai Leng Woo, Mark Zwolinski, Basel Halak. 485-490 [doi]
- Compact modeling of carbon nanotube thin film transistors for flexible circuit designLeilai Shao, Tsung-Ching Huang, Ting Lei, Zhenan Bao, Raymond G. Beausoleil, Kwang-Ting Cheng. 491-496 [doi]
- A high-speed design methodology for inductive coupling links in 3D-ICsBenjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak. 497-502 [doi]
- An exact method for design exploration of quantum-dot cellular automataMarcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler. 503-508 [doi]
- Accurate margin calculation for single flux quantum logic cellsSoheil Nazar Shahsavani, Bo Zhang, Massoud Pedram. 509-514 [doi]
- Improving reliability for real-time systems through dynamic recoveryYue Ma, Thidapat Chantem, Robert P. Dick, Xiaobo Sharon Hu. 515-520 [doi]
- Optimal metastability-containing sorting networksJohannes Bund, Christoph Lenzen, Moti Medina. 521-526 [doi]
- MAUI: Making aging useful, intentionallyKai-Chiang Wu, Tien-Hung Tseng, Shou-Chun Li. 527-532 [doi]
- EXPERT: Effective and flexible error protection by redundant multithreadingHwisoo So, Moslem Didehban, Yohan Ko, Aviral Shrivastava, Kyoungwoo Lee. 533-538 [doi]
- HePREM: Enabling predictable GPU execution on heterogeneous SoCBjörn Forsberg, Luca Benini, Andrea Marongiu. 539-544 [doi]
- Circuit carving: A methodology for the design of approximate hardwareIlaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi. 545-550 [doi]
- ICNN: An iterative implementation of convolutional neural networks to enable energy and computational complexity aware dynamic approximationKatayoun Neshatpour, Farnaz Behnia, Houman Homayoun, Avesta Sasan. 551-556 [doi]
- Task scheduling for many-cores with S-NUCA cachesAnuj Pathania, Jörg Henkel. 557-562 [doi]
- KVSSD: Close integration of LSM trees and flash translation layer for write-efficient KV storeSung-Ming Wu, Kai-Hsiang Lin, Li-Pin Chang. 563-568 [doi]
- In-growth test for monolithic 3D integrated SRAMPu Pang, Yixun Zhang, Tianjian Li, Sung Kyu Lim, Quan Chen, Xiaoyao Liang, Li Jiang. 569-572 [doi]
- A co-design methodology for scalable quantum processors and their classical electronic interfaceJeroen P. G. van Dijk, Andrei Vladimirescu, Masoud Babaie, Edoardo Charbon, Fabio Sebastiano. 573-576 [doi]
- Approximate quaternary addition with the fast carry chains of FPGAsSina Boroumand, Hadi Parandeh-Afshar, Philip Brisk. 577-580 [doi]
- NN compactor: Minimizing memory and logic resources for small neural networksSeongmin Hong, Inho Lee, Yongjun Park. 581-584 [doi]
- Improving fast charging efficiency of reconfigurable battery packsAlexander Lamprecht, Swaminathan Narayanaswamy, Sebastian Steinhorst. 585-588 [doi]
- Cloud-assisted control of ground vehicles using adaptive computation offloading techniquesArun Adiththan, S. Ramesh, Soheil Samii. 589-592 [doi]
- FusionCache: Using LLC tags for DRAM cacheEvangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis. 593-596 [doi]
- Improved synthesis of Clifford+T quantum functionalityPhilipp Niemann, Robert Wille, Rolf Drechsler. 597-600 [doi]
- Energy-efficient channel alignment of DWDM silicon photonic transceiversYuyang Wang, M. Ashkan Seyedi, Rui Wu, Jared Hulme, Marco Fiorentino, Raymond G. Beausoleil, Kwang-Ting Cheng. 601-604 [doi]
- A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETsShubham Rai, Ansh Rupani, Dennis Walter, Michael Raitza, Andre Heinzig, Tim Baldauf, Jens Trommer, Christian Mayr, Walter M. Weber, Akash Kumar 0001. 605-608 [doi]
- ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniquesDaniel Mueller-Gritschneder, Martin Dittrich, Josef Weinzierl, Eric Cheng, Subhasish Mitra, Ulf Schlichtmann. 609-612 [doi]
- Precise evaluation of the fault sensitivity of OoO superscalar processorsRafael Billig Tonetto, Gabriel L. Nazar, Antonio Carlos Schneider Beck. 613-616 [doi]
- StreamFTL: Stream-level address translation scheme for memory constrained flash storageHyukjoong Kim, Kyuhwa Han, Dongkun Shin. 617-620 [doi]
- Online concurrent workload classification for multi-core energy managementBasireddy Karunakar Reddy, Geoff V. Merrett, Bashir M. Al-Hashimi, Amit Kumar Singh. 621-624 [doi]
- AIM: Fast and energy-efficient AES in-memory implementation for emerging non-volatile main memoryMimi Xie, Shuangchen Li, Alvin Oliver Giova, Jingtong Hu, Yuangang Wang, Yuan Xie 0001. 625-628 [doi]
- SAT-based bit-flipping attack on logic encryptionsYuanqi Shen, Amin Rezaei, Hai Zhou. 629-632 [doi]
- AMS verification methodology regarding supply modulation in RF SoCs induced by digital standard cellsFabian Speicher, Jonas Meier, Soheil Aghaie, Ralf Wunderlich, Stefan Heinen. 633-636 [doi]
- Towards high-performance polarity-controllable FETs with 2D materialsGiovanni V. Resta, Jorge Romero Gonzalez, Yashwanth Balaji, Tarun Agarwal, Dennis Lin, Francky Catthoor, Iuliana P. Radu, Giovanni De Micheli, Pierre-Emmanuel Gaillardon. 637-641 [doi]
- Dynamic skewed tree for fast memory integrity verificationSaru Vig, Guiyuan Jiang, Siew Kei Lam. 642-647 [doi]
- Earthquake - A NoC-based optimized differential cache-collision attack for MPSoCsCezar Reinbrecht, Bruno Forlin, Andreas Zankl, Johanna Sepúlveda. 648-653 [doi]
- A fast and resource efficient FPGA implementation of secret sharing for storage applicationsJakob Stangl, Thomas Lorünser, Sai Manoj Pudukotai Dinakarrao. 654-659 [doi]
- Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernelTiago Pessoa, Nuno Lourenço 0003, Ricardo Martins, Ricardo Povoa, Nuno Horta. 660-665 [doi]
- A SystemC-based Simulator for design space exploration of smart wireless systemsGabriele Miorandi, Francesco Stefanni, Federico Fraccaroli, Davide Quaglia. 666-671 [doi]
- A circuit-design-driven tool with a hybrid automation approach for SAR ADCs in IoTMing Ding, Guibin Chen, Pieter Harpe, Benjamin Busze, Yao-Hong Liu, Christian Bachmann, Kathleen Philips, Arthur H. M. van Roermund. 672-675 [doi]
- Automatic integration of cycle-accurate descriptions with continuous-time models for cyber-physical virtual platformsMichele Lora, Stefano Centomo, Davide Quaglia, Franco Fummi. 676-681 [doi]
- Stability-aware integrated routing and scheduling for control applications in Ethernet networksRouhollah Mahfouzi, Amir Aminifar, Soheil Samii, Ahmed Rezine, Petru Eles, Zebo Peng. 682-687 [doi]
- Feedback control of real-time EtherCAT networks for reliability enhancement in CPSLiying Li, Peijin Cong, Kun Cao, Junlong Zhou, Tongquan Wei, Mingsong Chen, Xiaobo Sharon Hu. 688-693 [doi]
- Cache-aware task scheduling for maximizing control performanceWanli Chang, Debayan Roy, Xiaobo Sharon Hu, Samarjit Chakraborty. 694-699 [doi]
- Three years of low-power image recognition challenge: Introduction to special sessionKent Gauen, Ryan Dailey, Yung-Hsiang Lu, Eunbyung Park, Wei Liu, Alexander C. Berg, Yiran Chen. 700-703 [doi]
- Real-time object detection towards high power efficiencyJincheng Yu, Kaiyuan Guo, Yiming Hu, Xuefei Ning, Jiantao Qiu, Huizi Mao, Song Yao, Tianqi Tang, Boxun Li, Yu Wang, Huazhong Yang. 704-708 [doi]
- A retrospective evaluation of energy-efficient object detection solutions on embedded devicesYing Wang, Zhenyu Quan, Jiajun Li, Yinhe Han, Huawei Li, Xiaowei Li. 709-714 [doi]
- Joint optimization of speed, accuracy, and energy for embedded image recognition systemsDuseok Kang, Donghyun Kang, Jintaek Kang, Sungjoo Yoo, Soonhoi Ha. 715-720 [doi]
- Theoretical and practical aspects of verification of quantum computersYehuda Naveh, Elham Kashefi, James R. Wootton, Koen Bertels. 721-730 [doi]
- Airavat: Improving energy efficiency of heterogeneous applicationsTrinayan Baruah, Yifan Sun, Shi Dong, David R. Kaeli, Norm Rubin. 731-736 [doi]
- All-digital embedded meters for on-line power estimationDaniele Jahier Pagliari, Valentino Peluso, Yukai Chen, Andrea Calimera, Enrico Macii, Massimo Poncino. 737-742 [doi]
- PowerProbe: Run-time power modeling through automatic RTL instrumentationDavide Zoni, Luca Cremona, William Fornaciari. 743-748 [doi]
- Design optimization of photovoltaic arrays on curved surfacesSangyoung Park, Samarjit Chakraborty. 749-754 [doi]
- Improvements to boolean resynthesisLuca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli. 755-760 [doi]
- Logic optimization with considering boolean relationsTung-Yuan Lee, Chia-Cheng Wu, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang. 761-766 [doi]
- Technology mapping flow for emerging reconfigurable silicon nanowire transistorsShubham Rai, Michael Raitza, Akash Kumar 0001. 767-772 [doi]
- Efficient synthesis of approximate threshold logic circuits with an error rate guaranteeYung-An Lai, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang. 773-778 [doi]
- Row-buffer hit harvesting in orchestrated last-level cache and DRAM scheduling for heterogeneous multicore systemsYang Song, Olivier Alavoine, Bill Lin. 779-784 [doi]
- AdAM: Adaptive approximation management for the non-volatile memory hierarchiesMohammad Taghi Teimoori, Muhammad Abdullah Hanif, Alireza Ejlali, Muhammad Shafique 0001. 785-790 [doi]
- A cross-layer adaptive approach for performance and power optimization in STT-MRAMNour Sayed, Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori. 791-796 [doi]
- Low-cost high-accuracy variation characterization for nanoscale IC technologies via novel learning-based techniquesZhijian Pan, Miao Li, Jian Yao, Hong Lu, Zuochang Ye, Yanfeng Li, Yan Wang. 797-802 [doi]
- Mitigation of NBTI induced performance degradation in on-chip digital LDOsLongfei Wang, S. Karen Khatamifard, Ulya R. Karpuzcu, Selçuk Köse. 803-808 [doi]
- Evaluating the impact of execution parameters on program vulnerability in GPU applicationsFritz G. Previlon, Charu Kalra, David R. Kaeli, Paolo Rech. 809-814 [doi]
- ReRAM-based accelerator for deep learningBing Li, Linghao Song, Fan Chen, Xuehai Qian, Yiran Chen, Hai Helen Li. 815-820 [doi]
- Exploiting approximate computing for deep learning accelerationChia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Viji Srinivasan, Swagath Venkataramani. 821-826 [doi]
- An overview of next-generation architectures for machine learning: Roadmap, opportunities and challenges in the IoT eraMuhammad Shafique 0001, Theocharis Theocharides, Christos-Savvas Bouganis, Muhammad Abdullah Hanif, Faiq Khalid, Rehan Hafiz, Semeen Rehman. 827-832 [doi]
- Inference of quantized neural networks on heterogeneous all-programmable devicesThomas B. Preußer, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott. 833-838 [doi]
- CHASE: Contract-based requirement engineering for cyber-physical system designPierluigi Nuzzo, Michele Lora, Yishai A. Feldman, Alberto L. Sangiovanni-Vincentelli. 839-844 [doi]
- Resilience evaluation via symbolic fault injection on intermediate codeHoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler. 845-850 [doi]
- Online analysis of debug trace data for embedded systemsNormann Decker, Boris Dreyer, Philip Gottschling, Christian Hochberger, Alexander Lange, Martin Leucker, Torben Scheffel, Simon Wegener, Alexander Weiss. 851-856 [doi]
- Testbench qualification for SystemC-AMS timed data flow modelsMuhammad Hassan, Daniel Grose, Hoang M. Le, Thilo Vörtler, Karsten Einwich, Rolf Drechsler. 857-860 [doi]
- An algebra for modeling continuous time systemsJosé Edil G. de Medeiros, George Ungureanu, Ingo Sander. 861-864 [doi]
- TTW: A Time-Triggered Wireless design for CPSRomain Jacob, Licong Zhang, Marco Zimmerling, Jan Beutel, Samarjit Chakraborty, Lothar Thiele. 865-868 [doi]
- PHYLAX: Snapshot-based profiling of real-time embedded devices via JTAG interfaceCharalambos Konstantinou, Eduardo Chielle, Michail Maniatakos. 869-872 [doi]
- Characterizing display QoS based on frame dropping for power management of interactive applications on smartphonesKuan-Ting Ho, Chung-Ta King, Bhaskar Das, Yung-Ju Chang. 873-876 [doi]
- Prediction-based fast thermoelectric generator reconfiguration for energy harvesting from vehicle radiatorsHanchen Yang, Feiyang Kang, Caiwen Ding, Ji Li, Jaemin Kim, Donkyu Baek, Shahin Nazarian, Xue Lin, Paul Bogdan, Naehyuck Chang. 877-880 [doi]
- A parameterized timing-aware flip-flop merging algorithm for clock power reductionChaochao Feng, Daheng Yue, Zhenyu Zhao, Zhuofan Liao. 881-884 [doi]
- Fast chip-package-PCB coanalysis methodology for power integrity of multi-domain high-speed memory: A case studySeungwon Kim, Ki Jin Han, Youngmin Kim, Seokhyeong Kang. 885-888 [doi]
- Approximate hardware generation using symbolic computer algebra employing grobner basisSaman Fröhlich, Daniel Große, Rolf Drechsler. 889-892 [doi]
- m) bit-parallel multipliersJosé Luis Imana. 893-896 [doi]
- Processing in 3D memories to speed up operations on complex data structuresPaulo C. Santos, Geraldo F. Oliveira, Joao P. Lima, Marco Antonio Zanata Alves, Luigi Carro, Antonio C. S. Beck. 897-900 [doi]
- An efficient NBTI-aware wake-up strategy for power-gated designsKun-Wei Chiu, Yu-Guang Chen, Ing-Chao Lin. 901-904 [doi]
- Designing reliable processor cores in ultimate CMOS and beyond: A double sampling solutionThierry Bonnoit, Fraidy Bouesse, Nacer-Eddine Zergainoh, Michael Nicolaidis. 905-908 [doi]
- Design of a time-predictable multicore processor: The T-CREST projectMartin Schoeberl. 909-912 [doi]
- Error resilience analysis for systematically employing approximate computing in convolutional neural networksMuhammad Abdullah Hanif, Rehan Hafiz, Muhammad Shafique 0001. 913-916 [doi]
- DeMAS: An efficient design methodology for building approximate adders for FPGA-based systemsBharath Srinivas Prabakaran, Semeen Rehman, Muhammad Abdullah Hanif, Salim Ullah, Ghazal Mazaheri, Akash Kumar 0001, Muhammad Shafique 0001. 917-920 [doi]
- Gain scheduled control for nonlinear power management in CMPsBryan Donyanavard, Amir M. Rahmani, Tiago Mück, Kasra Moazemmi, Nikil D. Dutt. 921-924 [doi]
- Using polyhedral techniques to tighten WCET estimates of optimized code: A case study with array contractionThomas Lefeuvre, Imen Fassi, Christoph Cullmann, Gernot Gebhard, Emin-Koray Kasnakli, Isabelle Puaut, Steven Derrien. 925-930 [doi]
- Using multifunctional standardized stack as universal spintronic technology for IoTMehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Abdoulaye Gamatié, Pascal Nouet, F. Ouattara, Gilles Sassatelli, Kotb Jabeur, Pierre Vanhauwaert, A. Atitoaie, I. Firastrau, Gregory di Pendina, Guillaume Prenat. 931-936 [doi]
- Progress on carbon nanotube BEOL interconnectsB. Uhlig, J. Liang, J. Lee, R. Ramos, A. Dhavamani, N. Nagy, J. Dijon, H. Okuno, D. Kalita, Vihar P. Georgiev, A. Asenov, Salvatore M. Amoroso, Liping Wang, Campbell Millar, F. Konemann, B. Gotsmann, G. Goncalves, B. Chen, R. R. Pandey, R. Chen, A. Todri-Sanial. 937-942 [doi]
- A WCET-aware parallel programming model for predictability enhanced multi-core architecturesSimon Reder, Leonard Masing, Harald Bucher, Timon D. ter Braak, Timo Stripf, Jürgen Becker. 943-948 [doi]
- Online efficient bio-medical video transcoding on MPSoCs through content-aware workload allocationArman Iranfar, Ali Pahlevan, Marina Zapater, Martin Zagar, Mario Kovac, David Atienza. 949-954 [doi]
- Highly efficient and accurate seizure prediction on constrained IoT devicesFarzad Samie, Sebastian P. M. Paul, Lars Bauer, Jörg Henkel. 955-960 [doi]
- A wearable long-term single-lead ECG processor for early detection of cardiac arrhythmiaSyed Muhammad Abubakar, Wala Saadeh, Muhammad Awais Bin Altaf. 961-966 [doi]
- DroNet: Efficient convolutional neural network detector for real-time UAV applicationsChristos Kyrkou, George Plastiras, Theocharis Theocharides, Stylianos I. Venieris, Christos-Savvas Bouganis. 967-972 [doi]
- HyVE: Hybrid vertex-edge memory hierarchy for energy-efficient graph processingTianhao Huang, Guohao Dai, Yu Wang, Huazhong Yang. 973-978 [doi]
- Accurate neuron resilience prediction for a flexible reliability management in neural network acceleratorsChristoph Schorn, Andre Guntoro, Gerd Ascheid. 979-984 [doi]
- Rapid in-memory matrix multiplication using associative processorMohamed Ayoub Neggaz, Hasan Erdem Yantir, Smaïl Niar, Ahmed M. Eltawil, Fadi J. Kurdahi. 985-990 [doi]
- HiMap: A hierarchical mapping approach for enhancing lifetime reliability of dark silicon manycore systemsVijeta Rathore, Vivek Chaturvedi, Amit Kumar Singh, Thambipillai Srikanthan, R. Rohith, Siew Kei Lam, Muhammad Shaflque. 991-996 [doi]
- NBTI aged cell rejuvenation with back biasing and resulting critical path reordering for digital circuits in 28nm FDSOIAjith Sivadasan, Riddhi Jitendrakumar Shah, Vincent Huard, Florian Cacho, Lorena Anghel. 997-998 [doi]
- An industrial case study of low cost adaptive voltage scaling using delay test patternsMahroo Zandrahimi, Philippe Debaud, Armand Castillejo, Zaid Al-Ars. 999-1000 [doi]
- A case study for using dynamic partitioning based solution in volume diagnosisTao Wang, Zhangchun Shi, Junlin Huang, Huaxing Tang, Wu Yang, Junna Zhong. 1001-1002 [doi]
- On-line RF built-in self-test using noise injection and transmitter signal modulation by phase shifterJan Schat. 1003-1004 [doi]
- Neural networks for safety-critical applications - Challenges, experiments and perspectivesChih-Hong Cheng, Frederik Diehl, Gereon Hinz, Yassine Hamza, Georg Nührenberg, Markus Rickert 0001, Harald Ruess, Michael Truong Le. 1005-1006 [doi]
- IoT security assessment through the interfaces P-SCAN test bench platformThomas Maurin, Laurent-Frederic Ducreux, George Caraiman, Philippe Sissoko. 1007-1008 [doi]
- Supporting runtime reconfigurable VLIWs cores through dynamic binary translationSimon Rokicki, Erven Rohou, Steven Derrien. 1009-1014 [doi]
- uSFI: Ultra-lightweight software fault isolation for IoT-class devicesZelalem Birhanu Aweke, Todd M. Austin. 1015-1020 [doi]
- Converging safety and high-performance domains: Integrating OpenMP into AdaSara Royuela, Luís Miguel Pinho, Eduardo Quiñones. 1021-1026 [doi]
- Compiler-driven error analysis for designing approximate acceleratorsJorge Castro-Godinez, Sven Esser, Muhammad Shafique 0001, Santiago Pagani, Jörg Henkel. 1027-1032 [doi]
- Overview of the state of the art in embedded machine learningLiliana Andrade, Adrien Prost-Boucle, Frédéric Petrot. 1033-1038 [doi]
- PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networksAlexandre Carbon, J.-M. Philippe, Olivier Bichler, Renaud Schmit, Benoît Tain, D. Briand, Nicolas Ventroux, Michel Paindavoine, Olivier Brousse. 1039-1044 [doi]
- FFT-based deep learning deployment in embedded systemsSheng Lin, Ning Liu, Mahdi Nazemi, Hongjia Li, Caiwen Ding, Yanzhi Wang, Massoud Pedram. 1045-1050 [doi]
- A transprecision floating-point platform for ultra-low power computingGiuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, Luca Benini. 1051-1056 [doi]
- A peripheral circuit reuse structure integrated with a retimed data flow for low power RRAM crossbar-based CNNKeni Qiu, Weiwen Chen, Yuanchao Xu, Lixue Xia, Yu Wang 0002, Zili Shao. 1057-1062 [doi]
- Optimal DC/AC data bus inversion codingJan Lucas, Sohan Lal, Ben H. H. Juurlink. 1063-1068 [doi]
- LASER: A hardware/software approach to accelerate complicated loops on CGRAsMahesh Balasubramanian, Shail Dave, Aviral Shrivastava, Reiley Jeyapaul. 1069-1074 [doi]
- A time-multiplexed FPGA overlay with linear interconnectXiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy. 1075-1080 [doi]
- URECA: Unified register file for CGRAsShail Dave, Mahesh Balasubramanian, Aviral Shrivastava. 1081-1086 [doi]
- Optimizing the data placement and transformation for multi-bank CGRA computing systemZhongyuan Zhao, Yantao Liu, Weiguang Sheng, Tushar Krishna, Qin Wang, Zhigang Mao. 1087-1092 [doi]
- dReDBox: Materializing a full-stack rack-scale system prototype of a next-generation disaggregated datacenterM. Bielski, I. Syrigos, Kostas Katrinis, Dimitris Syrivelis, Andrea Reale, Dimitris Theodoropoulos, Nikolaos Alachiotis, Dionisis N. Pnevmatikatos, E. H. Pap, George Zervas, V. Mishra, A. Saljoghei, A. Rigo, Jose Fernando Zazo, Sergio López-Buedo, M. Torrents, Ferad Zyulkyarov, M. Enrico, Óscar González de Dios. 1093-1098 [doi]
- An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limitsGeorgios Karakonstantis, Konstantinos Tovletoglou, Lev Mukhanov, Hans Vandierendonck, Dimitrios S. Nikolopoulos, Peter Lawthers, Panos K. Koutsovasilis, Manolis Maroudas, Christos D. Antonopoulos, Christos Kalogirou, Nikolaos Bellas, Spyros Lalis, Srikumar Venugopal, Arnau Prat-Pérez, Alejandro Lampropulos, Marios Kleanthous, Andreas Diavastos, Zacharias Hadjilambrou, Panagiota Nikolaou, Yiannakis Sazeides, Pedro Trancoso, George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Shidhartha Das. 1099-1104 [doi]
- The transprecision computing paradigm: Concept, design, and applicationsA. Cristiano I. Malossi, Michael Schaffner, Anca Molnos, Luca Gammaitoni, Giuseppe Tagliavini, Andrew Emerson, Andrés Tomás, Dimitrios S. Nikolopoulos, Eric Flamand, Norbert Wehn. 1105-1110 [doi]
- An inside job: Remote power analysis attacks on FPGAsFalk Schellenberg, Dennis R. E. Gnad, Amir Moradi 0001, Mehdi Baradaran Tahoori. 1111-1116 [doi]
- Confident leakage assessment - A side-channel evaluation framework based on confidence intervalsFlorian Bache, Christina Plump, Tim Güneysu. 1117-1122 [doi]
- Øzone: Efficient execution with zero timing leakage for modern microarchitecturesZelalem Birhanu Aweke, Todd M. Austin. 1123-1128 [doi]
- SCADPA: Side-channel assisted differential-plaintext attack on bit permutation based ciphersJakub Breier, Dirmanto Jap, Shivam Bhasin. 1129-1134 [doi]
- Efficient mapping of quantum circuits to the IBM QX architecturesAlwin Zulehner, Alexandru Paler, Robert Wille. 1135-1138 [doi]
- Parallel code generation of synchronous programs for a many-core architectureAmaury Graillat, Matthieu Moy, Pascal Raymond, Benoît Dupont de Dinechin. 1139-1142 [doi]
- SOCRATES - A seamless online compiler and system runtime autotuning framework for energy-aware applicationsDavide Gadioli, Ricardo Nobre, Pedro Pinto, Emanuele Vitali, Amir H. Ashouri, Gianluca Palermo, João M. P. Cardoso, Cristina Silvano. 1143-1146 [doi]
- Non-intrusive program tracing of non-preemptive multitasking systems using power consumptionKamal Lamichhane, Carlos Moreno 0002, Sebastian Fischmeister. 1147-1150 [doi]
- Energy-performance design exploration of a low-power microprogrammed deep-learning acceleratorGiulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto. 1151-1154 [doi]
- GenPIM: Generalized processing in-memory to accelerate data intensive applicationsMohsen Imani, Saransh Gupta, Tajana Rosing. 1155-1158 [doi]
- Universal number posit arithmetic generator on FPGAManish Kumar Jaiswal, Hayden Kwok-Hay So. 1159-1162 [doi]
- Block convolution: Towards memory-efficient inference of large-scale CNNs on FPGAGang Li, Fanrong Li, Tianli Zhao, Jian Cheng. 1163-1166 [doi]
- Examining the consequences of high-level synthesis optimizations on power side-channelLu Zhang, Wei Hu, Armaiti Ardeshiricham, Yu Tai, Jeremy Blackstone, Dejun Mu, Ryan Kastner. 1167-1170 [doi]
- DFARPA: Differential fault attack resistant physical design automationMustafa Khairallah, Rajat Sadhukhan, Radhamanjari Samanta, Jakub Breier, Shivam Bhasin, Rajat Subhra Chakraborty, Anupam Chattopadhyay, Debdeep Mukhopadhyay. 1171-1174 [doi]
- An energy-efficient stochastic computational deep belief networkYidong Liu, Yanzhi Wang, Fabrizio Lombardi, Jie Han. 1175-1178 [doi]
- Pushing the number of qubits below the "minimum": Realizing compact boolean components for quantum logicAlwin Zulehner, Robert Wille. 1179-1182 [doi]
- Power optimization through peripheral circuit reusing integrated with loop tiling for RRAM crossbar-based CNNYuanhui Ni, Weiwen Chen, Wenjuan Cui, Yuanchun Zhou, Keni Qiu. 1183-1186 [doi]
- ORIENT: Organized interleaved ECCs for new STT-MRAM cachesZahra Azad, Hamed Farbeh, Amir Mahdi Hosseini Monazzah. 1187-1190 [doi]
- ERASMUS: Efficient remote attestation via self-measurement for unattended settingsXavier Carpent, Gene Tsudik, Norrathep Rattanavipanon. 1191-1194 [doi]
- End-to-end latency analysis of cause-effect chains in an engine management systemJunchul Choi, Donghyun Kang, Soonhoi Ha. 1195-1198 [doi]
- General floorplanning methodology for 3D ICs with an arbitrary bonding styleJai-Ming Lin, Chien-Yu Huang. 1199-1202 [doi]
- Digitalization in automotive and industrial systemsMatthias Traub, Hans-Jörg Vogel, Eric Sax, Thilo Streichert, Jérôme Härri. 1203-1204 [doi]
- Design and optimization of FeFET-based crossbars for binary convolution neural networksXiaoming Chen, Xunzhao Yin, Michael T. Niemier, Xiaobo Sharon Hu. 1205-1210 [doi]
- Low-power 3D integration using inductive coupling links for neurotechnology applicationsBenjamin J. Fletcher, Shidhartha Das, Chi-Sang Poon, Terrence S. T. Mak. 1211-1216 [doi]
- Mapping of local and global synapses on spiking neuromorphic hardwareAnup Das 0001, Yuefeng Wu, Khanh Huynh, Francesco Dell'Anna, Francky Catthoor, Siebren Schaafsma. 1217-1222 [doi]
- Energy-efficient neural networks using approximate computation reuseXun Jiao, Vahideh Akhlaghi, Yu Jiang, Rajesh K. Gupta 0001. 1223-1228 [doi]
- Multi-bit non-volatile spintronic flip-flopChristopher Munch, Rajendra Bishnoi, Mehdi Baradaran Tahoori. 1229-1234 [doi]
- ADAM: Architecture for write disturbance mitigation in scaled phase change memoryShivam Swami, Kartik Mohanram. 1235-1240 [doi]
- Program error rate-based wear leveling for NAND flash memoryXin Shi, Fei Wu, Shunzhuo Wang, Changsheng Xie, Zhonghai Lu. 1241-1246 [doi]
- ShadowGC: Cooperative garbage collection with multi-level buffer for performance improvement in NAND flash-based SSDsJinhua Cui, Youtao Zhang, Jianhang Huang, Weiguo Wu, Jun Yang. 1247-1252 [doi]
- Binary Ring-LWE hardware with power side-channel countermeasuresAydin Aysu, Michael Orshansky, Mohit Tiwari. 1253-1258 [doi]
- High speed ASIC implementations of leakage-resilient cryptographyRobert Schilling, Thomas Unterluggauer, Stefan Mangard, Frank K. Gürkaynak, Michael Muehlberghuber, Luca Benini. 1259-1264 [doi]
- Optimization of the PLL configuration in a PLL-based TRNG designElie Noumon Allini, Oto Petura, Viktor Fischer, Florent Bernard. 1265-1270 [doi]
- Availability enhancement and analysis for mixed-criticality systems on multi-coreRoberto Medina, Etienne Borde, Laurent Pautet. 1271-1276 [doi]
- Mixed-criticality scheduling with memory bandwidth regulationMuhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Akesson, Eduardo Tovar. 1277-1282 [doi]
- Design and validation of fault-tolerant embedded controllersSaurav Kumar Ghosh, Soumyajit Dey, Dip Goswami, Daniel Mueller-Gritschneder, Samarjit Chakraborty. 1283-1288 [doi]
- Computing with ferroelectric FETs: Devices, models, systems, and applicationsAhmedullah Aziz, Evelyn T. Breyer, An Chen, Xiaoming Chen, Suman Datta, Sumeet Kumar Gupta, Michael Hoffmann, Xiaobo Sharon Hu, Adrian Ionescu, Matthew Jerry, Thomas Mikolajick, Halid Mulaosmanovic, Kai Ni, Michael T. Niemier, Ian O'Connor, Atanu Saha, Stefan Slesazeck, Sandeep Krishna Thirumala, Xunzhao Yin. 1289-1298 [doi]
- The CAMEL approach to stacked sensor smart camerasSaibal Mukhopadhyay, Marilyn Wolf, Mohammed F. Amir, Evan Gebahrdt, Jong Hwan Ko, Jae Ha Kung, Burhan Ahmad Musassar. 1299-1303 [doi]
- A design tool for high performance image processing on multicore platformsJiahao Wu, Timothy Blattner, Walid Keyrouz, Shuvra S. Bhattacharyya. 1304-1309 [doi]
- Quasar, a high-level programming language and development environment for designing smart vision systems on embedded platformsBart Goossens, Hiêp Quang Luong, Jan Aelterman, Wilfried Philips. 1310-1315 [doi]
- Concurrent focal-plane generation of compressed samples from time-encoded pixel valuesMarco Trevisi, H. C. Bandala, Jorge Fernández-Berni, Ricardo Carmona-Galán, Ángel Rodríguez-Vázquez. 1316-1320 [doi]
- Contactless finger and face capturing on a secure handheld embedded deviceAxel Weissenfeld, Bernhard Strobl, Franz Daubner. 1321-1326 [doi]
- A faithful binary circuit model with adversarial noiseMatthias Függer, Jürgen Maier 0002, Robert Najvirt, Thomas Nowak, Ulrich Schmid 0001. 1327-1332 [doi]
- EVT-based worst case delay estimation under process variationCharalampos Antoniadis, Dimitrios Garyfallou, Nestor E. Evmorfopoulos, Georgios I. Stamoulis. 1333-1338 [doi]
- Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designsJai-Ming Lin, Chien-Yu Huang, Jhih-Ying Yang. 1339-1344 [doi]
- Accelerate analytical placement with GPU: A generic approachChun-Xun Lin, Martin D. F. Wong. 1345-1350 [doi]
- High performance collective communication-aware 3D Network-on-Chip architecturesBiresh Kumar Joardar, Karthi Duraisamy, Partha Pratim Pande. 1351-1356 [doi]
- A soft-error resilient route computation unit for 3D Networks-on-ChipsAlexandre Coelho, Amir Charif, Nacer-Eddine Zergainoh, Juan A. Fraire, Raoul Velazco. 1357-1362 [doi]
- SPA: Simple pool architecture for application resource allocation in many-core systemsJayasimha Sai Koduri, Iraklis Anagnostopoulos. 1364-1368 [doi]
- RSON: An inter/intra-chip silicon photonic network for rack-scale computing systemsPeng Yang, Zhengbin Pang, Zhifei Wang, Zhehui Wang, Min Xie, Xuanqi Chen, Luan H. K. Duong, Jiang Xu 0001. 1369-1374 [doi]
- HME: A lightweight emulator for hybrid memoryZhuohui Duan, Haikun Liu, Xiaofei Liao, Hai Jin. 1375-1380 [doi]
- VerC3: A library for explicit state synthesis of concurrent systemsMarco Elver, Christopher J. Banks, Paul Jackson, Vijay Nagarajan. 1381-1386 [doi]
- Prometheus: Processing-in-memory heterogeneous architecture design from a multi-layer network theoretic strategyYao Xiao, Shahin Nazarian, Paul Bogdan. 1387-1392 [doi]
- Advancing source-level timing simulation using loop accelerationJoscha Benz, Christoph Gerum, Oliver Bringmann. 1393-1398 [doi]
- Storage-aware sample preparation using flow-based microfluidic Labs-on-ChipSukanta Bhattacharjee, Robert Wille, Juinn-Dar Huang, Bhargab B. Bhattacharya. 1399-1404 [doi]
- Pump-aware flow routing algorithm for programmable microfluidic devicesGuan-Ru Lai, Chun-Yu Lin, Tsung-Yi Ho. 1405-1410 [doi]
- Adaptive approximation in arithmetic circuits: A low-power unsigned divider designHonglan Jiang, Leibo Liu, Fabrizio Lombardi, Jie Han. 1411-1416 [doi]
- Correlation manipulating circuits for stochastic computingVincent T. Lee, Armin Alaghi, Luis Ceze. 1417-1422 [doi]
- XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networksXiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu. 1423-1428 [doi]
- A novel fault tolerant cache architecture based on orthogonal latin squares theoryFilippos Filippou, Georgios Keramidas, Michail Mavropoulos, Dimitris Nikolos. 1429-1434 [doi]
- Technology-aware logic synthesis for ReRAM based in-memory computingDebjyoti Bhattacharjee, Luca Amarù, Anupam Chattopadhyay. 1435-1440 [doi]
- Leveraging thermally-aware chiplet organization in 2.5D systems to reclaim dark siliconFurkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Saiful A. Mojumder, Tiansheng Zhang. 1441-1446 [doi]
- Ising-PUF: A machine learning attack resistant PUF featuring lattice like arrangement of Arbiter-PUFsHiromitsu Awano, Takashi Sato. 1447-1452 [doi]
- Efficient helper data reduction in SRAM PUFs via lossy compressionYe Wang, Michael Orshansky. 1453-1458 [doi]
- Improving the efficiency of thermal covert channels in multi-/many-core systemsZijun Long, Xiaohang Wang, Yingtao Jiang, Guofeng Cui, Li Zhang, Terrence S. T. Mak. 1459-1464 [doi]
- A placement algorithm for superconducting logic circuits based on cell grouping and super-cell placementSoheil Nazar Shahsavani, Alireza Shafaei, Massoud Pedram. 1465-1468 [doi]
- Abax: 2D/3D legaliser supporting look-ahead legalisation and blockage strategiesNikolaos Sketopoulos, Christos Sotiriou, Stavros Simoglou. 1469-1472 [doi]
- LESAR: A dynamic line-end spacing aware detailed routerYing-Chi Wei, Radhamanjari Samanta, Yih-Lang Li. 1473-1476 [doi]
- Understanding turn models for adaptive routing: The modular approachEdoardo Fusella, Alessandro Cilardo. 1477-1480 [doi]
- Quater-imaginary base for complex number arithmetic circuitsSouradip Sarkar, Manil Dev Gomony. 1481-1483 [doi]
- Fault-tolerant valve-based microfluidic routing fabric for droplet barcoding in single-cell analysisYasamin Moradi, Mohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann. 1484-1487 [doi]
- Optimizing power-accuracy trade-off in approximate addersD. Celia, Vinita Vasudevan, Nitin Chandrachoodan. 1488-1491 [doi]
- Improving the error behavior of DRAM by exploiting its Z-channel propertyKira Kraft, Chirag Sudarshan, Deepak M. Mathew, Christian Weis, Norbert Wehn, Matthias Jung 0001. 1492-1495 [doi]
- Architecture and optimization of associative memories used for the implementation of logic functions based on nanoelectronic 1S1R cellsArne Heittmann, Tobias G. Noll. 1496-1499 [doi]
- Accurate prediction of smartphones' skin temperature by considering exothermic componentsJiHoon Park, Seokjun Lee, Hojung Cha. 1500-1503 [doi]
- Trustworthy proofs for sensor data using FPGA based physically unclonable functionsUrbi Chatterjee, Durga Prasad Sahoo, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty. 1504-1507 [doi]
- Towards fully automated TLM-to-RTL property refinementVladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler. 1508-1511 [doi]
- In-memory computing using paths-based logic and heterogeneous componentsAlvaro Velasquez, Sumit Kumar Jha 0001. 1512-1515 [doi]
- Non-intrusive testing technique for detection of Trojans in asynchronous circuitsLeonel Acunha Guimaraes, Thiago Ferreira de Paiva Leite, Rodrigo Possamai Bastos, Laurent Fesquet. 1516-1519 [doi]
- Towards inter-vendor compatibility of true random number generators for FPGAsMilos Grujic, Bohan Yang 0001, Vladimir Rozic, Ingrid Verbauwhede. 1520-1523 [doi]
- Efficient wear leveling for inodes of file systems on persistent memoriesXianzhang Chen, Edwin Hsing-Mean Sha, Yuansong Zeng, Chaoshu Yang, Weiwen Jiang, Qingfeng Zhuge. 1524-1527 [doi]
- Exploring non-volatile main memory architectures for handheld devicesSneha Ved, Manu Awasthi. 1528-1531 [doi]
- Design methodologies for enabling self-awareness in autonomous systemsArmin Sadighi, Bryan Donyanavard, Thawra Kadeed, Kasra Moazzemi, Tiago Mück, Ahmed Nassar, Amir M. Rahmani, Thomas Wild, Nikil D. Dutt, Rolf Ernst, Andreas Herkersdorf, Fadi J. Kurdahi. 1532-1537 [doi]
- Directed test generation using concolic testing on RTL modelsAlif Ahmed, Farimah Farahmandi, Prabhat Mishra. 1538-1543 [doi]
- Suspect set prediction in RTL bug huntingNeil Veira, Zissis Poulos, Andreas G. Veneris. 1544-1549 [doi]
- Symbolic assertion mining for security validationAlessandro Danese, Valeria Bertacco, Graziano Pravadelli. 1550-1555 [doi]
- Improving and extending the algebraic approach for verifying gate-level multipliersDaniela Ritirc, Armin Biere, Manuel Kauers. 1556-1561 [doi]
- Reconfigurable asynchronous pipelines: From formal models to siliconDanil Sokolov, Alessandro de Gennaro, Andrey Mokhov. 1562-1567 [doi]
- Automatic generation of hardware checkers from formal micro-architectural specificationsAlexander Fedotov, Julien Schmaltz. 1568-1573 [doi]
- Specification decomposition for synthesis from libraries of LTL Assume/Guarantee contractsAntonio Iannopollo, Stavros Tripakis, Alberto L. Sangiovanni-Vincentelli. 1574-1579 [doi]
- Hardware-assisted rootkit detection via on-line statistical fingerprinting of process executionLiwei Zhou, Yiorgos Makris. 1580-1585 [doi]
- Securing conditional branches in the presence of fault attacksRobert Schilling, Mario Werner, Stefan Mangard. 1586-1591 [doi]
- Towards provably-secure performance lockingMonir Zaman, Abhrajit Sengupta, Danqing Liu, Ozgur Sinanoglu, Yiorgos Makris, Jeyavijayan J. V. Rajendran. 1592-1597 [doi]
- An automated configurable Trojan insertion framework for dynamic trust benchmarksJonathan Cruz, Yuanwen Huang, Prabhat Mishra, Swarup Bhunia. 1598-1603 [doi]
- Extending the lifetime of NVMs with compressionJie Xu, Dan Feng, Yu Hua, Wei Tong, Jingning Liu, Chunyan Li. 1604-1609 [doi]
- Heterogeneous PCM array architecture for reliability, performance and lifetime enhancementTaeHyun Kwon, Muhammad Imran, Jung Min You, Joon-Sung Yang. 1610-1615 [doi]
- An efficient PCM-based main memory system via exploiting fine-grained dirtiness of cachelinesJie Xu, Dan Feng, Yu Hua, Wei Tong, Jingning Liu, Chunyan Li, Zheng Li. 1616-1621 [doi]
- DFPC: A dynamic frequent pattern compression scheme in NVM-based main memoryYuncheng Guo, Yu Hua, Pengfei Zuo. 1622-1627 [doi]
- Practical challenges in delivering the promises of real processing-in-memory machinesNishil Talati, Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky. 1628-1633 [doi]
- Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfacesMaha Kooli, Henri-Pierre Charles, Clément Touzet, Bastien Giraud, Jean-Philippe Noel. 1634-1639 [doi]
- Computing-in-memory with spintronicsShubham Jain, Sachin S. Sapatnekar, Jian-Ping Wang, Kaushik Roy 0001, Anand Raghunathan. 1640-1645 [doi]
- Memristive devices for computation-in-memoryJintao Yu, Hoang Anh Du Nguyen, Lei Xie 0005, Mottaqiallah Taouil, Said Hamdioui. 1646-1651 [doi]
- Energy-secure swarm power managementAugusto Vega, Alper Buyuktosunoglu, Pradip Bose. 1652-1657 [doi]
- SMARTag: Error Correction in Cache Tag Array by Exploiting Address LocalitySeyedeh Golsana Ghaemi, Iman Ahmadpour, Mehdi Ardebili, Hamed Farbeh. 1658-1663 [doi]