Ajith Sivadasan - researchr alias

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Viewing Publication 1 - 6 from 6

2018

NBTI aged cell rejuvenation with back biasing and resulting critical path reordering for digital circuits in 28nm FDSOIAjith Sivadasan, Riddhi Jitendrakumar Shah, Vincent Huard, Florian Cacho, Lorena Anghel. date 2018: 997-998 [doi]

2017

Workload dependent reliability timing analysis flowAjith Sivadasan, Armelle Notin, Vincent Huard, Etienne Maurin, Souhir Mhira, Florian Cacho, Lorena Anghel. date 2017: 736-737 [doi]

2016

Early system failure prediction by using aging in situ monitors: Methodology of implementation and application resultsLorena Anghel, A. Benhassain, Ajith Sivadasan, Florian Cacho, Vincent Huard. vts 2016: 1 [doi]

Activity profiling: Review of different solutions to develop reliable and performant designFlorian Cacho, Ahmed Benhassain, S. Mhira, Ajith Sivadasan, Vincent Huard, P. Cathelin, V. Knopik, A. Jain, C. R. Parthasarathy, Lorena Anghel. iolts 2016: 47-50 [doi]

Study of workload impact on BTI HCI induced aging of digital circuitsAjith Sivadasan, Florian Cacho, Sidi Ahmed Benhassain, Vincent Huard, Lorena Anghel. date 2016: 1020-1021 [doi]

Workload Impact on BTI HCI Induced Aging of Digital Circuits: A System level AnalysisAjith Sivadasan, Florian Cacho, Sidi Ahmed Benhassain, Vincent Huard, Lorena Anghel. date 2016: 38-40 [doi]

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