Table of Contents

• Towards performance and reliability-efficient computing in the dark silicon eraJörg Henkel, Santiago Pagani, Heba Khdr, Florian Kriebel, Semeen Rehman, Muhammad Shafique. 1-6 [doi]
• Towards near-threshold server processorsAli Pahlevan, Javier Picorel, Arash Pourhabibi Zarandi, Davide Rossi, Marina Zapater, Andrea Bartolini, Pablo Garcia Del Valle, David Atienza, Luca Benini, Babak Falsafi. 7-12 [doi]
• Can beyond-CMOS devices illuminate dark silicon?Robert Perricone, Xiaobo Sharon Hu, Joseph Nahas, Michael T. Niemier. 13-18 [doi]
• OTEM: Optimized Thermal and Energy Management for Hybrid Electrical Energy Storage in Electric VehiclesKorosh Vatanparvar, Mohammad Abdullah Al Faruque. 19-24 [doi]
• Supertask: Maximizing runnable-level parallelism in AUTOSAR applicationsSebastian Kehr, Milos Panic, Eduardo Quiñones, Bert Böddeker, Jorge Becerril Sandoval, Jaume Abella, Francisco J. Cazorla, Günter Schafer. 25-30 [doi]
• Formal analysis based evaluation of software defined networking for time-sensitive EthernetDaniel Thiele, Rolf Ernst. 31-36 [doi]
• Accelerated Artificial Neural Networks on FPGA for fault detection in automotive systemsShanker Shreejith, Bezborah Anshuman, Suhaib A. Fahmy. 37-42 [doi]
• Optimization for Multiple Patterning Lithography with cutting process and beyondJian Kuang 0001, Evangeline F. Y. Young. 43-48 [doi]
• A fast manufacturability aware Optical Proximity Correction (OPC) algorithm with adaptive wafer image estimationAhmed Awad, Atsushi Takahashi 0001, Chikaaki Kodama. 49-54 [doi]
• Redundant via insertion in directed self-assembly lithographyWoohyun Chung, Seongbo Shim, Youngsoo Shin. 55-60 [doi]
• Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stackingKwangsoo Han, Andrew B. Kahng, Jiajia Li. 61-66 [doi]
• A discrete thermal controller for chip-multiprocessorsYingnan Cui, Wei Zhang, Bingsheng He. 67-72 [doi]
• Swallow: Building an energy-transparent many-core embedded real-time systemSimon J. Hollis, Steve Kerrison. 73-78 [doi]
• A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancementsYen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang. 79-84 [doi]
• Efficient kernel management on GPUsXiuhong Li, Yun Liang. 85-90 [doi]
• Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faultsDamien Hardy, Isabelle Puaut, Yiannakis Sazeides. 91-96 [doi]
• A four-mode model for efficient fault-tolerant mixed-criticality systemsZaid Al-bayati, Jonah Caplan, Brett H. Meyer, Haibo Zeng. 97-102 [doi]
• Providing formal latency guarantees for ARQ-based protocols in Networks-on-ChipEberle A. Rambo, Selma Saidi, Rolf Ernst. 103-108 [doi]
• Achieving 100% cell-aware coverage by designZeye Dexter Liu, Ben Niewenhuis, Soumya Mittal, R. D. (Shawn) Blanton. 109-114 [doi]
• Modeling fabrication non-uniformity in chip-scale silicon photonic interconnectsMahdi Nikdast, Gabriela Nicolescu, Jelena Trajkovic, Odile Liboiron-Ladouceur. 115-120 [doi]
• Efficient spatial variation modeling via robust dictionary learningChanghai Liao, Jun Tao, Xuan Zeng, Yangfeng Su, Dian Zhou, Xin Li 0001. 121-126 [doi]
• TOTAL: TRNG on-the-fly testing for attack detection using Lightweight hardwareBohan Yang 0001, Vladimir Rozic, Nele Mentens, Wim Dehaene, Ingrid Verbauwhede. 127-132 [doi]
• On-chip fingerprinting of IC topology for integrity verificationMaxime Lecomte, Jacques J. A. Fournier, Philippe Maurine. 133-138 [doi]
• Activation of logic encrypted chips: Pre-test or post-test?Muhammad Yasin, Samah Mohamed Saeed, Jeyavijayan Rajendran, Ozgur Sinanoglu. 139-144 [doi]
• Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computingSyed Shakib Sarwar, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy. 145-150 [doi]
• Significance driven hybrid 8T-6T SRAM for energy-efficient synaptic storage in artificial neural networksGopalakrishnan Srinivasan, Parami Wijesinghe, Syed Shakib Sarwar, Akhilesh Jaiswal, Kaushik Roy. 151-156 [doi]
• Network delay-aware energy management for mobile systemsMinho Ju, Hyeonggyu Kim, Soontae Kim. 157-162 [doi]
• Enabling simultaneously bi-directional TSV signaling for energy and area efficient 3D-ICsSunghyun Park, Alice Wang, Uming Ko, Li-Shiuan Peh, Anantha P. Chandrakasan. 163-168 [doi]
• Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuitsJens Trommer, Andre Heinzig, Tim Baldauf, Thomas Mikolajick, Walter M. Weber, Michael Raitza, Marcus Völp. 169-174 [doi]
• Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checkingLuca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Robert Wille, Giovanni De Micheli. 175-180 [doi]
• Conservative modeling of shared resource contention for dependent tasks in partitioned multi-core systemsJunchul Choi, Donghyun Kang, Soonhoi Ha. 181-186 [doi]
• Formal worst-case timing analysis of Ethernet TSN's burst-limiting shaperDaniel Thiele, Rolf Ernst. 187-192 [doi]
• Real-time analysis of engine control applications with speed estimationAlessandro Biondi, Giorgio C. Buttazzo. 193-198 [doi]
• Trace-based analysis methodology of program flash contention in embedded multicore systemsLin Li, Albrecht Mayer. 199-204 [doi]
• A cross-layer analysis of Soft Error, aging and process variation in Near Threshold ComputingAnteneh Gebregiorgis, Saman Kiamehr, Fabian Oboril, Rajendra Bishnoi, Mehdi Baradaran Tahoori. 205-210 [doi]
• Fast-yet-accurate variation-aware current and voltage modelling of radiation-induced transient faultHsuan-Ming Huang, Yuwen Lin, Charles H.-P. Wen. 211-216 [doi]
• A detailed methodology to compute Soft Error Rates in advanced technologiesMarc Riera, Ramon Canal, Jaume Abella, Antonio González 0001. 217-222 [doi]
• Analysis of NBTI effects on high frequency digital circuitsAhmet Unutulmaz, Domenik Helms, Reef Eilers, Malte Metzdorf, Ben Kaczer, Wolfgang Nebel. 223-228 [doi]
• A scalable lane detection algorithm on COTSs with OpenCLKai Huang, Biao Hu, Jan Botsch, Nikhil Madduri, Alois Knoll. 229-232 [doi]
• Simulation of falling rain for robustness testing of video-based surround sensing systemsDennis Hospach, Stefan Müller, Wolfgang Rosenstiel, Oliver Bringmann. 233-236 [doi]
• Proposal for fast directional energy interchange used in MCMC-based autonomous decentralized mechanism toward resilient microgridYusuke Sakumoto, Ittetsu Taniguchi. 237-240 [doi]
• Grid-based Self-Aligned Quadruple Patterning aware two dimensional routing patternTakeshi Ihara, Toshiyuki Hongo, Atsushi Takahashi 0001, Chikaaki Kodama. 241-244 [doi]
• Practical ILP-based routing of standard cellsHsueh-Ju Lu, En-Jang Jang, Ang Lu, Yu Ting Zhang, Yu-He Chang, Chi-Hung Lin, Rung-Bin Lin. 245-248 [doi]
• A procedure for improving the distribution of congestion in global routingDaohang Shi, Azadeh Davoodi, Jeffrey T. Linderoth. 249-252 [doi]
• Machine Learned Machines: Adaptive co-optimization of caches, cores, and On-chip NetworkRahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney. 253-256 [doi]
• Improving performance by monitoring while maintaining worst-case guaranteesSyed Md Jakaria Abdullah, Kai Lampka, Wang Yi 0001. 257-260 [doi]
• Fault Tolerant Non-Volatile spintronic flip-flopRajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori. 261-264 [doi]
• Towards automatic diagnosis of minority carriers propagation problems in HV/HT automotive smart power ICsYasser Moursy, Hao Zou, Ramy Iskander, Pierre Tisserand, Dieu-My Ton, Giuseppe Pasetti, Ehrenfried Seebacher, Alexander Steinmair, Thomas Gneiting, Heidrun Alius. 265-268 [doi]
• HPAZ: A high-throughput pipeline architecture of ZUC in hardwareZongbin Liu, Qinglong Zhang, Cunqing Ma, Changting Li, Jiwu Jing. 269-272 [doi]
• Towards a highly reliable SRAM-based PUFsElena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto. 273-276 [doi]
• Current based PUF exploiting random variations in SRAM cellsFengchao Zhang, Shuo Yang, Jim Plusquellic, Swarup Bhunia. 277-280 [doi]
• Behavioral modeling of timing slack variation in digital circuits due to power supply noiseTaesik Na, Saibal Mukhopadhyay. 281-284 [doi]
• Lossless compression algorithm based on dictionary coding for multiple e-beam direct write systemPei-Chun Lin, Yu-Hsuan Pai, Yu-Hsiang Chiu, Shao-Yuan Fang, Charlie Chung-Ping Chen. 285-288 [doi]
• PhoNoCMap: An application mapping tool for photonic networks-on-chipEdoardo Fusella, Alessandro Cilardo. 289-292 [doi]
• Design of an efficient ready queue for earliest-deadline-first (EDF) schedulerRisat Mahmud Pathan. 293-296 [doi]
• RT level timing modeling for aging predictionNils Koppaetzky, Malte Metzdorf, Reef Eilers, Domenik Helms, Wolfgang Nebel. 297-300 [doi]
• Fast time-domain simulation for reliable fault detectionBratislav Tasic, Jos J. Dohmen, Rick Janssen, E. Jan W. ter Maten, Theo G. J. Beelen, Roland Pulch. 301-306 [doi]
• Holistic coupled field and circuit simulationWim Schoenmaker, Peter Meuris, Christian Strohm, Caren Tischendorf. 307-312 [doi]
• Model Order Reduction for nanoelectronics coupled problems with many inputsNicodemus Banagaaya, Liong Feng, Wim Schoenmaker, Peter Meuris, Aarnout Wieers, Renaud Gillon, Peter Benner. 313-318 [doi]
• Shape optimization of a power MOS device under uncertaintiesPiotr Putek, Peter Meuris, Roland Pulch, E. Jan W. ter Maten, Michael Gunther, Wim Schoenmaker, Frederik Deleu, Aarnout Wieers. 319-324 [doi]
• Practical evaluation of code injection in encrypted firmware updatesOscar M. Guillen, Dawin Schmidt, Georg Sigl. 325-330 [doi]
• Integration of ROP/JOP monitoring IPs in an ARM-based SoCYongje Lee, JinYong Lee, Ingoo Heo, Dongil Hwang, Yunheung Paek. 331-336 [doi]
• Verifying information flow properties of firmware using symbolic executionPramod Subramanyan, Sharad Malik, Hareesh Khattri, Abhranil Maiti, Jason Fung. 337-342 [doi]
• Low-overhead adaptive constrast enhancement and power reduction for OLEDsDaniele Jahier Pagliari, Massimo Poncino, Enrico Macii. 343-348 [doi]
• Dynamic energy burst scaling for transiently powered systemsAndres Gomez, Lukas Sigrist, Michele Magno, Luca Benini, Lothar Thiele. 349-354 [doi]
• Low-power multichannel spectro-temporal feature extraction circuit for audio pattern wake-upDinko Oletic, Vedran Bilas, Michele Magno, Norbert Felber, Luca Benini. 355-360 [doi]
• 3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applicationsNavneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel. 361-366 [doi]
• Design of latches and flip-flops using emerging tunneling devicesXunzhao Yin, Behnam Sedighi, Michael T. Niemier, Xiaobo Sharon Hu. 367-372 [doi]
• MASC: Ultra-low energy multiple-access single-charge TCAM for approximate computingMohsen Imani, Shruti Patil, Tajana S. Rosing. 373-378 [doi]
• Distributed fair scheduling for many-coresAnuj Pathania, Vanchinathan Venkataramani, Muhammad Shafique, Tulika Mitra, Jörg Henkel. 379-384 [doi]
• Keep it slow and in time: Online DVFS with hard real-time workloadsKai Lampka, Bjorn Forsberg. 385-390 [doi]
• Exploiting process variation for retention induced refresh minimization on flash memoryYejia Di, Liang Shi, Kaijie Wu, Chun Jason Xue. 391-396 [doi]
• Accurate synthesis of integrated RF passive components using surrogate modelsFábio Passos, Reinier Gonzalez-Echevarria, Elisenda Roca, R. Castro-López, Francisco V. Fernández. 397-402 [doi]
• Implementation and quality testing for compact models implemented in Verilog-AAnindya Mukherjee, Andreas Pawlak, Michael Schroter, Didier Celi, Zoltan Huszka. 403-408 [doi]
• Multi-harmonic nonlinear modeling of low-power PWM DC-DC converters operating in CCM and DCMYa Wang, Di Gao, Dani A. Tannir, Peng Li. 409-414 [doi]
• Availability and interpretability of optimal control for criticality estimation in vehicle active safetyStephan Herrmann, Wolfgang Utschick. 415-420 [doi]
• Fading memory effects in a memristor for Cellular Nanoscale Network applicationsAlon Ascoli, Ronald Tetzlaff, Leon O. Chua, John Paul Strachan, R. Stanley Williams. 421-425 [doi]
• Digital Memcomputing MachinesMassimiliano Di Ventra, Fabio L. Traversa. 426 [doi]
• The Programmable Logic-in-Memory (PLiM) computerPierre-Emmanuel Gaillardon, Luca Amaru, Anne Siemon, Eike Linn, Rainer Waser, Anupam Chattopadhyay, Giovanni De Micheli. 427-432 [doi]
• Oracle-guided incremental SAT solving to reverse engineer camouflaged logic circuitsDuo Liu, Cunxi Yu, Xiangyu Zhang, Daniel E. Holcomb. 433-438 [doi]
• A fully-digital EM pulse detectorDavid El-Baze, Jean-Baptiste Rigaud, Philippe Maurine. 439-444 [doi]
• On the development of a new countermeasure based on a laser attack RTL fault modelCharalampos Ananiadis, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle. 445-450 [doi]
• Multi-story power distribution networks for GPUsQixiang Zhang, Liangzhen Lai, Mark Gottscho, Puneet Gupta. 451-456 [doi]
• Energy-efficient cache memories using a dual-Vt 4T SRAM cell with read-assist techniquesAlireza Shafaei, Massoud Pedram. 457-462 [doi]
• Learning-based dynamic reliability management for dark silicon processor considering EM effectsTaeyoung Kim, Xin Huang, Hai-Bao Chen, Valeriy Sukharev, Sheldon X.-D. Tan. 463-468 [doi]
• MNSIM: Simulation platform for memristor-based neuromorphic computing systemLixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Xiling Yin, Wenqin Huangfu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie 0001, Huazhong Yang. 469-474 [doi]
• Conditional Deep Learning for energy-efficient and enhanced pattern recognitionPriyadarshini Panda, Abhronil Sengupta, Kaushik Roy. 475-480 [doi]
• Probabilistic Error Models for machine learning kernels implemented on stochastic nanoscale fabricsSai Zhang, Naresh R. Shanbhag. 481-486 [doi]
• A new parallel SystemC kernel leveraging manycore architecturesNicolas Ventroux, Tanguy Sassolas. 487-492 [doi]
• SystemC-link: Parallel SystemC simulation using time-decoupled segmentsJan Henrik Weinstock, Rainer Leupers, Gerd Ascheid, Dietmar Petras, Andreas Hoffmann. 493-498 [doi]
• Orthogonal signal modeling and operational computation of AMS circuits for fast and accurate system simulationLeandro Gil, Martin Radetzki. 499-504 [doi]
• Built-in test of millimeter-Wave circuits based on non-intrusive sensorsAthanasios Dimakos, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, Salvador Mir, Emeric de Foucauld. 505-510 [doi]
• Adaptive delay monitoring for wide voltage-range operationJongho Kim, Gunhee Lee, Kiyoung Choi, YongHwan Kim, Wook Kim, Kyung Tae Do, Jungyun Choi. 511-516 [doi]
• Analytical design optimization of sub-ranging ADC based on stochastic comparatorMd. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada. 517-522 [doi]
• Analyzing the impact of injected sensor data on an Advanced Driver Assistance System using the OP2TIMUS prototyping platformAlexander Stühring, Günter Ehmen, Sibylle B. Fröschle. 523-526 [doi]
• Hardware Trojans in incompletely specified on-chip bus systemsNicole Fern, Ismail San, Çetin Kaya Koç, Kwang-Ting Cheng. 527-530 [doi]
• Workload-aware power optimization strategy for asymmetric multiprocessorsE. Del Sozzo, Gianluca C. Durelli, E. M. G. Trainiti, Antonio Miele, Marco D. Santambrogio, Cristiana Bolchini. 531-534 [doi]
• The slowdown or race-to-idle question: Workload-aware energy optimization of SMT multicore platforms under process variationAnup Das 0001, Geoff V. Merrett, Bashir M. Al-Hashimi. 535-538 [doi]
• Towards general purpose computations on low-end mobile GPUsMatina Maria Trompouki, Leonidas Kosmidis. 539-542 [doi]
• Estimating delay differences of arbiter PUFs using silicon dataS. V. Sandeep Avvaru, Chen Zhou, Saroj Satapathy, Yingjie Lao, Chris H. Kim, Keshab K. Parhi. 543-546 [doi]
• On the use of Forward Body Biasing to decrease the repeatability of laser-induced faultsMarc Lacruche, Noemie Beringuier-Boher, Jean-Max Dutertre, Jean-Baptiste Rigaud, Edith Kussener. 547-550 [doi]
• Sequential analysis driven reset optimization to improve power, area and routabilitySrihari Yechangunja, Raj Shekhar, Mohit Kumar, Nikhil Tripathi, Abhishek Mittal, Abhishek Ranjan, Jianfeng Liu, Minyoung Mo, Kyung Tae Do, Jung Yun Choi, Sungho Park. 551-554 [doi]
• Efficient global optimization of MEMS based on surrogate model assisted evolutionary algorithmBo Liu, Anna Nikolaeva. 555-558 [doi]
• Efficient monitoring of loose-ordering properties for SystemC/TLMYuliia Romenska, Florence Maraninchi. 559-562 [doi]
• Testable design of repeaterless low swing on-chip interconnectK. Naveen, Dinesh Kumar Sharma. 563-566 [doi]
• All-digital hybrid-control buck converter for Integrated Voltage Regulator applicationsTa-Tung Yen, Bin Yu, Visvesh S. Sathe. 567-570 [doi]
• Panel: Looking backwards and forwardsMarco Casale-Rossi, Giovanni De Micheli, Antun Domic, Enrico Macii, Domenico Rossi, Joseph Sawicki. 571-575 [doi]
• Aging-aware voltage scalingVictor M. van Santen, Hussam Amrouch, Narendra Parihar, Souvik Mahapatra, Jörg Henkel. 576-581 [doi]
• RECORD: Reducing register traffic for checkpointing in embedded processorsTuo Li 0001, Jude Angelo Ambrose, Sri Parameswaran. 582-587 [doi]
• Error resilience and energy efficiency: An LDPC decoder design studyPhilipp Schläfer, Chu-Hsiang Huang, Clayton Schoeny, Christian Weis, Yao Li, Norbert Wehn, Lara Dolecek. 588-593 [doi]
• Runtime interval optimization and dependable performance for application-level checkpointingApostolos Kokolis, Alexandros Mavrogiannis, Dimitrios Rodopoulos, Christos Strydis, Dimitrios Soudris. 594-599 [doi]
• A systematic approach to automated construction of power emulation modelsBenjamin A. Bjornseth, Asbjørn Djupdal, Lasse Natvig. 600-605 [doi]
• Automatic generation of power state machines through dynamic mining of temporal assertionsAlessandro Danese, Graziano Pravadelli, Ivan Zandona. 606-611 [doi]
• Approximation through logic isolation for the design of quality configurable circuitsShubham Jain, Swagath Venkataramani, Anand Raghunathan. 612-617 [doi]
• Architecture synthesis for cost-constrained fault-tolerant flow-based biochipsMorten Chabert Eskesen, Paul Pop, Seetal Potluri. 618-623 [doi]
• Sieve-valve-aware synthesis of flow-based microfluidic biochips considering specific biological execution limitationsMengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann. 624-629 [doi]
• Integrated and real-time quantitative analysis using cyberphysical digital-microfluidic biochipsMohamed Ibrahim, Krishnendu Chakrabarty, Kristin Scott. 630-635 [doi]
• Self-triggered controllers and hard real-time guaranteesAmir Aminifar, Paulo Tabuada, Petru Eles, Zebo Peng. 636-641 [doi]
• A spatio-temporal fractal model for a CPS approach to brain-machine-body interfacesYuankun Xue, Saul Rodriguez, Paul Bogdan. 642-647 [doi]
• Modular code generation for emulating the electrical conduction system of the human heartNathan Allen, Sidharta Andalam, Partha S. Roop, Avinash Malik, Mark Trew, Nitish Patel. 648-653 [doi]
• Resource utilization and Quality-of-Control trade-off for a composable platformJuan Valencia, E. P. van Horssen, Dip Goswami, W. P. M. H. Heemels, Kees G. W. Goossens. 654-659 [doi]
• Inexact designs for approximate low power addition by cell replacementHaider A. F. Almurib, T. Nandha Kumar, Fabrizio Lombardi. 660-665 [doi]
• A general approach for highly defect tolerant Parallel Prefix Adder designSoumya Banerjee, Wenjing Rao. 666-671 [doi]
• Inverters' self-checking monitors for reliable photovoltaic systemsMartin Omaña, A. Fiore, Cecilia Metra. 672-677 [doi]
• EUROSERVER: Share-anything scale-out micro-server designManolis Marazakis, John Goodacre, Didier Fuin, Paul M. Carpenter, John Thomson, Emil Matús, Antimo Bruno, Per Stenström, Jérôme Martin, Yves Durand, Isabelle Dor. 678-683 [doi]
• Energy minimization at all layers of the data center: The ParaDIME projectOscar Palomar, Santhosh Kumar Rethinagiri, Gulay Yalcin, J. Rubén Titos Gil, Pablo Prieto, Emma Torrella, Osman S. Unsal, Adrián Cristal, Pascal Felber, Anita Sobe, Yaroslav Hayduk, Mascha Kurpicz, Christof Fetzer, Thomas Knauth, Malte Schneegaß, Jens Struckmeier, Dragomir Milojevic. 684-689 [doi]
• Rack-scale disaggregated cloud data centers: The dReDBox project visionKostas Katrinis, Dimitris Syrivelis, Dionisios N. Pnevmatikatos, Georgios Zervas, Dimitris Theodoropoulos, Iordanis Koutsopoulos, K. Hasharoni, D. Raho, C. Pinto, F. Espina, Sergio López-Buedo, Q. Chen, Mario Nemirovsky, Damian Roca, H. Klos, T. Berends. 690-695 [doi]
• ECOSCALE: Reconfigurable computing and runtime system for future exascale systemsIakovos Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Dimitrios S. Nikolopoulos, Dirk Koch, John Goodacre, Ioannis Sourdis, Vassilis Papaefstathiou, Marcello Coppola, Manuel Palomino. 696-701 [doi]
• Enabling HPC for QoS-sensitive applications: The MANGO approachJose Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Alessandro Cilardo, William Fornaciari, Ynse Hoornenborg, Mario Kovac, Bruno Maitre, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Fabrice Roudet, Rafael Tornero, Davide Zoni. 702-707 [doi]
• Autotuning and adaptivity approach for energy efficient Exascale HPC systems: The ANTAREX approachCristina Silvano, Giovanni Agosta, Andrea Bartolini, Andrea R. Beccari, Luca Benini, João Bispo, Radim Cmar, João M. P. Cardoso, Carlo Cavazzoni, Jan Martinovic, Gianluca Palermo, Martin Palkovic, Pedro Pinto, Erven Rohou, Nico Sanna, Katerina Slaninová. 708-713 [doi]
• A digital processor architecture for combined EEG/EMG falling risk predictionValerio F. Annese, Marco Crepaldi, Danilo Demarchi, Daniela De Venuto. 714-719 [doi]
• Distributed-neuron-network based machine learning on smart-gateway network towards real-time indoor data analyticsHantao Huang, Yuehua Cai, Hao Yu. 720-725 [doi]
• Touch-based system for beat-to-beat impedance cardiogram acquisition and hemodynamic parameters estimationDionisije Sopic, Srinivasan Murali, Francisco J. Rincón, David Atienza. 726-731 [doi]
• Quantifying the benefits of compressed sensing on a WBSN-based real-time biosignal monitorDaniele Bortolotti, Bojan Milosevic, Andrea Bartolini, Elisabetta Farella, Luca Benini. 732-737 [doi]
• System level synthesis for virtual memory enabled hardware threadsNicolas Estibals, Gaël Deest, Ali Hassan El Moussawi, Steven Derrien. 738-743 [doi]
• Composable, parameterizable templates for high-level synthesisJanarbek Matai, Dajung Lee, Alric Althoff, Ryan Kastner. 744-749 [doi]
• Leveraging power spectral density for scalable system-level accuracy evaluationBenjamin Barrois, Karthick Parashar, Olivier Sentieys. 750-755 [doi]
• Leader: Accelerating ReRAM-based main memory by leveraging access latency discrepancy in crossbar arraysHang Zhang, Nong Xiao, Fang Liu, Zhiguang Chen. 756-761 [doi]
• Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cacheXue Wang, Mengjie Mao, Enes Eken, Wujie Wen, Hai Li, Yiran Chen. 762-767 [doi]
• Exploiting more parallelism from write operations on PCMZheng Li, Fang Wang, Yu Hua, Wei Tong, Jingning Liu, Yu Chen, Dan Feng. 768-773 [doi]
• Dynamic partitioning strategy to enhance symbolic executionBrendan A. Marcellino, Michael S. Hsiao. 774-779 [doi]
• Quantitative timing analysis of UML activity diagrams using statistical model checkingFan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große, Rolf Drechsler. 780-785 [doi]
• Integrating symbolic and statistical methods for testing intelligent systems: Applications to machine learning and computer visionArvind Ramanathan, Laura L. Pullum, Faraz Hussain, Dwaipayan Chakrabarty, Sumit Kumar Jha. 786-791 [doi]
• Path selection and sensor insertion flow for age monitoring in FPGAsMohammad Ebrahimi, Zana Ghaderi, Eli Bozorgzadeh, Zain Navabi. 792-797 [doi]
• Design and evaluation of reliability-oriented task re-mapping in MPSoCs using time-series analysis of intermittent faultsSiva Satyendra Sahoo, Akash Kumar, Bharadwaj Veeravalli. 798-803 [doi]
• Lifetime-aware load distribution policies in multi-core systems: An in-depth analysisCristiana Bolchini, Luca Cassano, Antonio Miele. 804-809 [doi]
• A flexible inexact TMR technique for SRAM-based FPGAsShyamsundar Venkataraman, Rui Santos, Akash Kumar. 810-813 [doi]
• Accurate verification of RC power gridsMohammad Fawaz, Farid N. Najm. 814-817 [doi]
• Security-aware development of cyber-physical systems illustrated with automotive case studyViacheslav Izosimov, Alexandros Asvestopoulos, Oscar Blomkvist, Martin Törngren. 818-821 [doi]
• Online heuristic for the Multi-Objective Generalized traveling salesman problemJoost van Pinxten, Marc Geilen, Twan Basten, Umar Waqas, Lou J. Somers. 822-825 [doi]
• Towards low overhead control flow checking using regular structured controlZhiqi Zhu, Joseph Callenes-Sloan. 826-829 [doi]
• Emulation-based hierarchical fault-injection framework for coarse-to-fine vulnerability analysis of hardware-accelerated approximate algorithmsIoannis Chadjiminas, Ioannis Savva, Christos Kyrkou, Maria K. Michael, Theocharis Theocharides. 830-833 [doi]
• Technology Transfer in computing systems: The TETRACOM approachRainer Leupers. 834-837 [doi]
• Energy vs. reliability trade-offs exploration in biomedical ultra-low power devicesLoris Duch, P. Garcia del Valle, Shrikanth Ganapathy, Andreas Burg, David Atienza. 838-841 [doi]
• A machine learning approach for medication adherence monitoring using body-worn sensorsNiloofar Hezarjaribi, Ramin Fallahzadeh, Hassan Ghasemzadeh. 842-845 [doi]
• Requirements-centric closed-loop validation of implantable cardiac devicesWeiwei Ai, Nitish Patel, Partha S. Roop. 846-849 [doi]
• Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applicationsNan Liu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee, Joseph Sylvester Chang. 850-853 [doi]
• A lifetime-aware runtime mapping approach for many-core systems in the dark silicon eraMohammad Hashem Haghbayan, Antonio Miele, Amir-Mohammad Rahmani, Pasi Liljeberg, Hannu Tenhunen. 854-857 [doi]
• Automotive V2X on phones: Enabling next-generation mobile ITS appsJason H. Gao, Li-Shiuan Peh. 858-863 [doi]
• Collective Knowledge: Towards R&D sustainabilityGrigori Fursin, Anton Lokhmotov, Ed Plowman. 864-869 [doi]
• Lessons learned from the EU project T-CRESTMartin Schoeberl. 870-875 [doi]
• MULTI-POS: Marie Curie network in multi-technology positioningJari Nurmi, Elena Simona Lohan. 876-881 [doi]
• Program transformations in the POLCA projectJan Kuper, Lutz Schubert, Kilian Kempf, Colin W. Glass, Daniel Rubio Bonilla, Manuel Carro. 882-887 [doi]
• Computation and communication challenges to deploy robots in assisted living environmentsGeorgios Keramidas, Christos P. Antonopoulos, Nikolaos S. Voros, Fynn Schwiegelshohn, Philipp Wehner, Jens Rettkowski, Diana Göhringer, Michael Hübner, Stasinos Konstantopoulos, Theodoros Giannakopoulos, Vangelis Karkaletsis, Vaggelis Mariatos. 888-893 [doi]
• ATHENIS_3D: Automotive tested high-voltage and embedded non-volatile integrated SoC platform with 3D technologyE. Wachmann, Sergio Saponara, C. Zambelli, Pierre Tisserand, J. Charbonnier, T. Erlbacher, S. Gruenler, C. Hartler, J. Siegert, Pierre Chassard, D. M. Ton, L. Ferrari, Luca Fanucci. 894-899 [doi]
• Run time interpretation for creating custom acceleratorsSen Ma, Zeyad Aklah, David Andrews. 900-905 [doi]
• A self-adaptive approach to efficiently manage energy and performance in tomorrow's heterogeneous computing systemsE. M. G. Trainiti, Gianluca C. Durelli, Antonio Miele, Cristiana Bolchini, Marco D. Santambrogio. 906-911 [doi]
• Performance-centric scheduling with task migration for a heterogeneous compute node in the data centerAchim Lösch, Tobias Beisel, Tobias Kenter, Christian Plessl, Marco Platzner. 912-917 [doi]
• Adaptive Threshold Non-Pareto Elimination: Re-thinking machine learning for system level design space exploration on FPGAsPingfan Meng, Alric Althoff, Quentin Gautier, Ryan Kastner. 918-923 [doi]
• Monitoring of MTL specifications with IBM's spiking-neuron modelKonstantin Selyunin, Thang Nguyen, Ezio Bartocci, Dejan Nickovic, Radu Grosu. 924-929 [doi]
• Formal probabilistic analysis of distributed resource management schemes in on-chip systemsShafaq Iqtedar, Osman Hasan, Muhammad Shafique, Jörg Henkel. 930-935 [doi]
• An Operating System level data migration scheme in hybrid DRAM-NVM memory architectureReza Salkhordeh, Hossein Asadi. 936-941 [doi]
• Unified DRAM and NVM hybrid buffer cache architecture for reducing journaling overheadZhiyong Zhang, Lei Ju, Zhiping Jia. 942-947 [doi]
• Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter GraphsSaeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler. 948-953 [doi]
• Exploiting resource-constrained parallelism in hard real-time streaming applicationsJelena Spasic, Di Liu, Todor Stefanov. 954-959 [doi]
• Transaction Parameterized Dataflow: A model for context-dependent streaming applicationsXuan Khanh Do, Stéphane Louise, Albert Cohen. 960-965 [doi]
• GLAsT: Learning formal grammars to translate natural language specifications into hardware assertionsChristopher B. Harris, Ian G. Harris. 966-971 [doi]
• Accurate CEGAR-based ATPG in presence of unknown values for large industrial designsKarsten Scheibler, Dominik Erb, Bernd Becker. 972-977 [doi]
• Pre-bond testing of the silicon interposer in 2.5D ICsRan Wang, Zipeng Li, Sukeshwar Kannan, Krishnendu Chakrabarty. 978-983 [doi]
• Improving SRAM test quality by leveraging self-timed circuitsJosef Kinseher, Leonardo Bonet Zordan, Ilia Polian, Andreas Leininger. 984-989 [doi]
• Software security: Vulnerabilities and countermeasures for two attacker modelsFrank Piessens, Ingrid Verbauwhede. 990-999 [doi]
• OLITS: An Ohm's Law-like traffic splitting model based on congestion predictionGaoming Du, Yanghao Ou, Xiangyang Li, Ping Song, Zhonghai Lu, Minglun Gao. 1000-1005 [doi]
• MCAPI-compliant Hardware Buffer Manager mechanism to support communication in multi-core architecturesThiago Raupp da Rosa, Thomas Mesquida, Romain Lemaire, Fabien Clermidy. 1006-1011 [doi]
• Slack-based resource arbitration for real-time Networks-on-ChipAdam Kostrzewa, Selma Saidi, Rolf Ernst. 1012-1017 [doi]
• Challenges of using on-chip performance monitors for process and environmental variation compensationMahroo Zandrahimi, Zaid Al-Ars, Philippe Debaud, Armand Castillejo. 1018-1019 [doi]
• Study of workload impact on BTI HCI induced aging of digital circuitsAjith Sivadasan, Florian Cacho, Sidi Ahmed Benhassain, Vincent Huard, Lorena Anghel. 1020-1021 [doi]
• Fast prototyping platform for navigation systems with sensors fusionCharly Bechara, Karim Ben Chehida, Mickael Guibert, Renaud Schmit, Maria Lepecq, Laurent Soulier, Thomas Dombek, Yann Leclerc. 1022-1023 [doi]
• Precision timed industrial automation systemsMatthew M. Y. Kuo, Sidharta Andalam, Partha S. Roop. 1024-1025 [doi]
• AUTOSAR-based communication coprocessor for automotive ECUsAhmed Hamed, Mona Safar, M. Watheq El-Kharashi, Ashraf Salem. 1026-1027 [doi]
• Mantissa-masking for energy-efficient floating-point LTE uplink MIMO baseband processingDaniel Günther, Tomas Henriksson, Rainer Leupers, Gerd Ascheid. 1028-1029 [doi]
• Optimizing Majority-Inverter Graphs with functional hashingMathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 1030-1035 [doi]
• Resource-aware functional ECO patch generationAn-Che Cheng, Iris Hui-Ru Jiang, Jing-Yang Jou. 1036-1041 [doi]
• Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuitsGang Wu, Chris C. N. Chu. 1042-1047 [doi]
• Formal verification of integer multipliers by combining Gröbner basis with logic reductionAmr A. R. Sayed-Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler. 1048-1053 [doi]
• Root-cause analysis for memory-locked errorsJohn Adler, Djordje Maksimovic, Andreas G. Veneris. 1054-1059 [doi]
• Formal verification of clock domain crossing using gate-level models of metastable flip-flopsGhaith Tarawneh, Andrey Mokhov, Alex Yakovlev. 1060-1065 [doi]
• Response-time analysis of DAG tasks under fixed priority scheduling with limited preemptionsMaria A. Serrano, Alessandra Melani, Marko Bertogna, Eduardo Quiñones. 1066-1071 [doi]
• Speed optimization for tasks with two resourcesAlessandra Melani, Renato Mancuso, Daniel Cullina, Marco Caccamo, Lothar Thiele. 1072-1077 [doi]
• Self-suspension real-time tasks under fixed-relative-deadline fixed-priority schedulingWen-Hung Huang, Jian-Jia Chen. 1078-1083 [doi]
• Thermal-aware dynamic page allocation policy by future access patterns for Hybrid Memory Cube (HMC)Wei-Hen Lo, Kai-zen Liang, TingTing Hwang. 1084-1089 [doi]
• Minimizing peak temperature for pipelined hard real-time systemsLong Cheng, Kai Huang, Gang Chen, Biao Hu, Alois Knoll. 1090-1095 [doi]
• Thermal aware scheduling and mapping of multiphase applications onto chip multiprocessorAryabartta Sahu. 1096-1101 [doi]
• Embedded tutorial: Analog-/mixed-signal verification methods for AMS coverage analysisErich Barke, Andreas Furtig, Georg Glaeser, Christoph Grimm 0001, Lars Hedrich, Stefan Heinen, Eckhard Hennig, Hyun-Sek Lukas Lee, Wolfgang Nebel, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher. 1102-1111 [doi]
• A q-gram birthmarking approach to predicting reusable hardwareKevin Zeng, Peter M. Athanas. 1112-1115 [doi]
• Captopril: Reducing the pressure of bit flips on hot locations in non-volatile main memoriesMajid Jalili 0001, Hamid Sarbazi-Azad. 1116-1119 [doi]
• Handling complex dependencies in system designMischa Moestl, Rolf Ernst. 1120-1123 [doi]
• A synthesis-agnostic behavioral fault model for high gate-level fault coverageAnton Karputkin, Jaan Raik. 1124-1127 [doi]
• Recursive hierarchical DFT methodology with multi-level clock control and scan pattern retargetingDan Trock, Rick Fisette. 1128-1131 [doi]
• Combining graph-based guidance with error effect simulation for efficient safety analysisJo Laufenberg, Sebastian Reiter, Alexander Viehl, Oliver Bringmann, Thomas Kropf, Wolfgang Rosenstiel. 1132-1135 [doi]
• Packet security with path sensitization for NoCsTravis Boraten, Avinash Karanth Kodi. 1136-1139 [doi]
• Synthesis of approximate coders for on-chip interconnects using reversible logicRobert Wille, Oliver Keszocze, Stefan Hillmich, Marcel Walter, Alberto García Ortiz. 1140-1143 [doi]
• Design-synthesis co-optimisation using skewed and tapered gatesAyan Datta, James D. Warnock, Ankur Shukla, Saurabh Gupta, Yiu H. Chan, Karthik Mohan, Charudhattan Nagarajan. 1144-1147 [doi]
• A synthesis-parameter tuning system for autonomous design-space explorationMatthew M. Ziegler, Hung-Yi Liu, George Gristede, Bruce Owens, Ricardo Nigaglioni, Luca P. Carloni. 1148-1151 [doi]
• Unbounded safety verification for hardware using software analyzersRajdeep Mukherjee, Peter Schrammel, Daniel Kroening, Tom Melham. 1152-1155 [doi]
• Verilog2SMV: A tool for word-level verificationAhmed Irfan, Alessandro Cimatti, Alberto Griggio, Marco Roveri, Roberto Sebastiani. 1156-1159 [doi]
• Towards formal verification of real-world SystemC TLM peripheral models - a case studyHoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler. 1160-1163 [doi]
• Frequency scheduling for resilient chip multi-processors operating at Near Threshold VoltageYing Wang, Huawei Li, Xiaowei Li. 1164-1167 [doi]
• A low overhead error confinement method based on application statistical characteristicsZheng Wang, Georgios Karakonstantis, Anupam Chattopadhyay. 1168-1171 [doi]
• SOFIA: Software and control flow integrity architectureRuan de Clercq, Ronald De Keulenaer, Bart Coppens, Bohan Yang 0001, Pieter Maene, Koen De Bosschere, Bart Preneel, Bjorn De Sutter, Ingrid Verbauwhede. 1172-1177 [doi]
• Trust, but verify: Why and how to establish trust in embedded devicesAurélien Francillon. 1178-1182 [doi]
• CrossOver: Clock domain crossing under virtual-channel flow controlMichalis Paschou, Anastasios Psarras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos. 1183-1188 [doi]
• Correct runtime operation for NoCs through adaptive-region protectionRawan Abdel-Khalek, Valeria Bertacco. 1189-1194 [doi]
• Fault-tolerant 3-D network-on-chip design using dynamic link sharingSeyyed Hossein Seyyedaghaei Rezaei, Mehdi Modarressi, Reza Yazdani Aminabadi, Masoud Daneshtalab. 1195-1200 [doi]
• Enabling the heterogeneous accelerator model on ultra-low power microcontroller platformsFrancesco Conti 0001, Daniele Palossi, Andrea Marongiu, Davide Rossi, Luca Benini. 1201-1206 [doi]
• Thermal optimization using adaptive approximate computing for video codingDaniel Palomino, Muhammad Shafique, Altamiro Volcan Susin, Jorg Henkel. 1207-1212 [doi]
• High performance Time-of-Flight and color sensor fusion with image-guided depth super resolutionHannes Plank, Gerald Holweg, Thomas Herndl, Norbert Druml. 1213-1218 [doi]
• Saturated min-sum decoding: An "afterburner" for LDPC decoder hardwareStefan Scholl, Philipp Schläfer, Norbert Wehn. 1219-1224 [doi]
• Utilizing macromodels in floating random walk based capacitance extractionWenjian Yu, Bolong Zhang, Chao Zhang, Haiquan Wang, Luca Daniel. 1225-1230 [doi]
• Variability and statistical analysis flow for dynamic linear systems with large number of inputsA. Lucas Martins, Jorge Fernandez Villena, Luis Miguel Silveira. 1231-1236 [doi]
• Variation-aware near threshold circuit synthesisMohammad Saber Golanbari, Saman Kiamehr, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori. 1237-1242 [doi]
• Buffered compares: Excavating the hidden parallelism inside DRAM architectures with lightweight logicJinho Lee, Jung Ho Ahn, Kiyoung Choi. 1243-1248 [doi]
• Large vector extensions inside the HMCMarco Antonio Zanata Alves, Matthias Diener, Paulo C. Santos, Luigi Carro. 1249-1254 [doi]
• minFlash: A minimalistic clustered flash arrayMing Liu, Sang-Woo Jun, Sungjin Lee, Jamey Hicks, Arvind. 1255-1260 [doi]
• An optimized task-based runtime system for resource-constrained parallel acceleratorsDaniele Cesarini, Andrea Marongiu, Luca Benini. 1261-1266 [doi]
• A fine-grained performance model for GPU architecturesNicola Bombieri, Federico Busato, Franco Fummi. 1267-1272 [doi]
• Critical points based register-concurrency autotuning for GPUsAng Li, Shuaiwen Leon Song, Akash Kumar, Eddy Z. Zhang, Daniel G. Chavarria-Miranda, Henk Corporaal. 1273-1278 [doi]
• Grater: An approximation workflow for exploiting data-level parallelism in FPGA accelerationAtieh Lotfi, Abbas Rahimi, Amir Yazdanbakhsh, Hadi Esmaeilzadeh, Rajesh K. Gupta. 1279-1284 [doi]
• A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizationsWujie Wen, Mengjie Mao, Hai Li, Yiran Chen, Yukui Pei, Ning Ge. 1285-1290 [doi]
• Thermal-aware TSV repair for electromigration in 3D ICsShengcheng Wang, Mehdi Baradaran Tahoori, Krishnendu Chakrabarty. 1291-1296 [doi]
• Electrothermal simulation of bonding wire degradation under uncertain geometriesThorben Casper, Herbert De Gersem, Renaud Gillon, Tomas Gotthans, Tomas Kratochvil, Peter Meuris, Sebastian Schöps. 1297-1302 [doi]
• Security in industrie 4.0 - challenges and solutions for the fourth industrial revolutionMichael Waidner, Michael Kasper. 1303-1308 [doi]
• Cross-layer floorplan optimization for silicon photonic NoCs in many-core systemsAyse Kivilcim Coskun, Anjun Gu, Warren Jin, Ajay Joshi, Andrew B. Kahng, Jonathan Klamkin, Yenai Ma, John Recchio, Vaishnav Srinivas, Tiansheng Zhang. 1309-1314 [doi]
• Adaptive multi-voltage scaling in wireless NoC for high performance low power applicationsHemanta Kumar Mondal, Sri Harsha Gade, Raghav Kishore, Sujay Deb. 1315-1320 [doi]
• Energy efficient transceiver in wireless Network on Chip architecturesVincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi, Davide Patti. 1321-1326 [doi]
• Resistive configurable associative memory for approximate computingMohsen Imani, Abbas Rahimi, Tajana S. Rosing. 1327-1332 [doi]
• Exploiting CPU-load and data correlations in multi-objective VM placement for geo-distributed data centersAli Pahlevan, Pablo Garcia Del Valle, David Atienza. 1333-1338 [doi]
• Energy efficiency in cloud-based MapReduce applications through better performance estimationSeyed Morteza Nabavinejad, Maziar Goudarzi. 1339-1344 [doi]
• Unsupervised power modeling of co-allocated workloads for energy efficiency in data centersJuan C. Salinas Hilburg, Marina Zapater, José Luis Risco-Martín, José Manuel Moya, José Luis Ayala. 1345-1350 [doi]
• Automated test generation for Debugging arithmetic circuitsFarimah Farahmandi, Prabhat Mishra. 1351-1356 [doi]
• MCXplore: An automated framework for validating memory controller designsMohamed Hassan, Hiren D. Patel. 1357-1362 [doi]
• EAST: Efficient Assertion Simulation techniquesDebjyoti Bhattacharjee, Soumi Chattopadhyay, Ansuman Banerjee. 1363-1368 [doi]
• Combinational trace signal selection with improved state restoration for post-silicon debugSiamack BeigMohammadi, Bijan Alizadeh. 1369-1374 [doi]
• Practical way halting by speculatively accessing halt tagsDaniel Moreau, Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors. 1375-1380 [doi]
• Lazy Pipelines: Enhancing quality in approximate computingG. Tziantzioulis, A. M. Gok, S. M. Faisal, Nikolaos Hardavellas, Seda Ogrenci Memik, Srinivasan Parthsarathy. 1381-1386 [doi]
• High-efficiency logarithmic number unit design based on an improved cotransformation schemeYouri Popoff, Florian Scheidegger, Michael Schaffner, Michael Gautschi, Frank K. Gürkaynak, Luca Benini. 1387-1392 [doi]
• Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute arrayAtul Rahman, Jongeun Lee, Kiyoung Choi. 1393-1398 [doi]
• Energy efficient video fusion with heterogeneous CPU-FPGA devicesPeng Sun, Alin Achim, Ian Hasler, Paul R. Hill, José Núñez-Yáñez. 1399-1404 [doi]
• Highly efficient reconfigurable parallel graph cuts for embedded visionAntonis Nikitakis, Ioannis Papaefstathiou. 1405-1410 [doi]
• Pareto front analog layout placement using Satisfiability Modulo TheoriesSherif M. Saif, Mohamed Dessouky, M. Watheq El-Kharashi, Hazem M. Abbas, Salwa M. Nassar. 1411-1416 [doi]
• Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation dataBo Peng, Fan Yang, Changhao Yan, Xuan Zeng, Dian Zhou. 1417-1422 [doi]
• PolyGP: Improving GP-based analog optimization through accurate high-order monomials and semidefinite relaxationYe Wang, Constantine Caramanis, Michael Orshansky. 1423-1428 [doi]
• Reliability and performance trade-offs for 3D NoC-enabled multicore chipsSourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty. 1429-1432 [doi]
• Memory-access aware DVFS for network-on-chip in CMPsYuan Yao, Zhonghai Lu. 1433-1436 [doi]
• A dynamically reconfigurable ECC decoder architectureAwais Sani, Philippe Coussy, Cyrille Chavet. 1437-1440 [doi]
• Resistive Bloom filters: From approximate membership to approximate computing with bounded errorsVahideh Akhlaghi, Abbas Rahimi, Rajesh K. Gupta. 1441-1444 [doi]
• Real-time system-level implementation of a telepresence robot using an embedded GPU platformMuhammad Teguh Satria, Swathi T. Gurumani, Wang Zheng, Keng-Peng Tee, Augustine Koh, Pan Yu, Kyle Rupnow, Deming Chen. 1445-1448 [doi]
• Exploring specialized near-memory processing for data intensive operationsSalessawi Ferede Yitbarek, Tao Yang, Reetuparna Das, Todd M. Austin. 1449-1452 [doi]
• Matlab to C compilation targeting Application Specific Instruction Set ProcessorsIoannis Latifis, Karthick Parashar, Grigoris Dimitroulakos, Hans Cappelle, Christakis Lezos, Konstantinos Masselos, Francky Catthoor. 1453-1456 [doi]
• Sampling-based buffer insertion for post-silicon yield improvement under process variabilityGrace Li Zhang, Bing Li, Ulf Schlichtmann. 1457-1460 [doi]
• PRADA: Combating voltage noise in the NoC power supply through flow-control and routing algorithmsPrabal Basu, Rajesh JayashankaraShridevi, Koushik Chakraborty, Sanghamitra Roy. 1461-1464 [doi]
• A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cacheKyungsu Kang, Sangho Park, Jong-Bae Lee, Luca Benini, Giovanni De Micheli. 1465-1468 [doi]
• Power-efficient load-balancing on heterogeneous computing platformsMuhammad Usman Karim Khan, Muhammad Shafique, Apratim Gupta, Thomas Schumann, Jörg Henkel. 1469-1472 [doi]
• Topaz: Mining high-level safety properties from logic simulation tracesAhmed Nassar, Fadi J. Kurdahi, Salam R. Zantout. 1473-1476 [doi]
• Exploiting transaction level models for observability-aware post-silicon test generationFarimah Farahmandi, Prabhat Mishra, Sandip Ray. 1477-1480 [doi]
• SEERAD: A high speed yet energy-efficient rounding-based approximate dividerReza Zendegani, Mehdi Kamal, Arash Fayyazi, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram. 1481-1484 [doi]
• Improving performance guarantees in wormhole mesh NoC designsMilos Panic, Carles Hernández, Jaume Abella, Antoni Roca, Eduardo Quiñones, Francisco J. Cazorla. 1485-1488 [doi]
• A Data Layout Transformation (DLT) accelerator: Architectural support for data movement optimization in accelerated-centric heterogeneous systemsTung Thanh Hoang, Amirali Shambayati, Andrew A. Chien. 1489-1492 [doi]
• Ouessant: Flexible integration of dedicated coprocessors in Systems on ChipPierre-Henri Horrein, Philip-Dylan Gleonec, Erwan Libessart, Andre Lalevee, Matthieu Arzel. 1493-1496 [doi]
• A novel background subtraction scheme for in-camera acceleration in thermal imageryAntonis Nikitakis, Ioannis Papaefstathiou, Konstantinos Makantasis, Anastasios D. Doulamis. 1497-1500 [doi]
• Radiation-hardened DSP configurations for implementing arithmetic functions on FPGAMarcos Sanchez-Elez, Inmaculada Pardines, Felipe Serrano, Hortensia Mecha. 1501-1504 [doi]
• Configuration prefetching and reuse for preemptive hardware multitasking on partially reconfigurable FPGAsAurelio Morales-Villanueva, Rohit Kumar, Ann Gordon-Ross. 1505-1508 [doi]
• Analog circuit topological feature extraction with unsupervised learning of new sub-structuresHao Li, Fanshu Jiao, Alex Doboli. 1509-1512 [doi]
• Design automation tasks scheduling for enhanced parallel execution of a state-of-the-art layout-aware sizing approachDavid Neves, Ricardo Martins, Nuno C. Lourenço, Nuno Horta. 1513-1516 [doi]
• A design method for remote integrity checking of complex PCBsAydin Aysu, Shravya Gaddam, Harsha Mandadi, Carol Pinto, Luke Wegryn, Patrick Schaumont. 1517-1522 [doi]
• Quantifying hardware security using joint information flow analysisRyan Kastner, Wei Hu, Alric Althoff. 1523-1528 [doi]
• Instruction Set Extensions for secure applicationsFrancesco Regazzoni, Paolo Ienne. 1529-1534 [doi]
• Hardware security through chain assuranceYaw Obeng, Colm Nolan, David Brown. 1535-1537 [doi]
• Leverage Emerging Technologies For DPA-Resilient Block Cipher DesignYu Bi, Kaveh Shamsi, Jiann-shiun Yuan, François-Xavier Standaert, Yier Jin. 1538-1543 [doi]
• Using emerging technologies for hardware security beyond PUFsAn Chen, Xiaobo Sharon Hu, Yier Jin, Michael T. Niemier, Xunzhao Yin. 1544-1549 [doi]
• Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracyJason Helge Anderson, Yuko Hara-Azumi, Shigeru Yamashita. 1550-1555 [doi]
• Efficient program tracing and monitoring through power consumption - with a little help from the compilerCarlos Moreno, Sean Kauffman, Sebastian Fischmeister. 1556-1561 [doi]
• FLIC: Fast, lightweight checkpointing for mobile virtualization using NVRAMKan Zhong, Duo Liu, Liang Liang, Linbo Long, Yi Lin, Zili Shao. 1562-1567 [doi]
• PAIS: Parallelization aware instruction scheduling for improving soft-error reliability of GPU-based systemsHaeseung Lee, Hsinchung Chen, Mohammad Abdullah Al Faruque. 1568-1573 [doi]
• Accelerating source-level timing simulationSimon Schulz, Oliver Bringmann. 1574-1579 [doi]
• Sparsity-oriented sparse solver design for circuit simulationXiaoming Chen, Lixue Xia, Yu Wang, Huazhong Yang. 1580-1585 [doi]
• Integration of mixed-signal components into virtual platforms for holistic simulation of smart systemsEnrico Fraccaroli, Michele Lora, Sara Vinco, Davide Quaglia, Franco Fummi. 1586-1591 [doi]
• Decision tree generation for decoding irregular instructionsKatsumi Okuda, Haruhiko Takeyama. 1592-1597 [doi]
• A reconfigurable heterogeneous multicore with a homogeneous ISAJeckson Dellagostin Souza, Luigi Carro, Mateus Beck Rutzig, Antonio Carlos Schneider Beck. 1598-1603 [doi]
• The neuro vector engine: Flexibility to improve convolutional net efficiency for wearable visionMaurice Peemen, Runbin Shi, Sohan Lal, Ben H. H. Juurlink, Bart Mesman, Henk Corporaal. 1604-1609 [doi]
• Improving scalability of CMPs with dense ACCs coverageNasibeh Teimouri, Hamed Tabkhi, Gunar Schirner. 1610-1615 [doi]
• Hardware accelerator for analytics of sparse dataEriko Nurvitadhi, Asit Mishra, Yu Wang, Ganesh Venkatesh, Debbie Marr. 1616-1621 [doi]
• Securing the cloud with reconfigurable computing: An FPGA accelerator for homomorphic encryptionAlessandro Cilardo, Domenico Argenziano. 1622-1627 [doi]
• Throughput oriented FPGA overlays using DSP blocksAbhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy. 1628-1633 [doi]
• Run-time phase prediction for a reconfigurable VLIW processorQi Guo, Anderson Luiz Sartor, Anthony Brandon, Antonio C. S. Beck, Xuehai Zhou, Stephan Wong. 1634-1639 [doi]
• ADVOCAT: Automated deadlock verification for on-chip cache coherence and interconnectsFreek Verbeek, Pooria M. Yaghini, Ashkan Eghbal, Nader Bagherzadeh. 1640-1645 [doi]
• Guarantees for runnable entities with heterogeneous real-time requirementsLeonie Ahrendts, Zain Alabedin Haj Hammadeh, Rolf Ernst. 1646-1651 [doi]
• Validating scheduling transformation for behavioral synthesisZhenkun Yang, Kecheng Hao, Kai Cong, Li Lei, Sandip Ray, Fei Xie. 1652-1657 [doi]