Abstract is missing.
- Framework for quantifying and managing accuracy in stochastic circuit designFlorian Neugebauer, Ilia Polian, John P. Hayes. 1-6 [doi]
- Energy-efficient approximate multiplier design using bit significance-driven logic compressionIssa Qiqieh, Rishad A. Shafik, Ghaith Tarawneh, Danil Sokolov, Alex Yakovlev. 7-12 [doi]
- Energy-efficient hybrid stochastic-binary neural networks for near-sensor computingVincent T. Lee, Armin Alaghi, John P. Hayes, Visvesh Sathe, Luis Ceze. 13-18 [doi]
- Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbarLerong Chen, Jiawen Li, Yiran Chen, Qiuping Deng, Jiyuan Shen, Xiaoyao Liang, Li Jiang. 19-24 [doi]
- Shared last-level cache management for GPGPUs with hybrid main memoryGuan Wang, Xiaojun Cai, Lei Ju, Chuanqi Zang, Mengying Zhao, Zhiping Jia. 25-30 [doi]
- Effective cache bank placement for GPUsMohammad Sadrosadati, Amirhossein Mirhosseini, Shahin Roozkhosh, Hazhir Bakhishi, Hamid Sarbazi-Azad. 31-36 [doi]
- Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-coresArun Subramaniyan 0001, Semeen Rehman, Muhammad Shafique, Akash Kumar 0001, Jörg Henkel. 37-42 [doi]
- GATSim: Abstract timing simulation of GPUsKishore Punniyamurthy, Behzad Boroujerdian, Andreas Gerstlauer. 43-48 [doi]
- MeSAP: A fast analytic power model for DRAM memoriesSandeep Poddar, Rik Jongerius, Leandro Fiorin, Giovanni Mariani, Gero Dittmann, Andreea Anghel, Henk Corporaal. 49-54 [doi]
- AFEC: An analytical framework for evaluating cache performance in out-of-order processorsKecheng Ji, Ming Ling, Qin Wang, Longxing Shi, Jianping Pan. 55-60 [doi]
- Reliability assessment of fault tolerant routing algorithms in networks-on-chip: An analytic approachSadia Moriam, Gerhard P. Fettweis. 61-66 [doi]
- Online monitoring and adaptive routing for aging mitigation in NoCsZana Ghaderi, Ayed Alqahtani, Nader Bagherzadeh. 67-72 [doi]
- eBSP: Managing NoC traffic for BSP workloads on the 16-core Adapteva Epiphany-III processorSiddhartha, Nachiket Kapre. 73-78 [doi]
- On the limits of machine learning-based test: A calibrated mixed-signal system case studyManuel J. Barragan, Gildas Léger, Antonio J. Ginés, Eduardo J. Peralías, A. Rueda. 79-84 [doi]
- An extension of Cohn's sensitivity theorem to mismatch analysis of 1-port resistor networksSebastien Cliquennois. 85-90 [doi]
- Testing microfluidic Fully Programmable Valve Arrays (FPVAs)Chunfeng Liu, Bing Li, Bhargab B. Bhattacharya, Krishnendu Chakrabarty, Tsung-Yi Ho, Ulf Schlichtmann. 91-96 [doi]
- HARPA: Tackling physically induced performance variabilityNikolaos Zompakis, Michail Noltsis, Lorena Ndreu, Zacharias Hadjilambrou, Panayiotis Englezakis, Panagiota Nikolaou, Antoni Portero, Simone Libutti, Giuseppe Massari, Federico Sassi, Alessandro Bacchini, Chrysostomos Nicopoulos, Yiannakis Sazeides, Radim Vavrík, Martin Golasowski, Jiri Sevcík, Vít Vondrák, Francky Catthoor, William Fornaciari, Dimitrios Soudris. 97-102 [doi]
- Dynamic software randomisation: Lessons learnec from an aerospace case studyFabrice Cros, Leonidas Kosmidis, Franck Wartel, David Morales, Jaume Abella, Ian Broster, Francisco J. Cazorla. 103-108 [doi]
- READEX: Linking two ends of the computing continuum to improve energy-efficiency in dynamic applicationsPer Gunnar Kjeldsberg, Andreas Gocht, Michael Gerndt, Lubomir Riha, Joseph Schuchart, Umbreen Sabir Mian. 109-114 [doi]
- BASTION: Board and SoC test instrumentation for ageing and no failure foundArtur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans G. Kerkhoff, Rene Krenz-Baath, Piet Engelke. 115-120 [doi]
- RETHINK big: European roadmap for hardware anc networking optimizations for big dataGina Alioto, Paul Carpenter, Adrián Cristal, Osman S. Unsal, Marcus Leich, Christophe Avare. 121-126 [doi]
- Energy-quality scalable adaptive VLSI circuits and systems beyond approximate computingMassimo Alioto. 127-132 [doi]
- Beyond-CMOS non-Boolean logic benchmarking: Insights and future directionsChenyun Pan, Azad Naeemi. 133-138 [doi]
- Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspectiveHsin-Pai Cheng, Wei Wen, Chunpeng Wu, Sicheng Li, Hai Helen Li, Yiran Chen. 139-144 [doi]
- Cellular neural network friendly convolutional neural networks - CNNs with CNNsAndrás Horváth, Michael Hillmer, Qiuwen Lou, Xiaobo Sharon Hu, Michael T. Niemier. 145-150 [doi]
- Algebraic fault analysis of SHA-3Pei Luo, Konstantinos Athanasiou, Yunsi Fei, Thomas Wahl. 151-156 [doi]
- Evaluating coherence-exploiting hardware TrojanMinsu Kim, Sunhee Kong, Boeui Hong, Lei Xu, Weidong Shi, Taeweon Suh. 157-162 [doi]
- Hardware Trojan detection based on correlated path delays in defiance of variations with spatial correlationsFatma Nur Esirci, Alp Arslan Bayrakci. 163-168 [doi]
- Malware detection using machine learning based analysis of virtual memory access patternsZhixing Xu, Sayak Ray, Pramod Subramanyan, Sharad Malik. 169-174 [doi]
- Optimizing temperature guardbandsHussam Amrouch, Behnam Khaleghi, Jörg Henkel. 175-180 [doi]
- The hidden cost of functional approximation against careful data sizing - A case studyBenjamin Barrois, Olivier Sentieys, Daniel Ménard. 181-186 [doi]
- High-level synthesis of approximate hardware under joint precision and voltage scalingSeogoo Lee, Lizy K. John, Andreas Gerstlauer. 187-192 [doi]
- Approximate computing for spiking neural networksSanchari Sen, Swagath Venkataramani, Anand Raghunathan. 193-198 [doi]
- Adaptive weight compression for memory-efficient neural networksJong Hwan Ko, Duckhwan Kim 0001, Taesik Na, Jaeha Kung, Saibal Mukhopadhyay. 199-204 [doi]
- Real-time anomaly detection for streaming data using burst code on a neurosynaptic processorQiuwen Chen, Qinru Qiu. 205-207 [doi]
- Fast, low power evaluation of elementary functions using radial basis function networksParami Wijesinghe, Chamika M. Liyanagedera, Kaushik Roy 0001. 208-213 [doi]
- Charka: A reliability-aware test scheme for diagnosis of channel shorts beyond mesh NoCsBiswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas. 214-219 [doi]
- Recovery-aware proactive TSV repair for electromigration in 3D ICsShengcheng Wang, Hengyang Zhao, Sheldon X.-D. Tan, Mehdi Baradaran Tahoori. 220-225 [doi]
- Near-optimal metastability-containing sorting networksJohannes Bund, Christoph Lenzen, Moti Medina. 226-231 [doi]
- The concept of unschedulability core for optimizing priority assignment in real-time systemsYecheng Zhao, Haibo Zeng. 232-237 [doi]
- Utilization difference based partitioned scheduling of mixed-criticality systemsSaravanan Ramanathan, Arvind Easwaran. 238-243 [doi]
- Schedulability using native non-preemptive groups on an AUTOSAR/OSEK platform with cachesLeo Hatvani, Reinder J. Bril, Sebastian Altmeyer. 244-249 [doi]
- Structural design optimization for deep convolutional neural networks using stochastic computingZhe Li, Ao Ren, Ji Li, Qinru Qiu, Bo Yuan, Jeffrey Draper, Yanzhi Wang. 250-253 [doi]
- ApproxQA: A unified quality assurance framework for approximate computingTing Wang, Qian Zhang, Qiang Xu. 254-257 [doi]
- EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methodsVojtech Mrazek, Radek Hrbacek, Zdenek Vasícek, Lukás Sekanina. 258-261 [doi]
- Droop mitigating last level cache architecture for STTRAMRadha Krishna Aluru, Swaroop Ghosh. 262-265 [doi]
- Modeling instruction cache and instruction buffer for performance estimation of VLIW architectures using native simulationOmayma Matoussi, Frédéric Pétrot. 266-269 [doi]
- Analog fault testing through abstractionEnrico Fraccaroli, Franco Fummi. 270-273 [doi]
- BISCC: Efficient pre through post silicon validation of mixed-signal/RF systems using built in state consistency checkingSabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee. 274-277 [doi]
- Computing with nano-crossbar arrays: Logic synthesis and fault toleranceMustafa Altun, Valentina Ciriani, Mehdi Baradaran Tahoori. 278-281 [doi]
- SecureCloud: Secure big data processing in untrusted cloudsFlorian Kelbert, Franz Gregor, Rafael Pires, Stefan Köpsell, Marcelo Pasin, Aurelien Havet, Valerio Schiavoni, Pascal Felber, Christof Fetzer, Peter R. Pietzuch. 282-285 [doi]
- WCET-aware parallelization of model-based applications for multi-cores: The ARGO approachSteven Derrien, Isabelle Puaut, Panayiotis Alefragis, Marcus Bednara, Harald Bucher, Clement David, Yann Debray, Umut Durak, Imen Fassi, Christian Ferdinand, Damien Hardy, Angeliki Kritikakou, Gerard K. Rauwerda, Simon Reder, Martin Sicks, Timo Stripf, Kim Sunesen, Timon D. ter Braak, Nikolaos Voros, Jürgen Becker. 286-289 [doi]
- Exploring the unknown through successive generations of low power and low resource versatile agentsMartin Andraud, Gönenç Berkol, Jaro De Roose, Santosh Gannavarapu, Haoming Xin, Eugenio Cantatore, Pieter J. A. Harpe, Marian Verhelst, Peter G. M. Baltus. 290-293 [doi]
- Power profiling of microcontroller's instruction set for runtime hardware Trojans detection without golden circuit modelsFaiq Khalid Lodhi, Syed Rafay Hasan, Osman Hasan, Falah R. Awwad. 294-297 [doi]
- Accounting for systematic errors in approximate computingMartin Bruestel, Akash Kumar 0001. 298-301 [doi]
- Gaussian mixture error estimation for approximate circuitsAmin Ghasemazar, Mieszko Lis. 302-305 [doi]
- Enhancing symbolic system synthesis through ASPmT with partial assignment evaluationKai Neubauer, Philipp Wanko, Torsten Schaub, Christian Haubelt. 306-309 [doi]
- 3DFAR: A three-dimensional fabric for reliable multi-core processorsJavad Bagherzadeh, Valeria Bertacco. 310-313 [doi]
- Evaluating impact of human errors on the availability of data storage systemsMostafa Kishani, Reza Eftekhari, Hossein Asadi. 314-317 [doi]
- GPUguard: Towards supporting a predictable execution model for heterogeneous SoCBjörn Forsberg, Andrea Marongiu, Luca Benini. 318-321 [doi]
- A non-intrusive, operating system independent spinlock profiler for embedded multicore systemsLin Li, Philipp Wagner 0001, Albrecht Mayer, Thomas Wild, Andreas Herkersdorf. 322-325 [doi]
- Energy-performance optimized design of silicon photonic interconnection networks for high-performance computingMeisam Bahadori, Sébastien Rumley, Robert P. Polster, Alexander Gazman, Matt Traverso, Mark Webster, Kaushik Patel, Keren Bergman. 326-331 [doi]
- Rapid growth of IP traffic is driving adoption of silicon photonics in data centersKaushik Patel. 332-335 [doi]
- Generation of complex quantum states via integrated frequency combsChristian Reimer, Michael Kues, Piotr Roztocki, Benjamin Wetzel, Brent E. Little, Sai T. Chu, Lucia Caspani, David J. Moss, Roberto Morandotti. 336-337 [doi]
- Exploiting transistor-level reconfiguration to optimize combinational circuitsMichael Raitza, Akash Kumar 0001, Marcus Völp, Dennis Walter, Jens Trommer, Thomas Mikolajick, Walter M. Weber. 338-343 [doi]
- Automatic place-and-route of emerging LED-driven wires within a monolithically-integrated CMOS-III-V processTushar Krishna, Arya Balachandran, Siau Ben Chiah, Li Zhang, Bing Wang, Cong Wang, Kenneth Eng-Kian Lee, Jürgen Michel, Li-Shiuan Peh. 344-349 [doi]
- A tunable magnetic skyrmion neuron cluster for energy efficient artificial neural networkZhezhi He, Deliang Fan. 350-355 [doi]
- STAxCache: An approximate, energy efficient STT-MRAM cacheAshish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy 0001, Anand Raghunathan. 356-361 [doi]
- Rethinking on-chip DRAM cache for simultaneous performance and energy optimizationFazal Hameed, Jerónimo Castrillón. 362-367 [doi]
- An energy-efficient memory hierarchy for multi-issue processorsTiago T. Jost, Gabriel L. Nazar, Luigi Carro. 368-373 [doi]
- Mapping granularity adaptive FTL based on flash page re-programmingYazhi Feng, Dan Feng, Chenye Yu, Wei Tong, Jingning Liu. 374-379 [doi]
- Data flow testing for virtual prototypesMuhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler. 380-385 [doi]
- MINIME-validator: Validating hardware with synthetic parallel testcasesAlper Sen 0001, Etem Deniz, Brian Kahne. 386-391 [doi]
- Cost-effective analysis of post-silicon functional coverage eventsFarimah Farahmandi, Ronny Morad, Avi Ziv, Ziv Nevo, Prabhat Mishra. 392-397 [doi]
- Towards exascale computing with heterogeneous architecturesKenneth O'Brien, Lorenzo Di Tucci, Gianluca Durelli, Michaela Blott. 398-403 [doi]
- From exaflop to exaflowTobias Becker, Pavel Burovskiy, Anna Maria Nestorov, Hristina Palikareva, Enrico Reggiani, Georgi Gaydadjiev. 404-409 [doi]
- Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA projectMarco Rabozzi, Giuseppe Natale, Emanuele Del Sozzo, Alberto Scolari, L. Stornaiuolo, Marco D. Santambrogio. 410-415 [doi]
- An open reconfigurable research platform as stepping stone to exascale high-performance computingDirk Stroobandt, Catalin Bogdan Ciobanu, Marco D. Santambrogio, Gabriel Figueiredo, Andreas Brokalakis, Dionisios N. Pnevmatikatos, Michael Hübner, Tobias Becker, Alex J. W. Thom. 416-421 [doi]
- Fast and waveform-accurate hazard-aware SAT-based TSOF ATPGJan Burchard, Dominik Erb, Adit D. Singh, Sudhakar M. Reddy, Bernd Becker 0001. 422-427 [doi]
- Fault diagnosis of arbiter physical unclonable functionJing Ye, Qingli Quo, Yu Hu, Xiaowei Li 0001. 428-433 [doi]
- FPGA-based failure mode testing and analysis for MLC NAND flash memoryMeng Zhang, Fei Wu, He Huang, Qian Xia, Jian Zhou, Changsheng Xie. 434-439 [doi]
- Robust neuromorphic computing in the presence of process variationAli BanaGozar, Mohammad Ali Maleki, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram. 440-445 [doi]
- An on-line framework for improving reliability of real-time systems on "big-little" type MPSoCsYue Ma, Thidapat Chantem, Robert P. Dick, Shige Wang, Xiaobo Sharon Hu. 446-451 [doi]
- Application performance improvement by exploiting process variability on FPGA devicesKonstantinos Maragos, George Lentaris, Dimitrios Soudris, Kostas Siozios, Vasilis F. Pavlidis. 452-457 [doi]
- Make it reversible: Efficient embedding of non-reversible functionsAlwin Zulehner, Robert Wille. 458-463 [doi]
- QX: A high-performance quantum computer simulation platformNader Khammassi, I. Ashraf, X. Fu, Carmen G. Almudéver, Koen Bertels. 464-469 [doi]
- Design automation and design space exploration for quantum computersMathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli. 470-475 [doi]
- Pushing the limits of voltage over-scaling for error-resilient applicationsRengarajan Ragavan, Benjamin Barrois, Cedric Killian, Olivier Sentieys. 476-481 [doi]
- Combining structural and timing errors in overclocked inexact speculative addersXun Jiao, Vincent Camus, Mattia Cacciotti, Yu Jiang, Christian Enz, Rajesh K. Gupta. 482-487 [doi]
- DVAFS: Trading computational accuracy for energy through dynamic-voltage-accuracy-frequency-scalingBert Moons, Roel Uytterhoeven, Wim Dehaene, Marian Verhelst. 488-493 [doi]
- Exploiting computation skip to reduce energy consumption by approximate computing, an HEVC encoder case studyAlexandre Mercat, Justine Bonnot, Maxime Pelcat, Wassim Hamidouche, Daniel Ménard. 494-499 [doi]
- Location detection for navigation using IMUs with a map through coarse-grained machine learningE. J. Jose Gonzalez, Chen Luo, Anshumali Shrivastava, Krishna Palem, Yongshik Moon, Soonhyun Noh, Daedong Park, Seongsoo Hong. 500-505 [doi]
- Performance impacts and limitations of hardware memory access trace collectionNicholas C. Doyle, Eric Matthews, Graham M. Holland, Alexandra Fedorova, Lesley Shannon. 506-511 [doi]
- Context-sensitive timing automata for fast source level simulationSebastian Ottlik, Christoph Gerum, Alexander Viehl, Wolfgang Rosenstiel, Oliver Bringmann. 512-517 [doi]
- MARS: A flexible real-time streaming platform for testing automation systemsRaphael Eidenbenz, Alexandra Moga, Thanikesavan Sivanthi, Carsten Franke. 518-523 [doi]
- SERD: A simulation framework for estimation of system level reliability degradationSaurav Kumar Ghosh, Soumyajit Dey. 524-529 [doi]
- Magnetic tunnel junction enabled all-spin stochastic spiking neural networkGopalakrishnan Srinivasan, Abhronil Sengupta, Kaushik Roy 0001. 530-535 [doi]
- Embedded systems to high performance computing using STT-MRAMSophiane Senni, Thibaud Delobelle, Odilia Coi, Pierre-Yves Peneau, Lionel Torres, Abdoulaye Gamatié, Pascal Benoit, Gilles Sassatelli. 536-541 [doi]
- Voltage-controlled MRAM for working memory: Perspectives and challengesWang Kang, Liang Chang, Youguang Zhang, Weisheng Zhao. 542-547 [doi]
- Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processorTakahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui. 548-553 [doi]
- Opportunistic write for fast and reliable STT-MRAMNour Sayed, Mojtaba Ebrahimi, Rajendra Bishnoi, Mehdi Baradaran Tahoori. 554-559 [doi]
- Fault clustering technique for 3D memory BISRTianjian Li, Yan Han, Xiaoyao Liang, Hsien-Hsin S. Lee, Li Jiang. 560-565 [doi]
- Architectural evaluations on TSV redundancy for reliability enhancementYen-Hao Chen, Chien-Pang Chiu, Russell Barnes, TingTing Hwang. 566-571 [doi]
- Reusing trace buffers to enhance cache performanceNeetu Jindal, Preeti Ranjan Panda, Smruti R. Sarangi. 572-577 [doi]
- Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compressionSebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler. 578-583 [doi]
- Bounding deadline misses in weakly-hard real-time systems with task dependenciesZain Alabedin Haj Hammadeh, Rolf Ernst, Sophie Quinton, Rafik Henia, Laurent Rioux. 584-589 [doi]
- Real-time communication analysis for Networks-on-Chip with backpressureSebastian Tobuschat, Rolf Ernst. 590-595 [doi]
- Probabilistic schedulability analysis for fixed priority mixed criticality real-time systemsYasmina Abdeddaïm, Dorin Maxim. 596-601 [doi]
- Compact modeling and circuit-level simulation of silicon nanophotonic interconnectsRui Wu, Yuyang Wang, Zeyu Zhang, Chong Zhang, Clint L. Schow, John E. Bowers, Kwang-Ting Cheng. 602-605 [doi]
- A true random number generator based on parallel STT-MTJsYuanzhuo Qu, Jie Han, Bruce F. Cockburn, Witold Pedrycz, Yue Zhang, Weisheng Zhao. 606-609 [doi]
- Enabling area efficient RF ICs through monolithic 3D integrationPanagiotis Chaourani, Per-Erik Hellstrcom, Saul Rodriguez Duenas, Raul Onet, Ana Rusu. 610-613 [doi]
- Reconfigurable threshold logic gates using optoelectronic capacitorsRagh Kuttappa, Lunal Khuon, Bahram Nabet, Baris Taskin. 614-617 [doi]
- i-BEP: A non-redundant and high-concurrency memory persistency modelYuanchao Xu, Zeyi Hou, Junfeng Yan, Lu Yang, Hu Wan. 618-621 [doi]
- SPMS: Strand based persistent memory systemShuo Li, Peng Wang, Nong Xiao, Guangyu Sun, Fang Liu. 622-625 [doi]
- Architecting high-speed command schedulers for open-row real-time SDRAM controllersLeonardo Ecco, Rolf Ernst. 626-629 [doi]
- Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specificationsMehran Goli, Jannis Stoppe, Rolf Drechsler. 630-633 [doi]
- Head-mounted sensors and wearable computing for automatic tunnel vision assessmentYuchao Ma, Hassan Ghasemzadeh. 634-637 [doi]
- RetroDMR: Troubleshooting non-deterministic faults with retrospective DMRTing Wang, Yannan Liu, Qiang Xu, Zhaobo Zhang, Zhiyuan Wang, Xinli Gu. 638-641 [doi]
- Critical path - Oriented & thermal aware X-filling for high un-modeled defect coverageFotios Vartziotis, Xrysovalantis Kavousianos. 642-645 [doi]
- A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoCDavide Appello, Paolo Bernardi, G. Giacopelli, A. Motta, A. Pagani, G. Pollaccia, C. Rabbi, Marco Restifo, P. Ruberg, Ernesto Sánchez, C. M. Villa, F. Venini. 646-649 [doi]
- Energy efficient stochastic computing with Sobol sequencesSiting Liu, Jie Han. 650-653 [doi]
- Logic analysis and verification of n-input genetic logic circuitsHasan Baig, Jan Madsen. 654-657 [doi]
- A novel way to efficiently simulate complex full systems incorporating hardware acceleratorsTampouratzis Nikolaos, Konstantinos Georgopoulos, Yannis Papaefstathiou. 658-661 [doi]
- Automatic abstraction of multi-discipline analog models for efficient functional simulationEnrico Fraccaroli, Michele Lora, Franco Fummi. 662-665 [doi]
- Novel magnetic burn-in for retention testing of STTRAMMohammad Nasim Imtiaz Khan, Anirudh Srikant Iyengar, Swaroop Ghosh. 666-669 [doi]
- Automatic construction of models for analytic system-level design space exploration problemsSeyed Hosein Attarzadeh Niaki, Ingo Sander. 670-673 [doi]
- Security in the Internet of Things: A challenge of scalePatrick Schaumont. 674-679 [doi]
- Sensitized path PUF: A lightweight embedded physical unclonable functionMatthias Sauer, Pascal Raiola, Linus Feiten, Bernd Becker 0001, Ulrich Rührmair, Ilia Polian. 680-685 [doi]
- Temperature aware phase/frequency detector-basec RO-PUFs exploiting bulk-controlled oscillatorsSha Tao, Elena Dubrova. 686-691 [doi]
- ChaCha20-Poly1305 authenticated encryption for high-speed embedded IoT applicationsFabrizio De Santis, Andreas Schauer, Georg Sigl. 692-697 [doi]
- Towards post-quantum security for IoT endpoints with NTRUOscar M. Guillen, Thomas Pöppelmann, Jose M. Bermudo Mera, Elena Fuentes Bongenaar, Georg Sigl, Johanna Sepúlveda. 698-703 [doi]
- Automating the pipeline of arithmetic datapathsMatei Istoan, Florent de Dinechin. 704-709 [doi]
- Operand size reconfiguration for big data processing in memoryPaulo C. Santos, Geraldo F. Oliveira, Diego G. Tome, Marco Antonio Zanata Alves, Eduardo C. Almeida, Luigi Carro. 710-715 [doi]
- Architectural optimizations for high performance and energy efficient Smith-Waterman implementation on FPGAs using OpenCLLorenzo Di Tucci, Kenneth O'Brien, Michaela Blott, Marco D. Santambrogio. 716-721 [doi]
- Memristor for computing: Myth or reality?Said Hamdioui, Shahar Kvatinsky, Gert Cauwenberghs, Lei Xie, Nimrod Wald, Siddharth Joshi, Hesham Mostafa Elsayed, Henk Corporaal, Koen Bertels. 722-731 [doi]
- An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpartWeiWei Jiang, Davide Bertozzi, Gabriele Miorandi, Steven M. Nowick, Wayne P. Burleson, Greg Sadowski. 732-733 [doi]
- An advanced embedded architecture for connected component analysis in industrial applicationsMenbere Tekleyohannes, MohammadSadegh Sadri, Christian Weis, Norbert Wehn, Martin Klein, Michael Siegrist. 734-735 [doi]
- Workload dependent reliability timing analysis flowAjith Sivadasan, Armelle Notin, Vincent Huard, Etienne Maurin, Souhir Mhira, Florian Cacho, Lorena Anghel. 736-737 [doi]
- Probabilistic timing analysis on time-randomized platforms for the space domainMikel Fernández, David Morales, Leonidas Kosmidis, Alen Bardizbanyan, Ian Broster, Carles Hernández, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla, Paulo Machado, Luca Fossati. 738-739 [doi]
- Cross-layer design of reconfigurable cyber-physical systemsM. Masin, Francesca Palumbo, H. Myrhaug, J. A. de Oliveira Filho, M. Pastena, Maxime Pelcat, Luigi Raffo, Francesco Regazzoni, A. A. Sanchez, A. Toffetti, E. de la Torre, K. Zedda. 740-745 [doi]
- INSPEX: Design and integration of a portable/wearable smart spatial exploration systemS. Lesecq, Julie Foucault, F. Birot, H. de Chaumont, C. Jackson, M. Correvon, P. Heck, R. Banach, A. di Matteo, V. Di Palma, J. Barrett, S. Rea, J.-M. Van Gyseghem, C. O'Murchu, A. Mathewson. 746-751 [doi]
- Near-optimal deployment of dataflow applications on many-core platforms with real-time guaranteesStefanos Skalistis, Alena Simalatsar. 752-757 [doi]
- Simulating preemptive scheduling with timing-aware blocks in SimulinkAndreas Naderlinger. 758-763 [doi]
- Online workload monitoring with the feedback of actual execution time for real-time systemsBiao Hu, Kai Huang 0001, Gang Chen, Long Cheng, Alois Knoll. 764-769 [doi]
- Automated synthesis of compact crossbars for sneak-path based in-memory computingDwaipayan Chakraborty, Sumit Kumar Jha. 770-775 [doi]
- Hybrid spiking-based multi-layered self-learning neuromorphic system based on memristor crossbar arraysAmr M. Hassan, Chaofei Yang, Chenchen Liu, Hai Helen Li, Yiran Chen. 776-781 [doi]
- ReVAMP: ReRAM based VLIW architecture for in-memory computingDebjyoti Bhattacharjee, Rajeswari Devadoss, Anupam Chattopadhyay. 782-787 [doi]
- Accurate private/shared classification of memory accesses: A run-time analysis system for the LEON3 multi-core processorNam Ho, Ishraq Ibne Ashraf, Paul Kaufmann, Marco Platzner. 788-793 [doi]
- Design of a low power, relative timing based asynchronous MSP430 microprocessorDipanjan Bhadra, Kenneth S. Stevens. 794-799 [doi]
- A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioningRahul Jain 0004, Preeti Ranjan Panda, Sreenivas Subramoney. 800-805 [doi]
- GPIOCP: Timing-accurate general purpose I/O controller for many-core real-time systemsZhe Jiang, Neil C. Audsley. 806-811 [doi]
- An algorithm to find optimum support-reducing decompositions for index generation functionsTsutomu Sasao, Kyu Matsuura, Yukihiro Iguchi. 812-817 [doi]
- Taking one-to-one mappings for granted: Advanced logic design of encoder circuitsAlwin Zulehner, Robert Wille. 818-823 [doi]
- Analysis of short-circuit conditions in logic circuitsJoão Afonso, Jose Monteiro. 824-829 [doi]
- Busy man's synthesis: Combinational delay optimization with SATMathias Soeken, Giovanni De Micheli, Alan Mishchenko. 830-835 [doi]
- The engineering challenges in quantum computingCarmen G. Almudéver, L. Lao, Xiang Fu, N. Khammassi, Imran Ashraf, Dan Iorga, S. Varsamopoulos, C. Eichler, A. Wallraff, L. Geck, A. Kruth, J. Knoch, H. Bluhm, Koen Bertels. 836-845 [doi]
- MVP ECC : Manufacturing process variation aware unequal protection ECC for memory reliabilitySeung-Yeob Lee, Joon-Sung Yang. 846-851 [doi]
- Analyzing the effects of peripheral circuit aging of embedded SRAM architecturesJosef Kinseher, Leonhard Heis, Ilia Polian. 852-857 [doi]
- Mitigation of sense amplifier degradation using input switchingDaniel Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor, Wim Dehaene. 858-863 [doi]
- Scalable probabilistic power budgeting for many-coresAnuj Pathania, Heba Khdr, Muhammad Shafique, Tulika Mitra, Jörg Henkel. 864-869 [doi]
- Exploiting sporadic servers to provide budget scheduling for ARINC653 based real-time virtualization environmentsMatthias Beckert, Kai Bjorn Gemlau, Rolf Ernst. 870-875 [doi]
- Programming and analysing scenario-aware dataflow on a multi-processor platformReinier van Kampenhout, Sander Stuijk, Kees G. W. Goossens. 876-881 [doi]
- Leveraging aging effect to improve SRAM-based true random number generatorsSaman Kiamehr, Mohammad Saber Golanbari, Mehdi Baradaran Tahoori. 882-885 [doi]
- Design automation for obfuscated circuits with multiple viable functionsShahrzad Keshavarz, Christof Paar, Daniel E. Holcomb. 886-889 [doi]
- Double MAC: Doubling the performance of convolutional neural networks on modern FPGAsDong Nguyen, Daewoo Kim, Jongeun Lee. 890-893 [doi]
- BITMAN: A tool and API for FPGA bitstream manipulationsKhoa Dang Pham, Edson L. Horta, Dirk Koch. 894-897 [doi]
- A generic topology selection method for analog circuits with embedded circuit sizing demonstrated on the OTA exampleAndreas Gerlach, Jürgen Scheible, Thoralf Rosahl, Frank-Thomas Eitrich. 898-901 [doi]
- Latency analysis of homogeneous synchronous dataflow graphs using timed automataGuus Kuiper, Marco Jan Gerrit Bekooij. 902-905 [doi]
- COVERT: Counter OVErflow ReducTion for efficient encryption of non-volatlle memoriesShivam Swami, Kartik Mohanram. 906-909 [doi]
- A wear-leveling-aware counter mode for data encryption in non-volatile memoriesFangting Huang, Dan Feng, Yu Hua, Wen Zhou. 910-913 [doi]
- Tunnel FET based refresh-free-DRAMNavneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel. 914-917 [doi]
- A hardware implementation of the MCAS synchronization primitiveSrishty Patel, Rajshekar Kalayappan, Ishani Mahajan, Smruti R. Sarangi. 918-921 [doi]
- BandiTS: Dynamic timing speculation using multi-armed bandit based optimizationJeff Jun Zhang, Siddharth Garg. 922-925 [doi]
- Design and implementation of a fair credit-based bandwidth sharing scheme for busesMladen Slijepcevic, Carles Hernández, Jaume Abella, Francisco J. Cazorla. 926-929 [doi]
- Technology mapping with all spin logicBoyu Zhang, Azadeh Davoodi. 930-933 [doi]
- A new method to identify threshold logic functionsSeyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis. 934-937 [doi]
- A bridging fault model for line coverage in the presence of undetected transition faultsIrith Pomeranz. 938-941 [doi]
- CHRT: A criticality- and heterogeneity-aware runtime system for task-parallel applicationsMyeonggyun Han, Jinsu Park, Woongki Baek. 942-945 [doi]
- MobiXen: Porting Xen on Android devices for mobile virtualizationYaozu Dong, Jianguo Yao, Haibing Guan, R. Ananth Krishna, Yunhong Jiang. 946-949 [doi]
- Optimisation opportunities and evaluation for GPGPU applications on low-end mobile GPUsMatina Maria Trompouki, Leonidas Kosmidis. 950-953 [doi]
- Ultra-low power and dependability for IoT devices (Invited paper for IoT technologies)Jörg Henkel, Santiago Pagani, Hussam Amrouch, Lars Bauer, Farzad Samie. 954-959 [doi]
- Energy-driven computing: Rethinking the design of energy harvesting systemsGeoff V. Merrett, Bashir M. Al-Hashimi. 960-965 [doi]
- Nonvolatile processors: Why is it trending?Fang Su, Kaisheng Ma, Xueqing Li, Tongda Wu, Yongpan Liu, Vijaykrishnan Narayanan. 966-971 [doi]
- Advanced spintronic memory and logic for non-volatile processorsRobert Perricone, Ibrahim Ahmed, Zhaoxin Liang, Meghna G. Mankalale, Xiaobo Sharon Hu, Chris H. Kim, Michael T. Niemier, Sachin S. Sapatnekar, Jian-Ping Wang. 972-977 [doi]
- Automatic generation of formally-proven tamper-resistant Galois-field multipliers based on generalized masking schemeRei Ueno, Naofumi Homma, Sumio Morioka, Takafumi Aoki. 978-983 [doi]
- SCAM: Secured content addressable memory based on homomorphic encryptionSong Bian, Masayuki Hiromoto, Takashi Sato. 984-989 [doi]
- SPARX - A side-channel protected processor for ARX-based cryptographyFlorian Bache, Tobias Schneider 0002, Amir Moradi 0001, Tim Giineysu. 990-995 [doi]
- Adaptive compressed sensing at the fingertip of Internet-of-Things sensors: An ultra-low power activity recognitionRamin Fallahzadeh, Josue Pagan Ortiz, Hassan Ghasemzadeh. 996-1001 [doi]
- A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controllerAlexander Boschmann, Georg Thombansen, Linus Witschen, Alex Wiens, Marco Platzner. 1002-1007 [doi]
- Microwatt end-to-End digital neural signal processing systems for motor intention decodingZhewei Jiang, ChiSung Bae, Joonseong Kang, Sang Joon Kim, Mingoo Seok. 1008-1013 [doi]
- An embedded system remotely driving mechanical devices by P300 brain activityDaniela De Venuto, Valerio F. Annese, Giovanni Mezzina. 1014-1019 [doi]
- Revamping timing error resilience to tackle choke points at NTC systemsAatreyi Bal, Shamik Saha, Sanghamitra Roy, Koushik Chakraborty. 1020-1025 [doi]
- Efficient neural network acceleration on GPGPU using content addressable memoryMohsen Imani, Daniel Peroni, Yeseong Kim, Abbas Rahimi, Tajana Rosing. 1026-1031 [doi]
- Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networksShihao Wang, Dajiang Zhou, Xushen Han, Takeshi Yoshimura. 1032-1037 [doi]
- Continuous learning of HPC infrastructure models using big data analytics and in-memory processing toolsFrancesco Beneventi, Andrea Bartolini, Carlo Cavazzoni, Luca Benini. 1038-1043 [doi]
- Self-aware computing systems: From psychology to engineeringPeter R. Lewis. 1044-1049 [doi]
- Self-awareness in autonomous automotive systemsJohannes Schlatow, Mischa Möstl, Rolf Ernst, Marcus Nolte, Inga Jatzkowski, Markus Maurer, Christian Herber, Andreas Herkersdorf. 1050-1055 [doi]
- Self-awareness in remote health monitoring systems using wearable electronicsArman Anzanpour, Iman Azimi, Maximilian Gotzinger, Amir M. Rahmani, Nima Taherinejad, Pasi Liljeberg, Axel Jantsch, Nikil Dutt. 1056-1061 [doi]
- Hardware-accelerated dynamic binary translationSimon Rokicki, Erven Rohou, Steven Derrien. 1062-1067 [doi]
- Superword level parallelism aware word length optimizationAli Hassan El Moussawi, Steven Derrien. 1068-1073 [doi]
- Schedulability-aware SPM Allocation for preemptive hard real-time systems with arbitrary activation patternsArno Luppold, Heiko Falk. 1074-1079 [doi]
- A Log-aware Synergized scheme for page-level FTL designChu Li, Dan Feng, Yu Hua, Fang Wang, Chuntao Jiang, Wei Zhou. 1080-1085 [doi]
- MALRU: Miss-penalty aware LRU-based cache replacement for hybrid memory systemsDi Chen, Hai Jin, Xiaofei Liao, Haikun Liu, Rentong Guo, Dong Liu. 1086-1091 [doi]
- Endurance management for resistive Logic-In-Memory computing architecturesSaeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler. 1092-1097 [doi]
- Live together or Die Alone: Block cooperation to extend lifetime of resistive memoriesMohammad Khavari Tavana, Amir Kavyan Ziabari, David R. Kaeli. 1098-1103 [doi]
- Secure Cyber-Physical Systems: Current trends, tools and open research problemsAnupam Chattopadhyay, Alok Prakash, Muhammad Shafique. 1104-1109 [doi]
- Don't fall into a trap: Physical side-channel analysis of ChaCha20-Poly1305Bernhard Jungk, Shivam Bhasin. 1110-1115 [doi]
- The RowHammer problem and other issues we may face as memory becomes denserOnur Mutlu. 1116-1121 [doi]
- Compromising FPGA SoCs using malicious hardware blocksNisha Jacob, Carsten Rolfes, Andreas Zankl, Johann Heyszl, Georg Sigl. 1122-1127 [doi]
- Inspiring trust in outsourced integrated circuit fabricationSiddharth Garg. 1128 [doi]
- Analyzing security breaches of countermeasures throughout the refinement process in hardware design flowJean-Luc Danger, Sylvain Guilley, Philippe Nguyen, Robert Nguyen, Youssef Souissi. 1129-1134 [doi]
- Automatic operating point distillation for hybrid mapping methodologiesBehnaz Pourmohseni, Michael Glaß, Jürgen Teich. 1135-1140 [doi]
- Design Space exploration of FPGA-based accelerators with multi-level parallelismGuanwen Zhong, Alok Prakash, Siqi Wang, Yun Liang, Tulika Mitra, Smaïl Niar. 1141-1146 [doi]
- Design space exploration of FPGA accelerators for convolutional neural networksAtul Rahman, Sangyun Oh, Jongeun Lee, Kiyoung Choi. 1147-1152 [doi]
- A slack-based approach to efficiently deploy radix 8 booth multipliersAlberto A. Del Barrio, Román Hermida. 1153-1158 [doi]
- Measurement and validation of energy harvesting IoT devicesLukas Sigrist, Andres Gomez, Roman Lim, Stefan Lippuner, Matthias Leubin, Lothar Thiele. 1159-1164 [doi]
- A methodology for the design of dynamic accuracy operators by runtime back biasDaniele Jahier Pagliari, Yves Durand, David Coriat, Anca Molnos, Edith Beigné, Enrico Macii, Massimo Poncino. 1165-1170 [doi]
- A scan-chain based state retention methodology for IoT processors operating on intermittent energyPascal Alexander Hager, Hamed Fatemi, José Pineda de Gyvez, Luca Benini. 1171-1176 [doi]
- A circuit-equivalent battery model accounting for the dependency on load frequencyYukai Chen, Enrico Macii, Massimo Poncino. 1177-1182 [doi]
- SLoT: A supervised learning model to predict dynamic timing errors of functional unitsXun Jiao, Yu Jiang, Abbas Rahimi, Rajesh K. Gupta. 1183-1188 [doi]
- Exploiting data-dependence and Flip-Flop asymmetry for zero-overhead system soft error mitigationVikas Chandra, Liangzhen Lai. 1189-1194 [doi]
- Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuitsWenlong Lv, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng. 1195-1200 [doi]
- Efficient yield optimization method using a variable K-Means algorithm for analog IC sizingAntónio Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço 0003, Nuno Horta. 1201-1206 [doi]
- An efficient leakage-aware thermal simulation approach for 3D-ICs using corrected linearized model and algebraic multigridChao Yan, Hengliang Zhu, Dian Zhou, Xuan Zeng. 1207-1212 [doi]
- A thermally-aware energy minimization methodology for global interconnectsSoheil Nazar Shahsavani, Alireza Shafaei, Shahin Nazarian, Massoud Pedram. 1213-1218 [doi]
- Analysis and optimization of variable-latency designs in the presence of timing variabilityChang-Lin Tsai, Chao-Wei Cheng, Ning-Chi Huang, Kai-Chiang Wu. 1219-1224 [doi]
- 1024-Channel 3D ultrasound digital beamformer in a single 5W FPGAFederico Angiolini, A. Ibrahim, W. Simon, A. C. Yuzuguler, M. Arditi, Jean-Philippe Thiran, Giovanni De Micheli. 1225-1228 [doi]
- LAANT: A library to automatically optimize EDP for OpenMP applicationsArthur Francisco Lorenzon, Jeckson Dellagostin Souza, Antonio Carlos Schneider Beck. 1229-1232 [doi]
- Improving the accuracy of the leakage power estimation of embedded CPUsTing-Wu Chin, Shiao Li Tsao, Kuo-Wei Hung, Pei Shu Huang. 1233-1236 [doi]
- Schedule-aware loop parallelization for embedded MPSoCs by exploiting parallel slackMiguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Nikolaos Kavvadias, Liam Fitzpatrick. 1237-1240 [doi]
- Reducing code management overhead in software-managed multicoresJian Cai, Yooseong Kim, Youngbin Kim, Aviral Shrivastava, Kyoungwoo Lee. 1241-1244 [doi]
- Performance evaluation and optimization of HBM-Enabled GPU for data-intensive applicationsMaohua Zhu, Youwei Zhuo, Chao Wang, Wenguang Chen, Yuan Xie. 1245-1248 [doi]
- DAC: Dedup-assisted compression scheme for improving lifetime of NAND storage systemsJisung Park, Sungjin Lee, Jihong Kim. 1249-1252 [doi]
- Lifetime adaptive ECC in NAND flash page managementShunzhuo Wang, Fei Wu, Zhonghai Lu, You Zhou, Qin Xiong, Meng Zhang, Changsheng Xie. 1253-1556 [doi]
- 3D-DPE: A 3D high-bandwidth dot-product engine for high-performance neuromorphic computingMiguel Angel Lastras-Montaño, Bhaswar Chakrabarti, Dmitri B. Strukov, Kwang-Ting Cheng. 1257-1260 [doi]
- A schedulability test for software migration on multicore systemJung-Eun Kim, Richard M. Bradford, Tarek F. Abdelzaher, Lui Sha. 1261-1264 [doi]
- Adaptive power delivery system management for many-core processors with on/off-chip voltage regulatorsHaoran Li, Jiang Xu, Zhe Wang, Peng Yang, Rafael K. V. Maeda, Zhongyuan Tian. 1265-1268 [doi]
- Flying and decoupling capacitance optimization for area-constrained on-chip switched-capacitor voltage regulatorsXiaoyang Mi, Hesam Fathi Moghadam, Jae-sun Seo. 1269-1272 [doi]
- Enhancing analog yield optimization for variation-aware circuits sizingOns Lahiouel, Mohamed H. Zaki, Sofiène Tahar. 1273-1276 [doi]
- A new sampling technique for Monte Carlo-based statistical circuit analysisHiwa Mahmoudi, Horst Zimmermann. 1277-1280 [doi]
- Automatic technology migration of analog IC designs using generic cell librariesJose Cachaco, Nuno Machado, Nuno Lourenço 0003, Jorge Guilherme, Nuno Horta. 1281-1284 [doi]
- Noise-sensitive feedback loop identification in linear time-varying analog circuitsAng Li, Peng Li, Tingwen Huang, Edgar Sánchez-Sinencio. 1285-1288 [doi]
- CAnDy-TM: Comparative analysis of dynamic thermal management in many-cores using model checkingSyed Ali Asadullah Bukhari, Faiq Khalid Lodhi, Osman Hasan, Muhammad Shafique, Jörg Henkel. 1289-1292 [doi]
- Power pre-characterized meshing algorithm for finite element thermal analysis of integrated circuitsShohdy Abdelkader, Alaa ELRouby, Mohamed Dessouky. 1293-1296 [doi]
- An optimal approach for low-power migraine prediction models in the state-of-the-art wireless monitoring devicesJosué Pagán, Ramin Fallahzadeh, Hassan Ghasemzadeh, José Manuel Moya, José Luis Risco-Martín, Jose L. Ayala. 1297-1302 [doi]
- Logic optimization and synthesis: Trends and directions in industryLuca Gaetano Amarù, Patrick Vuillod, Jiong Luo, Janet Olson. 1303-1305 [doi]
- Wave pipelining for majority-based beyond-CMOS technologiesOdysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, G. De Micheli, Luca Gaetano Amarù, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins. 1306-1311 [doi]
- Design automation for quantum architecturesMartin Rötteler, Krysta Marie Svore, Dave Wecker, Nathan Wiebe. 1312-1317 [doi]
- Side-channel plaintext-recovery attacks on leakage-resilient encryptionThomas Unterluggauer, Mario Werner, Stefan Mangard. 1318-1323 [doi]
- Static power side-channel analysis of a threshold implementation prototype chipThorben Moos, Amir Moradi 0001, Bastian Richter. 1324-1329 [doi]
- Side-channel power analysis of XTS-AESChao Luo, Yunsi Fei, A. Adam Ding. 1330-1335 [doi]
- A field programmable transistor array featuring single-cycle partial/full dynamic reconfigurationJingxiang Tian, Gaurav Rajavendra Reddy, Jiajia Wang, William Swartz, Yiorgos Makris, Carl Sechen. 1336-1341 [doi]
- A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon eraZeinab Seifoori, Behnam Khaleghi, Hossein Asadi. 1342-1347 [doi]
- A static-placement, dynamic-issue framework for CGRA loop acceleratorZhongyuan Zhao, Weiguang Sheng, Weifeng He, Zhigang Mao, Zhaoshi Li. 1348-1353 [doi]
- Machine learning enabled power-aware Network-on-Chip designDominic DiTomaso, Md. Ashif I. Sikder, Avinash Karanth Kodi, Ahmed Louri. 1354-1359 [doi]
- Performance evaluation and design trade-offs for wireless-enabled SMART NoCKarthi Duraisamy, Partha Pratim Pande. 1360-1365 [doi]
- Robust TSV-based 3D NoC design to counteract electromigration and crosstalk noiseSourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty. 1366-1371 [doi]
- Mixed-criticality processing pipelinesDionisio de Niz, Björn Andersson, Hyoseung Kim, Mark H. Klein, Linh Thi Xuan Phan, Raj Rajkumar. 1372-1375 [doi]
- Performance and energy aware wavelength allocation on ring-based WDM 3D optical NoCJ. Luo, A. Elantably, V. D. Pham, Cedric Killian, Daniel Chillet, Sébastien Le Beux, Olivier Sentieys, Ian O'Connor. 1372-1377 [doi]
- Exploiting special-purpose function approximation for hardware-efficient QR-decompositionJochen Rust, Steffen Paul. 1378-1383 [doi]
- Embracing approximate computing for energy-efficient motion estimation in high efficiency video codingWalaa El-Harouni, Semeen Rehman, Bharath Srinivas Prabakaran, Akash Kumar 0001, Rehan Hafiz, Muhammad Shafique. 1384-1389 [doi]
- Hardware architecture of Bidirectional Long Short-Term Memory Neural Network for Optical Character RecognitionVladimir Rybalkin, Norbert Wehn, Mohammad Reza Yousefi, Didier Stricker. 1390-1395 [doi]
- MoDNN: Local distributed mobile computing system for Deep Neural NetworkJiachen Mao, Xiang Chen, Kent W. Nixon, Christopher Krieger, Yiran Chen. 1396-1401 [doi]
- Energy-adaptive scheduling of imprecise computation tasks for QoS optimization in real-Time MPSoC systemsJunlong Zhou, Jianming Yan, Tongquan Wei, Mingsong Chen, Xiaobo Sharon Hu. 1402-1407 [doi]
- Fix the leak! an information leakage aware secured cyber-physical manufacturing systemSujit Rokka Chhetri, Sina Faezi, Mohammad Abdullah Al Faruque. 1408-1413 [doi]
- Efficient drone hijacking detection using onboard motion sensorsZhiwei Feng, Nan Guan, Mingsong Lv, Weichen Liu, Qingxu Deng, Xue Liu, Wang Yi 0001. 1414-1419 [doi]
- Reconfigurable embedded systems applications for versatile biomedical measurementsLuca Cerina, Marco D. Santambrogio. 1420-1425 [doi]
- Ultra low power microelectronics for wearable and medical devicesPierre-François Ruedi, A. Bishof, Marcin K. Augustyniak, P. Persechini, J.-L. Nagel, Marc Pons, Stephane Emery, Olivier Chételat. 1426-1431 [doi]
- Design challenges for wearable EMG applicationsBojan Milosevic, Simone Benatti, Elisabetta Farella. 1432-1437 [doi]
- Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computingShaodi Wang, Saptadeep Pal, Tianmu Li, Andrew Pan, Cecile Grezes, Pedram Khalili Amiri, Kang L. Wang, Puneet Gupta. 1438-1443 [doi]
- Design and benchmarking of ferroelectric FET based TCAMXunzhao Yin, Michael T. Niemier, Xiaobo Sharon Hu. 1444-1449 [doi]
- Leveraging access port positions to accelerate page table walk in DWM-based main memoryHoda Aghaei Khouzani, Pouya Fotouhi, Chengmo Yang, Guang R. Gao. 1450-1455 [doi]
- VAET-STT: A variation aware estimator tool for STT-MRAM based memoriesSarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Mehdi Baradaran Tahoori. 1456-1461 [doi]
- A novel zero weight/activation-aware hardware architecture of convolutional neural networkDongyoung Kim, Junwhan Ahn, Sungjoo Yoo. 1462-1467 [doi]
- A Mechanism for energy-efficient reuse of decoding and scheduling of x86 instruction streamsMarcelo Brandalero, Antonio Carlos Schneider Beck. 1468-1473 [doi]
- Understanding the impact of precision quantization on the accuracy and energy of neural networksSoheil Hashemi, Nicholas Anthony, Hokchhay Tann, R. Iris Bahar, Sherief Reda. 1474-1479 [doi]
- Big vs little core for energy-efficient Hadoop computingMaria Malik, Katayoun Neshatpour, Tinoosh Mohsenin, Avesta Sasan, Houman Homayoun. 1480-1485 [doi]
- Quantifying error: Extending static timing analysis with probabilistic transitionsKevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides. 1486-1491 [doi]
- On refining standard cell placement for self-aligned double patterningYe Hong Chen, Sheng-He Wang, Ting-Chi Wang. 1492-1497 [doi]
- Cut mask optimization for multi-patterning directed self-assembly lithographyWachirawit Ponghiran, Seongbo Shim, Youngsoo Shin. 1498-1503 [doi]
- Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generationTaesik Na, Jong Hwan Ko, Saibal Mukhopadhyay. 1504-1509 [doi]
- On reducing busy waiting in autosar via task-release-delta-based runnable reorderingRobert Hoettger, Burkhard Igel, Olaf Spinczyk. 1510-1515 [doi]
- Power neutral performance scaling for energy harvesting MP-SoCsBenjamin J. Fletcher, Domenico Balsamo, Geoff V. Merrett. 1516-1521 [doi]
- Efficient decentralized active balancing strategy for smart battery cellsNitin Shivaraman, Arvind Easwaran, Sebastian Steinhorst. 1522-1527 [doi]
- WULoRa: An energy efficient IoT end-node for energy harvesting and heterogeneous communicationMichele Magno, Fayçal Ait Aoudia, Matthieu Gautier, Olivier Berder, Luca Benini. 1528-1533 [doi]
- Characterization of stack behavior under soft errorsJunchi Ma, Yun Wang. 1534-1539 [doi]
- Multi-armed bandits for efficient lifetime estimation in MPSoC designCalvin Ma, Aditya Mahajan, Brett H. Meyer. 1540-1545 [doi]
- Hardware-based on-line intrusion detection via system call routine fingerprintingLiwei Zhou, Yiorgos Makris. 1546-1551 [doi]
- Static netlist verification for IBM high-frequency processors using a tree-grammarChristoph Jäschke, Ulla Herter, Claudia Wolkober, Carsten Schmitt, Christian G. Zoellin. 1552-1557 [doi]
- m) arithmeticCunxi Yu, Daniel E. Holcomb, Maciej J. Ciesielski. 1558-1563 [doi]
- Formal specification and dependability analysis of optical communication networksUmair Siddique, Khaza Anuarul Hoque, Taylor T. Johnson. 1564-1569 [doi]
- An evolutionary approach to runtime variability mapping and mitigation on a multi-reconfigurable architectureSimon J. Bale, Pedro B. Campos, Martin A. Trefzer, James Alfred Walker, Andy M. Tyrrell. 1570-1575 [doi]
- Towards low power approximate DCT architecture for HEVC standardZdenek Vasícek, Vojtech Mrazek, Lukás Sekanina. 1576-1581 [doi]
- Semantic driven hierarchical learning for energy-efficient image classificationPriyadarshini Panda, Kaushik Roy 0001. 1582-1587 [doi]
- Machine learning for run-time energy optimisation in many-core systemsDwaipayan Biswas, Vibishna Balagopal, Rishad A. Shafik, Bashir M. Al-Hashimi, Geoff V. Merrett. 1588-1592 [doi]
- An evolutionary approach to hardware encryption and Trojan-horse mitigationAndrea Marcelli, Marco Restifo, Ernesto Sánchez, Giovanni Squillero. 1593-1598 [doi]
- Formal model for system-level power management designMirela Simonovic, Vojin Zivojnovic, Lazar Saranovac. 1599-1602 [doi]
- Extending memory capacity of neural associative memory based on recursive synaptic bit reuseTianchan Guan, Xiaoyang Zeng, Mingoo Seok. 1603-1606 [doi]
- Anomalies in scheduling control applications and design complexityAmir Aminifar, Enrico Bini. 1607-1610 [doi]
- Contract-based integration of automotive control softwareTobias Sehnke, Matthias Schultalbers, Rolf Ernst. 1611-1614 [doi]
- Modeling and integrating physical environment assumptions in medical cyber-physical system designZhicheng Fu, Chunhui Guo, Shangping Ren, Yu Jiang, Lui Sha. 1615-1618 [doi]
- A utility-driven data transmission optimization strategy in large scale cyber-physical systemsSoumi Chattopadhyay, Ansuman Banerjee, Bei Yu. 1619-1622 [doi]
- Protect non-volatile memory from wear-out attack based on timing difference of row buffer hit/missHaiyu Mao, Xian Zhang, Guangyu Sun, Jiwu Shu. 1623-1626 [doi]
- Effects of cell shapes on the routability of Digital Microfluidic BiochipsLeonard Schneider, Oliver Keszocze, Jannis Stoppe, Rolf Drechsler. 1627-1630 [doi]
- LESS: Big data sketching and Encryption on low power platformAmey M. Kulkarni, Colin Shea, Houman Homayoun, Tinoosh Mohsenin. 1631-1634 [doi]
- TruncApp: A truncation-based approximate divider for energy efficient DSP applicationsShaghayegh Vahdat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, Zainalabedin Navabi. 1635-1638 [doi]
- Timing-aware wire width optimization for SADP processYoungsoo Song, Sangmin Kim, Youngsoo Shin. 1639-1642 [doi]
- Formal timing analysis of non-scheduled traffic in automotive scheduled TSN networksFedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich. 1643-1646 [doi]
- Ultra low-power visual odometry for nano-scale unmanned aerial vehiclesDaniele Palossi, Andrea Marongiu, Luca Benini. 1647-1650 [doi]
- Long range wireless sensing powered by plant-microbial fuel cellMaurizio Rossi, Pietro Tosato, Luca Gemma, Luca Torquati, Cristian Catania, Sergio Camalo, Davide Brunelli. 1651-1654 [doi]
- On the cooperative automatic lane change: Speed synchronization and automatic "courtesy"Alexandre Lombard, Florent Perronnet, Abdeljalil Abbas-Turki, Abdellah El Moudni. 1655-1658 [doi]
- Evaluating matrix representations for error-tolerant computingPareesa Ameneh Golnari, Sharad Malik. 1659-1662 [doi]
- Simulation-based design procedure for sub 1V CMOS current referenceDmitry Osipov, Steffen Paul. 1663-1666 [doi]
- Fast architecture-level synthesis of fault-tolerant flow-based microfluidic biochipsWei-Lun Huang, Ankur Gupta 0002, Sudip Roy 0001, Tsung-Yi Ho, Paul Pop. 1667-1672 [doi]
- CoSyn: Efficient single-cell analysis using a hybrid microfluidic platformMohamed Ibrahim, Krishnendu Chakrabarty, Ulf Schlichtmann. 1673-1678 [doi]
- Verification of networked Labs-on-Chip architecturesAndreas Grimmer, Werner Haselmayr, Andreas Springer, Robert Wille. 1679-1684 [doi]
- Synthesis of activation-parallel convolution structures for neuromorphic architecturesSeban Kim, Jaeyong Chung. 1685-1690 [doi]
- Register transfer level information flow tracking for provably secure hardware designArmaiti Ardeshiricham, Wei Hu, Joshua Marxen, Ryan Kastner. 1691-1696 [doi]
- Dude, is my code constant time?Oscar Reparaz, Josep Balasch, Ingrid Verbauwhede. 1697-1702 [doi]
- Information flow tracking in analog/mixed-signal designs through proof-carrying hardware IPMohammad-Mahdi Bidmeshki, Angelos Antonopoulos, Yiorgos Makris. 1703-1708 [doi]
- Sampling-based binary-level cross-platform performance estimationXinnian Zheng, Haris Vikalo, Shuang Song, Lizy K. John, Andreas Gerstlauer. 1709-1714 [doi]
- A layered formal framework for modeling of cyber-physical systemsGeorge Ungureanu, Ingo Sander. 1715-1720 [doi]
- Efficient synchronization methods for LET-based applications on a Multi-Processor System on ChipGabriela Breaban, Sander Stuijk, Kees Goossens. 1721-1726 [doi]
- Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networksXiaoyi Wang, Hongyu Wang, Jian He, Sheldon X.-D. Tan, Yici Cai, Shengqi Yang. 1727-1732 [doi]
- A fast leakage aware thermal simulator for 3D chipsHameedah Sultan, Smruti R. Sarangi. 1733-1738 [doi]
- Blind identification of power sources in processorsSherief Reda, Adel Belouchrani. 1739-1744 [doi]
- Fast low power rule checking for multiple power domain designChien Pang Lu, Iris Hui-Ru Jiang. 1745-1750 [doi]
- Benefits of asynchronous control for analog electronics: Multiphase buck case studyDanil Sokolov, Vladimir Dubikhin, Victor Khomenko, David Lloyd, Andrey Mokhov, Alex Yakovlev. 1751-1756 [doi]
- High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADCNai-Chen Chen, Pang-Yen Chou, Helmut E. Graeb, Mark Po-Hung Lin. 1757-1762 [doi]
- Adaptive interference rejection in Human Body Communication using variable duty cycle integrating DDR receiverShovan Maity, Debayan Das, Shreyas Sen. 1763-1768 [doi]
- Efficient storage management for aged file systems on persistent memoryKaisheng Zeng, Youyou Lu, Hu Wan, Jiwu Shu. 1769-1774 [doi]
- LookNN: Neural network with no multiplicationMohammad Samragh Razlighi, Mohsen Imani, Farinaz Koushanfar, Tajana Rosing. 1775-1780 [doi]
- Pegasus: Efficient data transfers for PGAS languages on non-cache-coherent many-coresManuel Mohr, Carsten Tradowsky. 1781-1786 [doi]
- Digital-microfluidic biochips for quantitative analysis: Bridging the Gap between microfluidics and microbiologyMohamed Ibrahim, Krishnendu Chakrabarty. 1787-1792 [doi]
- The case for semi-automated design of microfluidic very large scale integration (mVLSI) chipsJeffrey McDaniel, William H. Grover, Philip Brisk. 1793-1798 [doi]
- Synthesis of on-chip control circuits for mVLSI biochipsSeetal Potluri, Alexander Schneider, Martin Horslev-Petersen, Paul Pop, Jan Madsen. 1799-1804 [doi]
- Scheduling and optimization of genetic logic circuits on flow-based microfluidic biochipsYu-Jhih Chen, Sumit Sharma, Sudip Roy 0001, Tsung-Yi Ho. 1805-1810 [doi]