Kecheng Ji - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 7 from 7

2019

Fast modeling DRAM access latency based on the LLC memory stride distribution without detailed simulationsMing Ling, Xiaojing Shang, Kecheng Ji, Longxing Shi. mam, 64:159-169, 2019. [doi]

2018

An Analytical Cache Performance Evaluation Framework for Embedded Out-of-Order Processors Using Software CharacteristicsKecheng Ji, Ming Ling, Longxing Shi, Jianping Pan 0001. tecs, 17(4), 2018. [doi]

2017

Using the first-level cache stack distance histograms to predict multi-level LRU cache missesKecheng Ji, Ming Ling, Longxing Shi. mam, 55:55-69, 2017. [doi]

AFEC: An analytical framework for evaluating cache performance in out-of-order processorsKecheng Ji, Ming Ling, Qin Wang, Longxing Shi, Jianping Pan. date 2017: 55-60 [doi]

Retraction notice to 'Power Modeling for High Performance Network-on-Chip Architectures' [Microprocessors and Microsystems 50 (2017) 80-89]Kecheng Ji, Ming Ling, Yang Zhang, Longxing Shi. mam, 50:66-79, 2017. [doi]

A trace-driven analytical model with less profiling overhead for DRAM access latenciesFengying Sun, Kecheng Ji, Ming Ling, Longxing Shi. pacrim 2017: 1-6 [doi]

A mechanistic model of memory level parallelism fed with cache miss ratesQin Wang, Kecheng Ji, Ming Ling, Longxing Shi. pacrim 2017: 1-6 [doi]

Sign in or sign up to see more results.

runs on WebDSL