Taesik Na, Jong Hwan Ko, Saibal Mukhopadhyay. Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation. In David Atienza, Giorgio Di Natale, editors, Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017. pages 1504-1509, IEEE, 2017. [doi]
Abstract is missing.