Yukihiro Iguchi - researchr alias

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Viewing Publication 1 - 30 from 30

2021

Classification Functions for Handwritten Digit RecognitionTsutomu Sasao, Yuto Horikawa, Yukihiro Iguchi. ieicetd, 104-D(8):1076-1082, 2021. [doi]

A Design Method for Multiclass ClassifiersTsutomu Sasao, Yuto Horikawa, Yukihiro Iguchi. ismvl 2021: 148-153 [doi]

2020

Handwritten Digit Recognition Based on Classification FunctionsTsutomu Sasao, Yuto Horikawa, Yukihiro Iguchi. ismvl 2020: 124-129 [doi]

2017

An algorithm to find optimum support-reducing decompositions for index generation functionsTsutomu Sasao, Kyu Matsuura, Yukihiro Iguchi. date 2017: 812-817 [doi]

2014

A Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions Using Difference MatrixTsutomu Sasao, Yuta Urano, Yukihiro Iguchi. ieicet, 97-A(12):2427-2433, 2014. [doi]

A Lower Bound on the Number of Variables to Represent Incompletely Specified Index Generation FunctionsTsutomu Sasao, Yuta Urano, Yukihiro Iguchi. ismvl 2014: 7-12 [doi]

2011

A Realization Method of Forward Converters from Multiple-Precision Binary Numbers to Residue Numbers with Arbitrary Mutable ModulusKoki Shirakawa, Takashi Uemura, Yukihiro Iguchi. ismvl 2011: 268-273 [doi]

2008

On the Complexity of Error Detection Functions for Redundant Residue Number SystemsTsutomu Sasao, Yukihiro Iguchi. dsd 2008: 880-887 [doi]

2007

Design Methods of Radix Converters Using Arithmetic DecompositionsYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura. ieicet, 90-D(6):905-914, 2007. [doi]

Design Methods for Binary to Decimal Converters Using Arithmetic DecompositionsYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura. mvl, 13(4-6):503-520, 2007. [doi]

On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura. ismvl 2007: 32 [doi]

2006

On Designs of Radix Converters Using Arithmetic DecompositionsYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura. ismvl 2006: 3 [doi]

A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGAHui Qin, Tsutomu Sasao, Yukihiro Iguchi. ieicet, 89-D(3):1139-1147, 2006. [doi]

2005

Hardware to Compute Walsh CoefficientsYukihiro Iguchi, Tsutomu Sasao. ismvl 2005: 75-81 [doi]

An FPGA design of AES encryption circuit with 128-bit keysHui Qin, Tsutomu Sasao, Yukihiro Iguchi. glvlsi 2005: 147-151 [doi]

On LUT Cascade Realizations of FIR FiltersTsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki. dsdm 2005: 467-475 [doi]

2004

A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT CascadesYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura. ismvl 2004: 302-308 [doi]

Fault Diagnosis for RAMs Using Walsh SpectrumAtsumu Iseno, Yukihiro Iguchi, Tsutomu Sasao. ieicet, 87-D(3):592-600, 2004. [doi]

2003

Evaluation of multiple-output logic functions using decision diagramsYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura. aspdac 2003: 312-315 [doi]

2002

2001

Realization of Multiple-Output Functions by Reconfigurable CascadesYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura. iccd 2001: 388-393

2000

A hardware simulation engine based on decision diagrams (short paper)Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno. aspdac 2000: 73-76 [doi]

Implementation of Multiple-Output Functions Using PQMDDsYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura. ismvl 2000: 199-205 [doi]

1999

Realization of Regular Ternary Logic FunctionsYukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, Atsumu Iseno. aspdac 1999: 331 [doi]

1997

On Decomposition of Kleene TDDsYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura. ats 1997: 234 [doi]

On properties of Kleene TDDsYukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura. aspdac 1997: 473-476 [doi]

1989

Maximum PLA folding using invertersYukihiro Iguchi, Masao Mukaidono. scjapan, 20(4):1-10, 1989. [doi]

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