Table of Contents

• A VLSI implementation of the blowfish encryption/decryption algorithmMichael C.-J. Lin, Youn-Long Lin. 1-2 [doi]
• VLSI implementation of rake receiver for IS-95 CDMA Testbed using FPGAOliver Yuk-Hang Leung, Chi-Ying Tsui, Roger S. Cheng. 3-4 [doi]
• VLSI implementation of a switch fabric for mixed ATM and IP trafficChi-Ying Tsui, Louis Chung-Yin Kwan, Chin-Tau Lea. 5-6 [doi]
• Design of digital neural cell scheduler for intelligent IB-ATM switchJ. K. Lee, Seung Min Lee, Mike Myung-Ok Lee, D. W. Lee, Y.-C. Kim, S.-J. Jeong. 7-8 [doi]
• Genetic algorithm accelerator GAA-IIShin ichi Wakabayashi, Tetsushi Koide, Nayoshi Toshine, Masataka Yamane, Hajime Ueno. 9-10 [doi]
• A programmable built-in self-test core for embedded memoriesChih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu. 11-12 [doi]
• An algorithm for VLSI implementation of highly efficient cubic-polynomial evaluationFan Mo, Yihua Zhang, Jun Yu, Qianling Zhang. 13-14 [doi]
• Design of self-timed asynchronous Booth s multiplierTin-Y. Tang, Chin-S. Choy, Pui-L. Siu, Cheong-F. Chan. 15-16 [doi]
• High speed and ultra-low power 16×16 MAC deisgn using TG techniques for web-based multimedia systemSeung Min Lee, Jin-Hong Chung, Hying-S. Yoon, Mike Myung-Ok Lee. 17-18 [doi]
• A smart imager for the vision processing front-ENDNoriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata. 19-20 [doi]
• A binary image sensor with flexible motion vector detection using block matching methodTomohiro Nezuka, Takafumi Fujita, Makoto Ikeda, Kunihiro Asada. 21-22 [doi]
• An arbitrary chaos generator core curcuit using PWM/PPM signalsKenichi Murakoshi, Takashi Morie, Makoto Nagata, Atsushi Iwata. 23-24 [doi]
• An application specific Java processor with reconfigurabilitiesShinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Tatsumori Abematsu, Katsumasa Watanabe. 25-26 [doi]
• Reconfigurable synchronized dataflow processorHiroshi Sasaki, Hitoshi Maruyama, Hideaki Tsukioka, Nobuyoshi Shoji, Hiroaki Kobayashi, Tadao Nakamura. 27-28 [doi]
• Prototype microprocessor LSI with scheduling support hardware for operating system on multiprocessor systemNaoki Nishimura, Takahiro Sasaki, Tetsuo Hironaka. 29-30 [doi]
• A floating point arithmetic unit for a static scheduling and compiler oriented multiprocessor systemTakahiro Kawaguchi, Takayuki Suzuki, Hideharu Amano. 31-32 [doi]
• A 16-bit redundant binary multiplier using low-power pass-transistor logic SPLHirofumi Sakamoto, Ken ichiro Uda, Bu-Y. Lee, Hiroyuki Ochi, Kazuo Taki, Takao Tsuda. 33-34 [doi]
• An 8×8 nRERL serial multiplier for ultra-low-power aplicationsJoonho Lim, Dong-G. Kim, Sang-C. Kang, Soo-Ik Chae. 35-36 [doi]
• Embedded tutorial: essential issues for IP reuseDaniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul, Shojiro Mori, Tom Nukiyama, Pierre Bricaud. 37-42 [doi]
• Usage-based characterization of complex functional blocks for reuse in behavioral synthesisNong Fan, Viraphol Chaiyakul, Daniel Gajski. 43-48 [doi]
• Reuse and protection of intellectual property in the SpecC systemRainer Dömer, Daniel Gajski. 49-54 [doi]
• Fair watermarking techniquesGang Qu, Jennifer L. Wong, Miodrag Potkonjak. 55-60 [doi]
• An efficient heuristic for state encoding minimizing the BDD representations of the transistion relations of finite state machinesRiccardo Forth, Paul Molitor. 61-66 [doi]
• Automatic partitioning for efficient combinatorial verificationRajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita. 67-72 [doi]
• A hardware simulation engine based on decision diagrams (short paper)Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno. 73-76 [doi]
• Formal verification based on assume and guarantee approach - a case study (short paper)Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata. 77-80 [doi]
• Multi-clock path analysis using propositional satisfiabilityKazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe. 81-86 [doi]
• Self-reforming routing for stochastic search in VLSI interconnection layoutYukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani. 87-92 [doi]
• An interconnect topology optimization by a tree transformationNaofumi Tsujii, Katsutoshi Baba, Shuji Tsukiyama. 93-98 [doi]
• Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layerTakahiro Deguchi, Tetsushi Koide, Shin ichi Wakabayashi. 99-104 [doi]
• Area routing oriented hierarchical corner stitching with partial binZhang Yan, Wang Baohua, Yici Cai, Xianlong Hong. 105-110 [doi]
• Offline program re-mapping to improve branch prediction efficiency in embedded systemsStephen S. Brown, Jeet Asher, William H. Mangione-Smith. 111-116 [doi]
• Timing driven co-design of networked embedded systemsDinesh Ramanathan, Ravindra Jejurikar, Rajesh K. Gupta. 117-122 [doi]
• Low-power design methodology and applications utilizing dual supply voltagesKimiyoshi Usami, Mutsunori Igarashi. 123-128 [doi]
• Co-synthesis with custom ASICsYuan Xie, Wayne Wolf. 129-134 [doi]
• A new method for constructing IP level power model based on power sensitivityHeng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou. 135-140 [doi]
• A hybrid approach for core-based system-level power modelingTony Givargis, Frank Vahid, Jörg Henkel. 141-146 [doi]
• Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisationAllan Rae, Sri Parameswaran. 147-152 [doi]
• Synthesis of low power folded programmable coefficient FIR digital filters (short paper)Vijay Sundararajan, Keshab K. Parhi. 153-156 [doi]
• Invited talk: synthesis challenges for next-generation high-performance and high-density PLDsJason Cong, Songjie Xu. 157-162 [doi]
• KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath arrayReiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger. 163-168 [doi]
• Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAsByungil Jeong, Sungjoo Yoo, Sunghyun Lee, Kiyoung Choi. 169-174 [doi]
• A new encoding scheme for rectangle packing problemToshihiko Takahashi. 175-178 [doi]
• Analytical minimization of half-perimeter wirelengthAndrew A. Kennings, Igor L. Markov. 179-184 [doi]
• Modeling and minimization of routing congestionMaogang Wang, Majid Sarrafzadeh. 185-190 [doi]
• System-in-package (SIP): challenges and opportunitiesKing L. Tai. 191-196 [doi]
• Taiwan foundry for system-in-package (SIP)Albert Lin. 197-204 [doi]
• Integration of large-scale FPGA and DRAM in a package using chip-on-chip technologyMichael X. Wang, Katsuharu Suzuki, Wayne Wei-Ming Dai, Yee L. Low, Kevin J. O Conner, King L. Tai. 205-210 [doi]
• Modeling and analysis of integrated spiral inductors for RF system-in-packageMinqing Liu, Wayne Wei-Ming Dai. 211-216 [doi]
• Narrow bus encoding for low power systemsYoungsoo Shin, Kiyoung Choi. 217-220 [doi]
• Data transmission over a bus with peak-limited transition activityVijay Sundararajan, Keshab K. Parhi. 221-224 [doi]
• Power analysis and implementation of a low-power 300 MHz 8-b × 8-b pipelined multiplierJinn-Shyan Wang, Po-Hui Yang. 225-228 [doi]
• A new approach to assembly software retargeting for microcontrollersIng-Jer Huang, Dao-Zhen Chen. 229-234 [doi]
• Register allocation for common subexpressions in DSP data pathsRainer Leupers. 235-240 [doi]
• A technique for QoS-based system partitioningJohnson S. Kin, Chunho Lee, William H. Mangione-Smith, Miodrag Potkonjak. 241-246 [doi]
• Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functionsDebatosh Debnath, Tsutomu Sasao. 247-252 [doi]
• An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluationShigeru Yamashita, Hiroshi Sawada, Akira Nagoya. 253-258 [doi]
• Three parameters to find functional decompositionsTsutomu Sasao, Ken-ichi Kurimoto. 259-264 [doi]
• Delay-optimal wiring plan for the microprocessor of high performance computing machinesJun Kikuchi, Tetsuo Sasaki, Tohru Hashimoto, Kazuhisa Miyamoto. 265-270 [doi]
• MMP: a novel placement algorithm for combined macro block and standard cell layout designHong Yu, Xianlong Hong, Yici Cai. 271-276 [doi]
• Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal applicationJason Cong, Tianming Kong, Faming Liang, Jun S. Liu, Wing Hung Wong, Dongmin Xu. 277-282 [doi]
• Symbolic circuit-noise analysis and modeling with determinant decision diagramsXiang-Dong Tan, C.-J. Richard Shi. 283-288 [doi]
• Gate-level aged timing simulation methodology for hot-carrier reliability assuranceYoshiyuki Kawakami, Jingkun Fang, Hirokazu Yonezawa, Nobufusa Iwanishi, Lifeng Wu, Alvin I-Hsien Chen, Norio Koike, Ping Chen, Chune-Sin Yeh, Zhihong Liu. 289-294 [doi]
• Embedded tutorial: subwavelength lithographyTsuneo Terasawa. 295-300 [doi]
• Embedded tutorial: IC design technology for building system-on-a-chipRajesh V. Gupta. 301-302 [doi]
• Thread partitioning method for hardware compiler bachMizuki Takahashi, Nagisa Ishiura, Akihisa Yamada, Takashi Kambe. 303-308 [doi]
• An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper)Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki. 309-312 [doi]
• A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper)Taewhan Kim, Junhyung Um. 313-316 [doi]
• Communicating logic: an alternative embedded stream processing paradigmNorbert Imlig, Ryusuke Konishi, Tsunemichi Shiozawa, Kiyoshi Oguri, Kouichi Nagami, Hideyuki Ito, Minoru Inamori, Hiroshi Nakada. 317-322 [doi]
• A scheduling and allocation method to reduce data transfer time by dynamic reconfigurationKazuhito Ito. 323-328 [doi]
• Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talkMasakazu Yamashina, Masato Motomura. 329-332 [doi]
• Power reduction by simultaneous voltage scaling and gate sizingChunhong Chen, Majid Sarrafzadeh. 333-338 [doi]
• Analysis of power-clocked CMOS with application to the design of energy-recovery circuitsMassoud Pedram, Xunwei Wu. 339-344 [doi]
• Low-power design of sequential circuits using a quasi-synchronous derived clockXunwei Wu, Jian Wei, Massoud Pedram, Qing Wu. 345-350 [doi]
• FSM decomposition by direct circuit manipulation applied to low power designJosé C. Monteiro, Arlindo L. Oliveira. 351-358 [doi]
• Timing closure: the solution and its problemsRaul Camposano, Olivier Coudert, Patrick Groeneveld, Leon Stok, Ralph H. J. M. Otten. 359-364 [doi]
• High performance of short-channel MOSFETs due to an elevated central-channel dopingMasayasu Tanaka, N. Tokida, T. Okagaki, Michiko Miura-Mattausch, Walter Hansch, Hans Jürgen Mattausch. 365-370 [doi]
• Circuit performance oriented device optimization using BSIM3 pre-silicon model parametersMikako Miyama, Shiro Kamohara. 371-374 [doi]
• Design for manufacturability: a path from system level to high yielding chips: embedded tutorialAndrzej J. Strojwas. 375-376 [doi]
• Low-power silicon architecture for wireless communications: embedded tutorialJan M. Rabaey. 377-380 [doi]
• Run-time power control scheme using software feedback loop for low-power real-time applicationSeongsoo Lee, Takayasu Sakurai. 381-386 [doi]
• An interleaved dual-battery power supply for battery-operated electronicsQing Wu, Qinru Qiu, Massoud Pedram. 387-390 [doi]
• embedded system design with multiple languages: embedded tutorialRolf Ernst, Ahmed Amine Jerraya. 391-396 [doi]
• Symbolic debugging of globally optimized behavioral specificationsInki Hong, Darko Kirovski, Miodrag Potkonjak, Marios C. Papaefthymiou. 397-400 [doi]
• Fast development of source-level debugging system using hardware emulation (short paper)Sang-Joon Nam, Jun-Hee Lee, Byoung-Woon Kim, Yeon-Ho Im, Young-Su Kwon, Kyong-Gu Kang, Chong-Min Kyung. 401-404 [doi]
• Methodology for hardware/software co-verification in C/C++ (short paper)Luc Séméria, Abhijit Ghosh. 405-408 [doi]
• Performance-optimal clustering with retiming for sequential circuitsTzu-Chieh Tien, Youn-Long Lin. 409-414 [doi]
• IBAW: an implication-tree based alternative-wiring logic transformation algorithmWangning Long, Yu-Liang Wu, Jinian Bian. 415-422 [doi]
• On mixture density and maximum likelihood power estimation via expectation-maximizationRamamurti Chandramouli, Vamsi K. Srikantam. 423-428 [doi]
• Edge separability based circuit clustering with application to circuit partitioningJason Cong, Sung Kyu Lim. 429-434 [doi]
• Feasible two-way circuit partitioning with complex resource constraintsHsun-Cheng Lee, Ting-Chi Wang. 435-440 [doi]
• Performance driven multiway partitioningJason Cong, Sung Kyu Lim. 441-446 [doi]
• Hierarchical computation of 3-D interconnect capacitance using direct boundary element methodJiangchun Gu, Zeyi Wang, Xianlong Hong. 447-452 [doi]
• A simplified hybrid method for calculating the frequency-dependent inductances of transmission lines with rectangular cross sectionShuzhou Fang, Xiaobo Tang, Zeyi Wang, Xianlong Hong. 453-456 [doi]
• An analytic calculation method for delay time of RC-class interconnectsW. K. Kal, S. Y. Kim. 457-462 [doi]
• A new efficient waveform simulation method for RLC interconnect via amplitude and phase approximationXiaodong Yang, Walter H. Ku, Chung-Kuan Cheng. 463-468 [doi]
• Optimization of VDD and VTH for low-power and high speed applicationsKoichi Nose, Takayasu Sakurai. 469-474 [doi]
• Compact yet high performance (CyHP) library for short time-to-market with new technologiesNguyen Minh Duc, Takayasu Sakurai. 475-480 [doi]
• A new CMAC neural network architecture and its ASIC realizationYuan-Bao Hsu, Kao-Shing Hwang, Chien-Yuan Pao, Jinn-Shyan Wang. 481-484 [doi]
• Retargetable estimation scheme for DSP architecture selectionNaji Ghazal, A. Richard Newton, Jan M. Rabaey. 485-490 [doi]
• Data memory minimization by sharing large size buffersHyunok Oh, Soonhoi Ha. 491-496 [doi]
• Array allocation taking into account SDRAM characteristicsHong-Kai Chang, Youn-Long Lin. 497-502 [doi]
• Causality based generation of directed test casesNina Saxena, Jacob A. Abraham, Avijit Saha. 503-508 [doi]
• Fault models and test generation for IDDQ testing: embedded tutorialYoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita. 509-514 [doi]
• Issues on SOC testing in DSM area: embedded tutorialTakashi Aikyo. 515-516 [doi]
• A cell synthesis method for salicide processKazuhisa Okada, Takayuki Yamanouchi, Takashi Kambe. 517-522 [doi]
• Monte-Carlo algorithms for layout density controlYu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky. 523-528 [doi]
• Layout generation of array cell for NMOS 4-phase dynamic logic (short paper)Makoto Furuie, Bao-Yu Song, Yukihiro Yoshida, Takao Onoye, Isao Shirakawa. 529-532 [doi]
• A new efficient method for substrate-aware device-level placement (short paper)C. Lin, D. M. W. Leenaerts. 533-536 [doi]
• The enchancing of efficiency of the harmonic balance analysis by adaptation of preconditioner to circuit nonlinearityMark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Kiran K. Gullapalli, Brian J. Mulvaney. 537-540 [doi]
• Analog-testability analysis by determinant-decision-diagrams based symbolic analysisTao Pi, C.-J. Richard Shi. 541-546 [doi]
• A method for linking process-level variability to system performancesTomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru. 547-552 [doi]
• Design challenges for 0.1um and beyond: embedded tutorialTakayasu Sakurai. 553-558 [doi]
• A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphicsYoung-Su Kwon, In-Cheol Park, Chong-Min Kyung. 559-564 [doi]
• Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystemJin-Hua Hong, Cheng-Wen Wu. 565-570 [doi]
• An introduction to SLDL and RosettaSteven E. Schultz. 571-572 [doi]
• SystemC standardGuido Arnout. 573-578 [doi]
• Java based object oriented hardware specification and synthesisTommy Kuhn, Wolfgang Rosenstiel. 579-582 [doi]
• Superlog, a unified design language for system-on-chipPeter Flake, Simon J. Davidmann. 583-586 [doi]
• Performance sensitivity analysis using statistical method and its applications to delayJing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, Deb Aditya Mukherjee, Sandip Kundu. 587-592 [doi]
• A testability metric for path delay faults and its applicationHuan-Chih Tsai, Kwang-Ting Cheng, Vishwani D. Agrawal. 593-598 [doi]
• A non-scan DFT method at register-transfer level to achieve complete fault efficiencySatoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara. 599-604 [doi]
• A sigma-delta modulation based BIST scheme for mixed-signal circuitsJiun-Lang Huang, Kwang-Ting Cheng. 605-612 [doi]
• A 12b 50 MHz 3.3V CMOS acquisition time minimized A/D converterYoung-Deuk Jeon, Byeong-Lyeol Jean, Seung-Chul Lee, Sang-Min Yoo, Seung-Hoon Lee. 613-616 [doi]
• A benchmark suite for substrate analysisEdoardo Charbon, Luis Miguel Silveira, Paolo Miliozzi. 617-622 [doi]
• Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorialMakoto Nagata, Atsushi Iwata. 623-630 [doi]
• Importance of CAD tools and methodology in high speed CPU design: invited talkHaruyuki Tago, Kazuhiro Hashimoto, Nobuyuki Ikumi, Masato Nagamatsu, Masakazu Suzuoki, Yasuyuki Yamamoto. 631-634 [doi]
• 300MHz design methodology of VU for emotion synthesisTakayuki Kamei, Hideaki Takeda, Yukio Ootaguro, Takayoshi Shimazawa, Kazuhiko Tachibana, Shin ichi Kawakami, Seiji Norimatsu, Fujio Ishihara, Toshinori Sato, Hiroaki Murakami, Nobuhiro Ide, Yukio Endo, Akira Aono, Atsushi Kunimatsu. 635-640 [doi]
• Repeater insertion method and its application to a 300MHz 128-bit 2-way superscalar microprocessorNorman Kojima, Yukiko Parameswar, Christian Klingner, Yukio Ohtaguro, Masataka Matsui, Shigeaki Iwasa, Tatsuo Teruyama, Takayoshi Shimazawa, Hideki Takeda, Kouji Hashizume, Haruyuki Tago, Masaaki Yamada. 641-646 [doi]
• Clock design of 300MHz 128-bit 2-way superscalar microprocessorFujio Ishihara, Christian Klinger, Ken-ichi Agawa. 647-652 [doi]
• One language or more?: how can we design an SoC at a system level?Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura. 653-654 [doi]
• Circuit partitioning with coupled logic restructuring techniquesYu-Liang Wu, Xiao-Long Yuan, David Ihsin Cheng. 655-660 [doi]
• Improved algorithms for hypergraph bipartitioningAndrew E. Caldwell, Andrew B. Kahng, Igor L. Markov. 661-666 [doi]
• Multi-way partitioning using bi-partition heuristicsMaogang Wang, Sung Lim, Jason Cong, Majid Sarrafzadeh. 667 [doi]