Akira Nagoya - researchr alias

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Viewing Publication 1 - 32 from 32

2022

Convolutional neural network implementations using Vitis AIAkihiko Ushiroyama, Minoru Watanabe, Nobuya Watanabe, Akira Nagoya. ccwc 2022: 365-371 [doi]

2018

Acceleration of Analysis Processing on Decentralized Performance Profiling System Using Virtual MachinesMasao Yamamoto, Kohta Nakashima, Toshihiro Yamauchi, Akira Nagoya, Hideo Taniguchi. ic-nc 2018: 152-158 [doi]

2007

Network Processor for High-Speed Network and Quick ProgrammingTakahiro Murooka, Akira Nagoya, Toshiaki Miyazaki, Hiroyuki Ochi, Yukihiro Nakamura. jcsc, 16(1):65-79, 2007. [doi]

2004

Dynamically Reconfigurable Logic LSI: PCA-2Hideyuki Ito, Ryusuke Konishi, Hiroshi Nakada, Hideyuki Tsuboi, Yuichi Okuyama, Akira Nagoya. ieicet, 87-D(8):2011-2020, 2004. [doi]

2003

Concept and implementation of run-time resource management system operating on autonomously reconfigurable architectureYoshiki Nakane, Kouichi Nagami, Tsunemichi Shiozawa, Akira Nagoya. fpt 2003: 136-143 [doi]

Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCAKiyoshi Oguri, Yuichiro Shibata, Akira Nagoya. APCSAC 2003: 54-68 [doi]

2002

A Method of Mapping Finite State Machine into PCA Plastic PartsMinoru Inamori, Hiroshi Nakada, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri. ieiceta, 85-A(4):804-810, 2002. [doi]

2001

2000

1999

A Method for Implementing Fractal Image Compression on Reconfigurable ArchitectureAkihiro Matsuura, Hidehisa Nagano, Akira Nagoya. fpga 1999: 251 [doi]

Summation Algorithms on Constrained Reconfigurable MeshesAkihiro Matsuura, Akira Nagoya. ispan 1999: 400-405 [doi]

Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing ApproachHidehisa Nagano, Takayuki Suyama, Akira Nagoya. aspdac 1999: 161-164 [doi]

An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable ArchitectureHidehisa Nagano, Akihiro Matsuura, Akira Nagoya. ipps 1999: 670-678

Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation HeuristicTakayuki Suyama, Makoto Yokoo, Akira Nagoya. ipps 1999: 709-711

Solving Satisfiability Problems on FPGAs Using Experimental Unit PropagationTakayuki Suyama, Makoto Yokoo, Akira Nagoya. cp 1999: 434-445

An Integrated Approach for Synthesizing LUT NetworksShigeru Yamashita, Hiroshi Sawada, Akira Nagoya. glvlsi 1999: 136-139 [doi]

1998

Soft Decision Maximum Likelihood Decoders for Binary Linear Block Codes Implemented on FPGAs (Abstract)Hidehisa Nagano, Takayuki Suyama, Akira Nagoya. fpga 1998: 261 [doi]

Restructuring Logic Representations with Easily Detectable Simple Disjunctive DecompositionsHiroshi Sawada, Shigeru Yamashita, Akira Nagoya. date 1998: 755 [doi]

New Methods to Find Optimal Non-Disjoint Bi-DecompositionsShigeru Yamashita, Hiroshi Sawada, Akira Nagoya. aspdac 1998: 59-68

1997

A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-ProcessorShinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya. codes 1997: 147-152 [doi]

Formulation of the Addition-Shift-Sequence Problem and Its ComplexityKaihiro Matsuura, Akira Nagoya. isaac 1997: 42-51

Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric VariablesHiroshi Sawada, Shigeru Yamashita, Akira Nagoya. glvlsi 1997: 39-44 [doi]

1996

LUT-based FPGA Technology Mapping using Permissible FunctionsTakayuki Suyama, Hiroshi Sawada, Akira Nagoya. vlsid 1996: 215-218 [doi]

A new method to express functional permissibilities for LUT based FPGAs and its applicationsShigeru Yamashita, Hiroshi Sawada, Akira Nagoya. iccad 1996: 254-261 [doi]

1995

Logic synthesis for look-up table based FPGAs using functional decomposition and support minimizationHiroshi Sawada, Takayuki Suyama, Akira Nagoya. iccad 1995: 353-358 [doi]

1990

Multi-Level Optimization for Large Scale ASICSAkira Nagoya, Yukihiro Nakamura, Kiyoshi Oguri, Ryo Nomura. iccad 1990: 564-567

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1990

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