Kazuo Nakajima - researchr alias

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Viewing Publication 1 - 33 from 33

2006

A New Approach to Online FPGA PlacementMitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, Kazuo Nakajima, Katsumasa Watanabe. ciss 2006: 145-150 [doi]

An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAsMitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, Kazuo Nakajima, Katsumasa Watanabe. ieicet, 89-A(12):3416-3426, 2006. [doi]

2003

2002

A Component Architecture for FPGA-Based, DSP System DesignGary Spivey, Shuvra S. Bhattacharyya, Kazuo Nakajima. asap 2002: 41 [doi]

2000

A Threshold Logic-Based Reconfigurable Logic Element with a New Programming TechnologyKazuo Aoyama, Hiroshi Sawada, Akira Nagoya, Kazuo Nakajima. fpl 2000: 665-674 [doi]

1999

SEGRA: a very fast general area router for multichip modulesYoung-Jun Cha, Chong S. Rim, Kazuo Nakajima. tcad, 18(5):659-665, 1999. [doi]

A Graph Theoretical Approach for the Yield Enhancement of Reconfigurable VLSI/WSI ArraysJagannathan Narasimhan, Kazuo Nakajima, Chong S. Rim. DAM, 90(1-3):195-221, 1999. [doi]

Maximum/minimum detection by a module-based neural network with redundant architectureKazuyoshi Tsutsumi, Kazuo Nakajima. ijcnn 1999: 558-561 [doi]

1997

A simple and effective greedy multilayer router for MCMsYoung-Jun Cha, Chong S. Rim, Kazuo Nakajima. ispd 1997: 67-72 [doi]

1995

Min-cut placement with global objective functions for large scale sea-of-gates arraysKazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai, Koji Sato. tcad, 14(4):434-446, 1995. [doi]

1994

1993

A Reconfiguration-Based Yield Enhancement SystemJagannathan Narasimhan, Kazuo Nakajima. iccd 1993: 224-228

1992

1991

Polynomial time algorithms on circular-arc overlap graphsToshinobu Kashiwabara, Sumio Masuda, Kazuo Nakajima, Toshio Fujisawa. networks, 21(2):195-203, 1991. [doi]

A New Model for Over-The-Cell Channel Routing with Three LayersMasayuki Terai, Kazuhiro Takahashi, Kazuo Nakajima, Koji Sato. iccad 1991: 432-435

1990

A linear time algorithm for optimal CMOS functional cell layoutsPo-Yang F. Lin, Kazuo Nakajima. iccd 1990: 449-453 [doi]

Crossing Minimization in Linear Embeddings of GraphsSumio Masuda, Kazuo Nakajima, Toshinobu Kashiwabara, Thio Fujisawa. TC, 39(1):124-127, 1990.

Efficient algorithms for finding maximum cliques of an overlap graphSumio Masuda, Kazuo Nakajima, Toshinobu Kashiwabara, Toshio Fujisawa. networks, 20(2):157-171, 1990. [doi]

1989

Graph Bipartization and via MinimizationHyeong-Ah Choi, Kazuo Nakajima, Chong S. Rim. siamdm, 2(1):38-47, 1989.

The Via Minimization Problem is NP-CompleteNicholas J. Naclerio, Sumio Masuda, Kazuo Nakajima. TC, 38(11):1604-1608, 1989.

Exact algorithms for multilayer topological via minimizationChong S. Rim, Toshinobu Kashiwabara, Kazuo Nakajima. tcad, 8(11):1165-1173, 1989. [doi]

1988

An Optimal Algorithm for Finding a Maximum Independent Set of a Circular-Arc GraphSumio Masuda, Kazuo Nakajima. SICOMP, 17(1):41-52, 1988.

1987

Via Minimization for Gridless LayoutsNicholas J. Naclerio, Sumio Masuda, Kazuo Nakajima. dac 1987: 159-165 [doi]

1986

An Algorithm for Determining the Fault Diagnosability of a SystemJagannathan Narasimhan, Kazuo Nakajima. TC, 35(11):1004-1008, 1986.

1984

On Adaptive System DiagnosisS. Louis Hakimi, Kazuo Nakajima. TC, 33(3):234-240, 1984.

1982

Complexity Results for Scheduling Tasks with Discrete Starting TimesKazuo Nakajima, S. Louis Hakimi. jal, 3(4):344-361, 1982.

1980

Traffic Assistance Service System for ESSHideo Yabe, Yoshisuke Shimizu, Chikara Iwata, Kazuo Nakajima. tcom, 28(1):117-122, 1980. [doi]

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