Abstract is missing.
- The Rising Wave of Field ProgrammabilityTsugio Makimoto. 1-6 [doi]
- Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCSSriram Govindarajan, Ranga Vemuri. 7-18 [doi]
- A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol CharacterizationJohan Ditmar, Kjell Torkelsson, Axel Jantsch. 19-28 [doi]
- A Compiler Directed Approach to Hiding Configuration Latency in Chameleon ProcessorsXinan Tang, Manning Aalsma, Raymond Jou. 29-38 [doi]
- Reconfigurable Network Processors Based on Field Programmable System Level Integrated CircuitsMarios Iliopoulos, Theodore Antonakopoulos. 39-47 [doi]
- Internet Connected FPLHamish Fallside, Michael John Sebastian Smith. 48-57 [doi]
- Field Programmable Communication Emulation and Optimization for Embedded System DesignFrank-Michael Renner, Jürgen Becker, Manfred Glesner. 58-67 [doi]
- FPGA-Based Emulation: Industrial and Custom Prototyping SolutionsHelena Krupnova, Gabriele Saucier. 68-77 [doi]
- FPGA-Based Prototyping for Product DefinitionRainer Kress, Andreas Pyttel, Alexander Sedlmeier. 78-86 [doi]
- Implementation of Virtual Circuits by Means of the FIPSOC DevicesE. Cantó, Juan Manuel Moreno, Joan Cabestany, I. Lacadena, Josep Maria Insenser. 87-95 [doi]
- Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCTJörn Gause, Peter Y. K. Cheung, Wayne Luk. 96-105 [doi]
- A Self-Reconfigurable Gate Array ArchitectureReetinder P. S. Sidhu, Sameer Wadhwa, Alessandro Mei, Viktor K. Prasanna. 106-120 [doi]
- Multitasking on FPGA CoprocessorsHarald Simmler, L. Levinson, Reinhard Männer. 121-130 [doi]
- Design Visualisation for Dynamically Reconfigurable SystemsMilan Vasilko. 131-140 [doi]
- Verification of Dynamically Reconfigurable LogicDavid Robinson, Patrick Lysaght. 141-150 [doi]
- Design of a Fault Tolerant FPGAT. Bartzick, M. Henze, J. Kickler, K. Woska. 151-156 [doi]
- Real-Time Face Detection on a Configurable Hardware SystemRob McCready. 157-162 [doi]
- Multifunctional Programmable Single-Board CAN Monitoring ModulePetr Pfeifer. 163-168 [doi]
- Self-Testing of Linear Segments in User-Programmed FPGAsPawel Tomaszewicz. 169-174 [doi]
- Implementing a Fieldbus Interface Using an FPGAG. Lías, María Dolores Valdés, Miguel A. Domínguez, María José Moure. 175-180 [doi]
- Area-Optimized Technology Mapping for Hybrid FPGAsSrini Krishnamoorthy, Sriram Swaminathan, Russell Tessier. 181-190 [doi]
- CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAsJoerg Abke, Erich Barke. 191-200 [doi]
- Efficient Embedding of Partitioned Circuits onto Multi-FPGA BoardsSushil Chandra Jain, Anshul Kumar, Shashi Kumar. 201-210 [doi]
- A Placement Algorithm for FPGA Designs with Multiple I/O StandardsJason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman. 211-220 [doi]
- A Mapping Methodology for Code Trees onto LUT-Based FPGAsHolger Kropp, Carsten Reuter. 221-229 [doi]
- Possibilities and Limitations of Applying Evolvable Hardware to Real-World ApplicationsJim Torresen. 230-239 [doi]
- A Co-processor System with a Virtex FPGA for Evolutionary ComputationYoshiki Yamaguchi, Akira Miyashita, Tsutomu Maruyama, Tsutomu Hoshino. 240-249 [doi]
- System Design with Genetic AlgorithmsChristine Bauer, Peter Zipf, Hans Wojtkowiak. 250-259 [doi]
- Implementing Kak Neural Networks on a Reconfigurable Computing PlatformJihan Zhu, George J. Milne. 260-269 [doi]
- Compact Spiking Neural Network Implementation in FPGASelene Maya, Rocio Reynoso, César Torres, Miguel Arias-Estrada. 270-276 [doi]
- Silicon Platforms for the Next Generation Wireless Systems - What Role Does Reconfigurable Hardware Play?Jan M. Rabaey. 277-285 [doi]
- From Reconfigurability to Evolution in Construction Systems: Spanning the Electronic, Microfluidic and Biomolecular DomainsJohn S. McCaskill, Patrick Wagler. 286-299 [doi]
- A Specific Test Methodology for Symmetric SRAM-Based FPGAsMichel Renovell. 300-311 [doi]
- DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications ApplicationsJürgen Becker, Thilo Pionteck, Manfred Glesner. 312-321 [doi]
- Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Re-configurable LogicA. Blaickner, O. Nagy, Herbert Grünbacher. 322-331 [doi]
- Software Radio Reconfigurable Hardware System (SHaRe)Xavier Revés, Antoni Gelonch, Ferran Casadevall, José L. García. 332-341 [doi]
- Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet TransformJavier Ramírez, Antonio García, Pedro G. Fernández, Luis Parrilla, Antonio Lloris-Ruíz. 342-351 [doi]
- Partial Run-Time Reconfiguration Using JRTRScott McMillan, Steve Guccione. 352-360 [doi]
- A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable SystemsXue-Jie Zhang, Kam-Wing Ng, Wayne Luk. 361-370 [doi]
- A Hybrid Prototyping Platform for Dynamically Reconfigurable DesignsTero Rissa, Jarkko Niittylahti. 371-378 [doi]
- Task Rearrangement on Partially Reconfigurable FPGAs with Restricted BufferHossam A. ElGindy, Martin Middendorf, Hartmut Schmeck, Bernd Schmidt. 379-388 [doi]
- Generation of Design Suggestions for Coarse-Grain Reconfigurable ArchitecturesReiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger. 389-399 [doi]
- Mapping of DSP Algorithms on Field Programmable Function ArraysPaul M. Heysters, Jaap Smit, Gerard J. M. Smit, Paul J. M. Havinga. 400-411 [doi]
- On Availability of Bit-Narrow Operations in General-Purpose ApplicationsDarko Stefanovic, Margaret Martonosi. 412-421 [doi]
- A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix MultipliersRadhika S. Grover, Weijia Shang, Qiang Li. 422-431 [doi]
- A New Floorplanning Method for FPGA Architectural ResearchFrank Wolz, Reiner Kolla. 432-442 [doi]
- Efficient Self-Reconfigurable Implementations Using On-chip MemorySameer Wadhwa, Andreas Dandalis. 443-448 [doi]
- Design and Implementation of an XC6216 FPGA Model in VerilogAlexander Glasmacher, Kai Woska. 449-455 [doi]
- Reusable DSP Functions in FPGAsJernej Andrejas, Andrej Trost. 456-461 [doi]
- A Parallel Pipelined SAT Solver for FPGAsM. Redekopp, Andreas Dandalis. 462-468 [doi]
- A Multi-node Dynamic Reconfigurable Computing System with Distributed Reconfiguration ControllerAbdellah Touhafi. 469-474 [doi]
- A Reconfigurable Stochastic Model Simulator for Analysis of Parallel SystemsOu Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano. 475-484 [doi]
- A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera SystemStephen J. Bellis, William P. Marnane. 485-494 [doi]
- Reconfigurable Computing for Speech Recognition: Preliminary FindingsStephen J. Melnikoff, Philip James-Roxby, Steven F. Quigley, Martin J. Russell. 495-504 [doi]
- Security Upgrade of Existing ISDN Devices by Using Reconfigurable LogicHagen Ploog, Mathias Schmalisch, Dirk Timmermann. 505-514 [doi]
- The Fastest Multiplier on FPGAs with Redundant Binary RepresentationTakahiro Miomo, Koichi Yasuoka, Masanori Kanazawa. 515-524 [doi]
- High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAsRolf Enzler, Tobias Jeger, Didier Cottet, Gerhard Tröster. 525-534 [doi]
- Balancing Logic Utilization and Area Efficiency in FPGAsRussell Tessier, Heather Giza. 535-544 [doi]
- Performance Penalty for Fault Tolerance in Roving STARsJohn M. Emmert, Charles E. Stroud, Jason A. Cheatham, Andrew M. Taylor, Pankaj Kataria, Miron Abramovici. 545-554 [doi]
- Optimum Functional Decomposition for LUT-Based FPGA SynthesisJian Qiao, Makoto Ikeda, Kunihiro Asada. 555-564 [doi]
- Optimization of Run-Time Reconfigurable Embedded SystemsMichael Eisenring, Marco Platzner. 565-574 [doi]
- It s FPL, Jim - But Not as We Know It! Opportunities for the New Commercial ArchitecturesTom Kean. 575-584 [doi]
- Reconfigurable Systems: New Activities in AsiaHideharu Amano, Yuichiro Shibata, Masaki Uno. 585-594 [doi]
- StReAm: Object-Oriented Programming of Stream Architectures Using PAM-BloxOskar Mencer, Heiko Hübert, Martin Morf, Michael J. Flynn. 595-604 [doi]
- Stream Computations Organized for Reconfigurable Execution (SCORE)Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon. 605-614 [doi]
- Memory Access Schemes for Configurable ProcessorsHolger Lange, Andreas Koch. 615-625 [doi]
- Generating Addresses for Multi-dimensional Array Access in FPGA On-chip MemoryAndreas C. Döring, Gunther Lustig. 626-635 [doi]
- Combining Serialisation and Reconfiguration for FPGA DesignsArran Derbyshire, Wayne Luk. 636-645 [doi]
- Multiple-Wordlength Resource BindingGeorge A. Constantinides, Peter Y. K. Cheung, Wayne Luk. 646-655 [doi]
- Automatic Temporal Floorplanning with Guaranteed Solution FeasibilityMilan Vasilko, Graham Benyon-Tinker. 656-664 [doi]
- A Threshold Logic-Based Reconfigurable Logic Element with a New Programming TechnologyKazuo Aoyama, Hiroshi Sawada, Akira Nagoya, Kazuo Nakajima. 665-674 [doi]
- Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAsAndrzej Krasniewski. 675-684 [doi]
- Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual HardwareAtsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hideharu Amano. 685-694 [doi]
- Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and SynthesisBernardo Kastrup, Jeroen Trum, Orlando Moreira, Jan Hoogerbrugge, Jef L. van Meerbergen. 695-706 [doi]
- Behavioural Language Compilation with Virtual Hardware ManagementOliver Diessel, George J. Milne. 707-717 [doi]
- Synthesis and Implementation of RAM-Based Finite State Machines in FPGAsValery Sklyarov. 718-728 [doi]
- Evaluation of Accelerator Designs for Subgraph Isomorphism ProblemShuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangtham Udorn, Kouji Konishi. 729-738 [doi]
- The Implementation of Synchronous Dataflow Graphs Using Reconfigurable HardwareMartyn Edwards, Peter Green. 739-748 [doi]
- Multiplexer Based Reconfiguration for Virtex MultipliersTim Courtney, Richard H. Turner, Roger Woods. 749-758 [doi]
- Efficient Building of Word Recongnizer in FPGAs for Term-Document Matrices ConstructionChristophe Bobda, Thomas Lehmann. 759-768 [doi]
- Reconfigurable Computing between Classifications and Metrics - The Approach of Space/Time-SchedulingChristian Siemers. 769-772 [doi]
- FPGA Implementation of a Prototype WDM On-Line SchedulerWinnie W. Cheng, Steven J. E. Wilton, Babak Hamidzadeh. 773-776 [doi]
- An FPFA Based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard-Time SystemsJens Hildebrandt, Dirk Timmermann. 777-780 [doi]
- Formal Verification of a Reconfigurable MicroprocessorSergej Sawitzki, Jens Schönherr, Rainer G. Spallek, Bernd Straube. 781-784 [doi]
- The Role of the Embedded Memories in the Implementation of Artificial Neural NetworksRafael Gadea Gironés, Vicente Herrero, Angel Sebastia, Antonio Mocholí Salcedo. 785-788 [doi]
- Programmable System Level Integration Brings System-on-Chip Design to the DesktopGuy Lecurieux Lafayette. 789-792 [doi]
- On Applying Software Development Best Practice to FPFAs in Safety Critical SystemsA. Hilton, J. Hall. 793-796 [doi]
- Pre-route Assistant: A Routing Tool for Run-Time ReconfigurationBrandon Blodget. 797-800 [doi]
- High Speed Computation of Lattice gas Automata with FPFATomoyoshi Kobori, Tsutomu Maruyama, Tsutomu Hoshino. 801-804 [doi]
- An Implementation of Longest Prefix Matching for IP Router on Plastic Cell ArchitectureTsunemichi Shiozawa, Norbert Imlig, Kouichi Nagami, Kiyoshi Oguri, Akira Nagoya, Hiroshi Nakada. 805-809 [doi]
- FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational NumbersBogdan Matasaru, Tudor Jebelean. 810-813 [doi]
- Toward Uniform Approach to Design of Evolvable Hardware Based SystemsLukás Sekanina, Azeddien M. Sllame. 814-817 [doi]
- Educational Programmable Hardware Prototyping and Verification SystemAndrej Trost, Andrej Zemva, Baldomir Zajc. 818-821 [doi]
- A Stream Processor Architecture Based on the Configurable CEPRA-SRolf Hoffmann, Bernd Ulmann, Klaus-Peter Völkmann, Stefan Waldschmidt. 822-825 [doi]
- An Innovative Approach to Couple EDA Tools with Reconfigurable HardwareUwe Hatnik, Jürgen Haufe, Peter Schwarz. 826-829 [doi]
- FPL Curriculum at Tallinn Technical UniversityKalle Tammemäe, T. Evartson. 830-833 [doi]
- The Modular Architecture of SYNTHUP, FPFA Based PCI Board for Real-Time Sound Synthesis and Digital Signal ProcessingJean-Michel Raczinski, Stéphane Sladek. 834-837 [doi]
- A Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network ProcessorAndré Brinkmann, Dominik Langen, Ulrich Rückert. 838-841 [doi]
- Configuration Prefetching for Non-deterministic Event Driven Multi-context SchedulersJuanjo Noguera, Rosa M. Badia. 842-845 [doi]
- Wireless Base Station Design Using a Reconfigurable Communications ProcessorChris Phillips. 846-848 [doi]
- Placement of Linear ArraysErwan Fabiani, Dominique Lavenier. 849-852 [doi]