M. Redekopp, Andreas Dandalis. A Parallel Pipelined SAT Solver for FPGAs. In Reiner W. Hartenstein, Herbert Grünbacher, editors, Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings. Volume 1896 of Lecture Notes in Computer Science, pages 462-468, Springer, 2000. [doi]
Abstract is missing.