Antonio Lloris-Ruíz - researchr alias

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Viewing Publication 1 - 27 from 27

2017

A new area-efficient BCD-digit multiplierEncarnación Castillo, Antonio Lloris-Ruíz, Diego P. Morales, Luis Parrilla, Antonio García, Guillermo Botella. dsp, 62:1-10, 2017. [doi]

2016

Comments on "Fast architecture for decimal digit multiplication"Encarnación Castillo, Antonio Lloris-Ruíz, Antonio García, Luis Parrilla, Diego P. Morales. mam, 47:441-444, 2016. [doi]

2007

IPP@HDL: Efficient Intellectual Property Protection Scheme for IP CoresEncarnación Castillo, Uwe Meyer-Bäse, Antonio García, Luis Parrilla, Antonio Lloris-Ruíz. tvlsi, 15(5):578-591, 2007. [doi]

Intellectual Property Protection of HDL IP Cores Through Automated Sognature HostingEncarnación Castillo, Luis Parrilla, Antonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz. fpl 2007: 183-188 [doi]

2006

IPP Watermarking Technique for IP Core Protection on FPL DevicesEncarnación Castillo, Luis Parrilla, Antonio García, Antonio Lloris-Ruíz, Uwe Meyer-Bäse. fpl 2006: 1-6 [doi]

2005

Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter BanksAntonio García, Javier Ramírez, Uwe Meyer-Bäse, Encarnación Castillo, Antonio Lloris-Ruíz. fpl 2005: 531-534

Efficient Clock Distribution Scheme for VLSI RNS-Enabled ControllersDaniel González, Luis Parrilla, Antonio García, Encarnación Castillo, Antonio Lloris-Ruíz. patmos 2005: 657-665 [doi]

2004

Intellectual Property Protection for RNS Circuits on FPGAsLuis Parrilla, Encarnación Castillo, Antonio García, Antonio Lloris-Ruíz. fpl 2004: 1139-1141 [doi]

2003

2002

A New Methodology for Efficient Synchronization of RNS-Based VLSI SystemsDaniel González, Antonio García, Graham A. Jullien, Javier Ramírez, Luis Parrilla, Antonio Lloris-Ruíz. patmos 2002: 188-197 [doi]

2001

Implementation of the one dimensional discrete cosine transform using the residue number systemPedro G. Fernández, Javier Ramírez 0001, Antonio García 0001, Luis Parrilla 0001, Antonio Lloris-Ruíz. icecsys 2001: 433-436 [doi]

Design of RNS-based distributed arithmetic DWT filterbanksJavier Ramírez, Antonio García, Uwe Meyer-Bäse, Fred J. Taylor, Pedro G. Fernández, Antonio Lloris-Ruíz. icassp 2001: 1193-1196 [doi]

2000

A new architecture to compute the discrete cosine transform using the quadratic residue number systemJ. Ramirez, A. Garcia, Pedro G. Fernández, Luis Parrilla, Antonio Lloris-Ruíz. iscas 2000: 321-324 [doi]

Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet TransformJavier Ramírez, Antonio García, Pedro G. Fernández, Luis Parrilla, Antonio Lloris-Ruíz. fpl 2000: 342-351 [doi]

1999

A Look-Up Scheme for Scaling in the RNSAntonio García, Antonio Lloris-Ruíz. TC, 48(7):748-751, 1999.

RNS implementation of FIR filters based on distributed arithmetic using field-programmable logicAntonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz, Fred J. Taylor. iscas 1999: 486-489 [doi]

Using PVM for Distributed Logic Minimization in a Network of ComputersLuis Parrilla, Julio Ortega, Antonio Lloris-Ruíz. pvm 1999: 541-548 [doi]

1998

Pipelined RNS multipliers: an application to scalingAntonio García 0001, Antonio Lloris-Ruíz. icecsys 1998: 55-58 [doi]

Testability of AND-EXOR logic vs. AND-OR logicLuis Parrilla 0001, Julio Ortega, Antonio Lloris-Ruíz. icecsys 1998: 213-216 [doi]

1997

Modified Boltzmann Machine for an Efficient Distributed ImplementationJulio Ortega, Luis Parrilla, Alberto Prieto, Antonio Lloris-Ruíz, Carlos García Puntonet. iwann 1997: 1221-1232

1993

1991

Optimization Problems on Concurrent Testing Solved by Neural NetworksJulio Ortega, Alberto Prieto, Francisco J. Pelayo, Antonio Lloris-Ruíz, P. Martin-Smith. iwann 1991: 385-400

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