Abstract is missing.
- FPGAs and the Era of Field ProgrammabilityWim Roelandts. 1 [doi]
- Reconfigurable Systems EmergeNick Tredennick, Brion Shimamoto. 2-11 [doi]
- System-Level Design Tools Can Provide Low Cost Solutions in FPGAs: TRUE or FALSE?Mark Dickinson. 12 [doi]
- Hardware Accelerated Novel Protein IdentificationAnish Alex, Jonathan Rose, Ruth Isserlin-Weinberger, Christopher W. V. Hogue. 13-22 [doi]
- Large Scale Protein Sequence Alignment Using FPGA Reprogrammable Logic DevicesStefan Dydel, Piotr Bala. 23-32 [doi]
- A Key Management Architecture for Securing Off-Chip Data TransfersJonathan Graf, Peter M. Athanas. 33-42 [doi]
- FPGA Implementation of Biometric Authentication System Based on Hand GeometryCelia López-Ongil, Raul Sánchez-Reillo, Judith Liu-Jimenez, Fernando Casado, Leslie Sánchez, Luis Entrena. 43-53 [doi]
- SoftSONIC: A Customisable Modular Platform for Video ApplicationsTero Rissa, Peter Y. K. Cheung, Wayne Luk. 54-63 [doi]
- Deploying Hardware Platforms for SoC Validation: An Industrial Case StudyA. Bigot, F. Charpentier, Helena Krupnova, I. Sans. 64-73 [doi]
- Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption SchemesTim Kerins, Emanuel M. Popovici, William P. Marnane. 74-83 [doi]
- Power Analysis Attacks Against FPGA Implementations of the DESFrançois-Xavier Standaert, Siddika Berna Örs, Jean-Jacques Quisquater, Bart Preneel. 84-94 [doi]
- Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable ComputerMaya Gokhale, Janette Frigo, Christine Ahrens, Justin L. Tripp, Ronald Minnich. 95-104 [doi]
- Stochastic Simulation for Biochemical Reactions on FPGAMasato Yoshimi, Yasunori Osana, Tomonori Fukushima, Hideharu Amano. 105-114 [doi]
- Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware ArchitecturesAlexander Thomas, Jürgen Becker. 115-124 [doi]
- Interconnecting Heterogeneous Nodes in an Adaptive Computing MachineFrederick C. Furtek, Eugene Hogenauer, James Scheuermann. 125-134 [doi]
- Improving FPGA Performance and Area Using an Adaptive Logic ModuleMichael Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini. 135-144 [doi]
- A Dual-V::DD:: Low Power FPGA ArchitectureAman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan. 145-157 [doi]
- Simultaneous Timing Driven Clustering and Placement for FPGAsGang Chen, Jason Cong. 158-167 [doi]
- Run-Time-Conscious Automatic Timing-Driven FPGA Layout SynthesisJason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng. 168-178 [doi]
- Compact Buffered Routing ArchitectureAndrea Lodi 0002, Roberto Giansante, Carlo Chiesa, Luca Ciccarelli, Fabio Campi, Mario Toma. 179-188 [doi]
- On Optimal Irregular Switch Box DesignsHongbing Fan, Yu-Liang Wu, Chak-Chung Cheung, Jiping Liu. 189-199 [doi]
- Dual Fixed-Point: An Efficient Alternative to Floating-Point ComputationChun Te Ewe, Peter Y. K. Cheung, George A. Constantinides. 200-208 [doi]
- Comparative Study of SRT-Dividers in FPGAGustavo Sutter, Gery Bioul, Jean-Pierre Deschamps. 209-220 [doi]
- Second Order Function Approximation Using a Single Multiplication on FPGAsJérémie Detrey, Florent de Dinechin. 221-230 [doi]
- Efficient Modular Division Implementation: ECC over GF(p) Affine Coordinates ApplicationGuerric Meurice de Dormale, Philippe Bulens, Jean-Jacques Quisquater. 231-240 [doi]
- A Low Fragmentation Heuristic for Task Placement in 2D RTR HW ManagementJesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos. 241-250 [doi]
- The Partition into Hypercontexts Problem for Hyperreconfigurable ArchitecturesSebastian Lange, Martin Middendorf. 251-260 [doi]
- A High-Density Optically Reconfigurable Gate Array Using Dynamic MethodMinoru Watanabe, Fuminori Kobayashi. 261-269 [doi]
- Evolvable Hardware for Signal Separation and Noise Cancellation Using Analog Reconfigurable DeviceDidier Keymeulen, Ricardo Salem Zebulum, Adrian Stoica, Vu Duong, Michael I. Ferguson. 270-278 [doi]
- Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGAEduardo Picatoste-Olloqui, Francisco Cardells-Tormo, Jordi Sempere-Agulló, Atilà Herms-Berenguer. 279-288 [doi]
- Logic Modules with Shared SRAM Tables for Field-Programmable Gate ArraysFatih Kocan, Jason Meyer. 289-300 [doi]
- A Modular System for FPGA-Based TCP Flow Processing in High-Speed NetworksDavid V. Schuehler, John W. Lockwood. 301-310 [doi]
- Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAsZachary K. Baker, Viktor K. Prasanna. 311-321 [doi]
- BIST Based Interconnect Fault Location for FPGAsNicola Campregher, Peter Y. K. Cheung, Milan Vasilko. 322-332 [doi]
- FPGAs BIST EvaluationA. Parreira, João Paulo Teixeira, Marcelino B. Santos. 333-343 [doi]
- Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded ProcessorC. J. Tavares, C. Bungardean, G. M. Matos, José T. de Sousa. 344-353 [doi]
- Evaluating Fault Emulation on FPGAPeeter Ellervee, Jaan Raik, Valentin Tihhomirov, Kalle Tammemäe. 354-363 [doi]
- Automating Optimized Table-with-Polynomial Function Evaluation for FPGAsDong-U Lee, Oskar Mencer, David J. Pearce, Wayne Luk. 364-373 [doi]
- Multiple Restricted MultiplicationNalin Sidahao, George A. Constantinides, Peter Y. K. Cheung. 374-383 [doi]
- Area*Time Optimized Hogenauer Channelizer Design Using FPL DevicesUwe Meyer-Bäse, Suhasini Rao, Javier Ramírez, Antonio García. 384-393 [doi]
- A Steerable Complex Wavelet Construction and Its Implementation on FPGAChristos-Savvas Bouganis, Peter Y. K. Cheung, Jeffrey Ng, Anil A. Bharath. 394-403 [doi]
- Programmable Logic Has More Computational Power than Fixed LogicGordon J. Brebner. 404-413 [doi]
- JHDLBits: The Merging of Two WorldsAlexandra Poetter, Jesse Hunter, Cameron Patterson, Peter M. Athanas, Brent E. Nelson, Neil Steiner. 414-423 [doi]
- A System Level Resource Estimation Tool for FPGAsChangchun Shi, James Hwang, Scott McMillan, Ann Root, Vinay Singh. 424-433 [doi]
- The PowerPC Backend Molen CompilerElena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis. 434-443 [doi]
- An Integrated Online Scheduling and Placement MethodologyManish Handa, Ranga Vemuri. 444-453 [doi]
- On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive PrioritiesMichael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker. 454-463 [doi]
- Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough CasesHideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu Suzuki. 464-473 [doi]
- Throughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image FiltersMarcos R. Boschetti, Sergio Bampi, Ivan Saraiva Silva. 474-483 [doi]
- Over 10Gbps String Matching Mechanism for Multi-stream Packet Scanning SystemsYutaka Sugawara, Mary Inaba, Kei Hiraki. 484-493 [doi]
- Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2Ma José Canet, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat, Eduardo R. de Lima. 494-504 [doi]
- Three-Dimensional Dynamic Programming for Homology SearchYoshiki Yamaguchi, Tsutomu Maruyama, Akihiko Konagaya. 505-515 [doi]
- An Instance-Specific Hardware Algorithm for Finding a Maximum CliqueShin ichi Wakabayashi, Kenji Kikuchi. 516-525 [doi]
- IP Generation for an FPGA-Based Audio DAC Sigma-Delta ConverterRalf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong-Pang Pun, Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong. 526-535 [doi]
- Automatic Creation of Reconfigurable PALs/PLAs for SoCMark Holland, Scott Hauck. 536-545 [doi]
- A Key Agile 17.4 Gbit/sec Camellia ImplementationDaniel Denning, James Irvine, Malachy Devlin. 546-554 [doi]
- High Performance True Random Number Generator in Altera Stratix FPLDsViktor Fischer, Milos Drutarovský, Martin Simka, Nathalie Bochard. 555-564 [doi]
- A Universal and Efficient AES Co-processor for Field Programmable Logic ArraysNorbert Pramstaller, Johannes Wolkerstorfer. 565-574 [doi]
- Exploring Area/Delay Tradeoffs in an AES FPGA ImplementationJoseph Zambreno, David Nguyen, Alok N. Choudhary. 575-585 [doi]
- Reconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit ProcessorSandeep S. Kumar, Christof Paar. 586-595 [doi]
- Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable CoprocessorsMiljan Vuletic, Laura Pozzi, Paolo Ienne. 596-605 [doi]
- Storage Allocation for Diverse FPGA Memory SpecificationsDalia Dagher, Iyad Ouaiss. 606-616 [doi]
- Real Time Optical Flow Processing SystemJavier Díaz, Eduardo Ros, Sonia Mota, Richard R. Carrillo, Rodrigo Agís. 617-626 [doi]
- Methods and Tools for High-Resolution ImagingTim Todman, Wayne Luk. 627-636 [doi]
- Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to ImplementationAndrei Bartic, Dirk Desmet, Jean-Yves Mignolet, Théodore Marescaux, Diederik Verkest, Serge Vernalde, Rudy Lauwereins, J. Miller, Frédéric Robert. 637-647 [doi]
- A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible DataChristophe Layer, Hans-Jörg Pfleiderer. 648-657 [doi]
- A Framework for Energy Efficient Design of Multi-rate Applications Using Hybrid Reconfigurable SystemsSumit Mohanty, Viktor K. Prasanna. 658-668 [doi]
- An Efficient Battery-Aware Task Scheduling Methodology for Portable RC PlatformsJawad Khan, Ranga Vemuri. 669-678 [doi]
- HW/SW Co-design by Automatic Embedding of Complex IP CoresHolger Lange, Andreas Koch. 679-689 [doi]
- Increasing Pipelined IP Core Utilization in Process Networks Using ExplorationClaudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere. 690-699 [doi]
- Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAsRawat Siripokarpirom. 700-709 [doi]
- SOC and RTOS: Managing IPs and Tasks CommunicationsArthur Segard, François Verdier. 710-718 [doi]
- The Impact of Pipelining on Energy per Operation in Field-Programmable Gate ArraysSteven J. E. Wilton, Su-Shin Ang, Wayne Luk. 719-728 [doi]
- A Methodology for Energy Efficient FPGA Designs Using Malleable AlgorithmsJingzhao Ou, Viktor K. Prasanna. 729-739 [doi]
- Power-Driven Design PartitioningRajarshi Mukherjee, Seda Ogrenci Memik. 740-750 [doi]
- Power Consumption Reduction Through Dynamic ReconfigurationMichael G. Lorenz, Luis Mengibar, Mario García-Valderas, Luis Entrena. 751-760 [doi]
- The XPP Architecture and Its Co-simulation Within the Simulink EnvironmentMihail Petrov, Tudor Murgan, F. May, Martin Vorbach, Peter Zipf, Manfred Glesner. 761-770 [doi]
- An FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic CancerMuhammad Atif Tahir, Ahmed Bouridane, Fatih Kurugollu. 771-780 [doi]
- Increasing ILP of RISC Microprocessors Through Control-Flow Based ReconfigurationSteffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek. 781-790 [doi]
- Using of FPGA Coprocessor for Improving the Execution Speed of the Pattern Recognition Algorithm for ATLAS - High Energy Physics ExperimentChristian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller. 791-800 [doi]
- Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAsBrandon Blodget, Christophe Bobda, Michael Hübner, Adronis Niyonkuru. 801-810 [doi]
- SystemC for the Design and Modeling of Programmable SystemsAdam Donlin, Axel Braun, Adam Rose. 811-820 [doi]
- An Evolvable Hardware TutorialJim Torresen. 821-830 [doi]
- A Runtime Environment for Reconfigurable Hardware Operating SystemsHerbert Walder, Marco Platzner. 831-835 [doi]
- A Dynamically Reconfigurable Asynchronous FPGA ArchitectureXin Jia, Jayanthi Rajagopalan, Ranga Vemuri. 836-841 [doi]
- Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC ArchitecturesBjörn Griese, Erik Vonnahme, Mario Porrmann, Ulrich Rückert. 842-846 [doi]
- Optimal Routing-Conscious Dynamic Placement for Reconfigurable DevicesAli Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen. 847-851 [doi]
- Optimizing the Performance of the Simulated Annealing Based Placement Algorithms for Island-Style FPGAsAlexander Danilin, Sergei Sawitzki. 852-856 [doi]
- Automating the Layout of Reconfigurable Subsystems via Template ReductionShawn Phillips, Akshay Sharma, Scott Hauck. 857-861 [doi]
- FPGA Acceleration of Rigid Molecule InteractionsTom Van Court, Yongfeng Gu, Martin C. Herbordt. 862-867 [doi]
- Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-PathMichalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis. 868-873 [doi]
- Exploring Potential Benefits of 3D FPGA IntegrationCristinel Ababei, Pongstorn Maidee, Kia Bazargan. 874-880 [doi]
- System-Level Modeling of Dynamically Reconfigurable Co-processorsYang Qu, Kari Tiensyrjä, Kostas Masselos. 881-885 [doi]
- A Development Support System for Applications That Use Dynamically Reconfigurable HardwareJoão Canas Ferreira, José Silva Matos. 886-890 [doi]
- Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable ArchitecturesNikhil Bansal, Sumit Gupta, Nikil D. Dutt, Alexandru Nicolau, Rajesh K. Gupta. 891-899 [doi]
- Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAsRenqiu Huang, Manish Handa, Ranga Vemuri. 900-905 [doi]
- Mapping Basic Recursive Structures to Runtime Reconfigurable HardwareHossam A. ElGindy, George Ferizis. 906-910 [doi]
- Implementation of the Extended Euclidean Algorithm for the Tate Pairing on FPGATakehiro Ito, Yuichiro Shibata, Kiyoshi Oguri. 911-916 [doi]
- Java Technology in an FPGAMartin Schoeberl. 917-921 [doi]
- Hardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT SolversValery Sklyarov, Iouliia Skliarova, Bruno Figueiredo Pimentel, Joel Arrais. 922-926 [doi]
- The Chess Monster HydraChrilly Donninger, Ulf Lorenz. 927-932 [doi]
- FPGA-Efficient Hybrid LUT/CORDIC ArchitectureIreneusz Janiszewski, Hermann Meuth, Bernhard Hoppe. 933-937 [doi]
- A Multiplexer-Based Concept for Reconfigurable Multiplier ArraysOliver A. Pfänder, Roland Hacker, Hans-Jörg Pfleiderer. 938-942 [doi]
- Design and Implementation of a CFAR Processor for Target DetectionCesar Torres-Huitzil, René Cumplido-Parra, Santos López-Estrada. 943-947 [doi]
- A Parallel FFT Architecture for FPGAsJoseph Palmer, Brent E. Nelson. 948-953 [doi]
- FPGA Custom DSP for ECG Signal Analysis and CompressionMarcos Martínez Peiró, Francisco Ballester, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer. 954-958 [doi]
- FPGA Implementation of Adaptive Multiuser Detector for DS-CDMA SystemsQuoc Thai Ho, Daniel Massicotte. 959-964 [doi]
- Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC DesignUnai Bidarte, Armando Astarloa, José Luis Martín, Jon Andreu. 965-969 [doi]
- A Low Power FPAA for Wide Band ApplicationsErik Schüler, Luigi Carro. 970-974 [doi]
- Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAsEdson L. Horta, John W. Lockwood. 975-979 [doi]
- Real-Time Computation of the Generalized Hough TransformTsutomu Maruyama. 980-985 [doi]
- Minimum Sum of Absolute Differences Implementation in a Single FPGA DeviceJoaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides. 986-990 [doi]
- Design and Efficient FPGA Implementation of an RGB to YCrCb Color Space Converter Using Distributed ArithmeticFaycal Bensaali, Abbes Amira. 991-995 [doi]
- High Throughput Serpent Encryption ImplementationJesús Lázaro, Armando Astarloa, Jagoba Arias, Unai Bidarte, Carlos Cuadrado. 996-1000 [doi]
- Implementation of Elliptic Curve Cryptosystems over GF(2:::n:::) in Optimal Normal Basis on a Reconfigurable ComputerSashisu Bajracharya, Chang Shu, Kris Gaj, Tarek A. El-Ghazawi. 1001-1005 [doi]
- Wavelet-Based Image Compression on the Reconfigurable Computer ACE-VHagen Gädke, Andreas Koch. 1006-1010 [doi]
- A Reconfigurable Communication Processor Compatible with Different Industrial FieldbusesMaría Dolores Valdés, Miguel A. Domínguez, María José Moure, Camilo Quintáns. 1011-1016 [doi]
- Multithreading in a Hyper-programmable Platform for Networked SystemsPhilip James-Roxby, Gordon J. Brebner. 1017-1021 [doi]
- An Environment for Exploring Data-Driven ArchitecturesRicardo Ferreira, João M. P. Cardoso, Horácio C. Neto. 1022-1026 [doi]
- FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-TChristian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge Weber. 1027-1031 [doi]
- A Dynamic NoC Approach for Communication in Reconfigurable DevicesChristophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich. 1032-1036 [doi]
- Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time SystemsMichael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen Becker. 1037-1041 [doi]
- FiPRe: An Implementation Model to Enable Self-Reconfigurable ApplicationsLeandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato. 1042-1046 [doi]
- A Structured Methodology for System-on-an-FPGA DesignN. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk. 1047-1051 [doi]
- Secure Logic SynthesisKris Tiri, Ingrid Verbauwhede. 1052-1056 [doi]
- Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic InsertionM. G. Valderas, Eduardo de la Torre, F. Ariza, Teresa Riesgo. 1057-1061 [doi]
- The Implementation of a FPGA Hardware Debugger System with Minimal System OverheadJonathan Noel Tombs, Miguel Angel Aguirre Echánove, Fernando Muñoz Chavero, Vicente Baena Lecuyer, Antonio Jesús Torralba Silgado, A. Fernandez-León, Francisco Tortosa. 1062-1066 [doi]
- Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded MemoryAndrzej Krasniewski. 1067-1072 [doi]
- FPGA Implementation of a Neuromimetic Cochlea for a Bionic Bat HeadChris Clarke, Lin Qiang, Herbert Peremans, Álvaro Hernández. 1073-1075 [doi]
- FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree EvaluationTerrence S. T. Mak, K. P. Lam. 1076-1079 [doi]
- Processing Repetitive Sequence Structures with Mismatches at Streaming RateAlbert A. Conti, Tom Van Court, Martin C. Herbordt. 1080-1083 [doi]
- Artificial Neural Networks Processor - A Hardware Implementation Using a FPGAPedro Ferreira, Pedro Ribeiro, Ana Antunes, Fernando Morgado Dias. 1084-1086 [doi]
- FPGA Implementation of the Ridge Line Following Fingerprint AlgorithmEnrique Cantó, Nicolau Canyellas, Mariano Fons, Francisco Fons, Mariano López. 1087-1089 [doi]
- A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile TerminalsThilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner. 1090-1092 [doi]
- Flow Monitoring in High-Speed Networks with 2D Hash TablesDavid Nguyen, Joseph Zambreno, Gokhan Memik. 1093-1097 [doi]
- A VHDL Generator for Elliptic Curve CryptographyKimmo U. Järvinen, Matti Tommiska, Jorma Skyttä. 1098-1100 [doi]
- FPGA-Based Parallel Comparison of Run-Length-Encoded StringsAlessandro Bogliolo, Valerio Freschi, Filippo Miglioli, Matteo Canella. 1101-1103 [doi]
- Real Environments Image Labelling Based on Reconfigurable ArchitecturesJuan Manuel García Chamizo, Andrés Fuster Guilló, Jorge Azorín López. 1104-1106 [doi]
- Object Oriented Programming Paradigms for the VHDLJan Borgosz. 1107-1109 [doi]
- Using Reconfigurable Hardware Through Web Services in Distributed ApplicationsIvan Gonzalez, Javier Sanchez-Pastor, Jorge L. Hernandez-Ardieta, Francisco J. Gomez-Arribas, Javier Martínez. 1110-1112 [doi]
- Data Reuse in Configurable Architectures with RAM Blocks: Extended AbstractNastaran Baradaran, Joonseok Park, Pedro C. Diniz. 1113-1115 [doi]
- A Novel FPGA Configuration Bitstream Generation Algorithm and Tool DevelopmentK. Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis. 1116-1118 [doi]
- AAA and SynDEx-Ic: A Methodology and a Software Framework for the Implementation of Real-Time Applications onto Reconfigurable CircuitsPierre Niang, Thierry Grandpierre, Mohamed Akil, Yves Sorel. 1119-1123 [doi]
- A Self-Reconfiguration Framework for Multiprocessor CSoPCsArmando Astarloa, Jesús Lázaro, Unai Bidarte, José Luis Martín, Aitzol Zuloaga. 1124-1126 [doi]
- A Virtual File System for Dynamically Reconfigurable FPGAsAdam Donlin, Patrick Lysaght, Brandon Blodget, Gerd Troeger. 1127-1129 [doi]
- Virtualizing the Dimensions of a Coarse-Grained Reconfigurable ArrayTapio Ristimäki, Jari Nurmi. 1130-1132 [doi]
- Design and Implementation of the Memory Scheduler for the PC-Based RouterTomás Marek, Martin Novotný, Ludek Crha. 1133-1135 [doi]
- Analog Signal Processing Reconfiguration for Systems-on-Chip Using a Fixed Analog Cell ApproachEric E. Fabris, Luigi Carro, Sergio Bampi. 1136-1138 [doi]
- Intellectual Property Protection for RNS Circuits on FPGAsLuis Parrilla, Encarnación Castillo, Antonio García, Antonio Lloris-Ruíz. 1139-1141 [doi]
- FPGA Implementation of a Tool Breakage Detection Algorithm in CNC Milling MachinesRené de Jesús Romero-Troncoso, Gilberto Herrera Ruiz. 1142-1145 [doi]
- Implementation of a 3-D Switching Median Filtering Scheme with an Adaptive LUM-Based Noise DetectorMilos Drutarovský, Viktor Fischer. 1146-1148 [doi]
- Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGAJan Schier, Antonin Hermanek. 1149-1151 [doi]
- FPGA Implementation of a Vision-Based Motion Estimation Algorithm for an Underwater RobotViorela Ila, Rafael García, François Charot, Joan Batlle. 1152-1154 [doi]
- Real-Time Detection of Moving ObjectsHiroaki Niitsuma, Tsutomu Maruyama. 1155-1157 [doi]
- Real-Time Visual Motion Detection of Overtaking Cars for Driving Assistance Using FPGAsSonia Mota, Eduardo Ros, Javier Díaz, Eva M. Ortigosa, Rodrigo Agís, Richard R. Carrillo. 1158-1161 [doi]
- Versatile Imaging Architecture Based on a System on ChipPierre Chalimbaud, François Berry. 1162-1164 [doi]
- A Hardware Implementation of a Content Based Image Retrieval AlgorithmConstantinos Skarpathiotis, Keith R. Dimond. 1165-1167 [doi]
- Optimization Algorithms for Dynamic Reconfigurable Embedded Systems pAli Ahmadinia. 1168 [doi]
- Low Power Reconfigurable DevicesAman Gayasen. 1169 [doi]
- Code Re-ordering for a Class of Reconfigurable MicroprocessorsBrian F. Veale, John K. Antonio, Monte P. Tull. 1170 [doi]
- Design Space Exploration for Distributed Hardware Reconfigurable SystemsChristian Haubelt. 1171 [doi]
- TPR: Three-D Place and Route for FPGAsCristinel Ababei. 1172 [doi]
- Implementing Graphics Shaders Using FPGAsDavid B. Thomas, Wayne Luk. 1173 [doi]
- Preemptive Hardware Task ManagementDirk Koch. 1174 [doi]
- Automated Speculation and Parallelism in High Performance Network ApplicationsGraham Schelle, Dirk Grunwald. 1175 [doi]
- Automated Mapping of Coarse-Grain Pipelined Applications to FPGA SystemsHeidi E. Ziegler. 1176-1177 [doi]
- A Specific Scheduling Flow for Dynamically Reconfigurable HardwareJavier Resano. 1178-1179 [doi]
- Design and Evaluation of an FPGA Architecture for Software ProtectionJoseph Zambreno. 1180 [doi]
- Scalable Defect Tolerance Beyond the SIA RoadmapMahim Mishra. 1181-1182 [doi]
- Run-Time Reconfiguration Management for Adaptive High-Performance Computing SystemsMohamed Taher, Tarek A. El-Ghazawi. 1183 [doi]
- Optimized Field Programmable Gate Array Based Function EvaluationNalin Sidahao. 1184 [doi]
- MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory BlocksR. Manimegalai, A. Manoj Kumar, B. Jayaram, V. Kamakoti. 1185 [doi]
- A System on Chip Design Framework for Prime Number Validation Using Reconfigurable HardwareRay C. C. Cheung. 1186-1187 [doi]
- On Computing Maximum Likelihood Phylogeny Using FPGA pTerrence S. T. Mak, K. P. Lam. 1188 [doi]
- Minimising Reconfiguration Overheads in Embedded Applications (Abstract)Usama Malik. 1189 [doi]
- Application Specific Small-Scale ReconfigurabilityVinu Vijay Kumar. 1190 [doi]
- Efficient FPGA-Based Security KernelsZachary K. Baker. 1191 [doi]