Siddika Berna Örs - researchr alias

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Viewing Publication 1 - 25 from 25

2021

Comparison of RISC-V and transport triggered architectures for a postquantum cryptography applicationLatif Akçay, Siddika Berna Örs. elektrik, 29(1):321-333, 2021. [doi]

2020

Instruction Extension of an Open Source RV32IMC Core for NTRU CryptosystemElif Nur Isman, Canberk Topal, Latif Akçay, Siddika Berna Örs. ecctd 2020: 1-5 [doi]

2015

Design of core blocks and implementation on a programmable logic controller for a train signalization systemBurcu Akmansayar, Salman Kurtulan, Siddika Berna Örs. siu 2015: 1942-1945 [doi]

2014

Image filtering processor and its applicationsAhmet Cagri Bagbaba, Siddika Berna Örs, Ahmet Turan Erozan. siu 2014: 2011-2014 [doi]

Analyzing and comparing the AES architectures for their power consumptionAhmet Dogan, Siddika Berna Örs, Gökay Saldamli. jim, 25(2):263-271, 2014. [doi]

2013

Implementation of a secure RFID protocolSubutay Giray Baskir, Siddika Berna Örs. siu 2013: 1-4 [doi]

Hardware/Software codesign for watermarking in DCT domainAhmet Turan Erozan, Subutay Giray Baskir, Siddika Berna Örs. siu 2013: 1-4 [doi]

2011

Architectures for Fast Modular MultiplicationAhmet Aris, Siddika Berna Örs, Gökay Saldamli. dsd 2011: 434-437 [doi]

Implementation of a PUF Circuit on a FPGAMehmet Soybali, Siddika Berna Örs, Gökay Saldamli. ntms 2011: 1-5 [doi]

2008

2007

Differential power and electromagnetic attacks on a FPGA implementation of elliptic curve cryptosystemsElke De Mulder, Siddika Berna Örs, Bart Preneel, Ingrid Verbauwhede. cee, 33(5-6):367-382, 2007. [doi]

Power Analysis Resistant Hardware Implementations of AESLevent Ordu, Siddika Berna Örs. icecsys 2007: 1408-1411 [doi]

2004

Flexible Hardware Design for RSA and Elliptic Curve CryptosystemsLejla Batina, Geeke Bruin-Muurling, Siddika Berna Örs. ctrsa 2004: 250-263 [doi]

An FPGA Implementation of a Montgomery Multiplier Over GF(2^m)Nele Mentens, Siddika Berna Örs, Bart Preneel, Joos Vandewalle. cai, 23(5):487-499, 2004.

An FPGA implementation of an elliptic curve processor GF(2:::m:::)Nele Mentens, Siddika Berna Örs, Bart Preneel. glvlsi 2004: 454-457 [doi]

Power Analysis Attacks Against FPGA Implementations of the DESFrançois-Xavier Standaert, Siddika Berna Örs, Jean-Jacques Quisquater, Bart Preneel. fpl 2004: 84-94 [doi]

Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure?François-Xavier Standaert, Siddika Berna Örs, Bart Preneel. ches 2004: 30-44 [doi]

Power-Analysis Attack on an ASIC AES implementationSiddika Berna Örs, Frank K. Gürkaynak, Elisabeth Oswald, Bart Preneel. itcc 2004: 546-552 [doi]

2003

1999

Modeling Bit Multiplication Blocks for DSP Applications Using VHDLSiddika Berna Örs, Ahmet Dervisoglu. euromicro 1999: 1402-1405 [doi]

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