Abstract is missing.
- Fast custom instruction identification by convex subgraph enumerationKubilay Atasu, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar. 1-6 [doi]
- Bit matrix multiplication in commodity processorsYedidya Hilewitz, Cédric Lauradoux, Ruby B. Lee. 7-12 [doi]
- Synthesis of application accelerators on Runtime Reconfigurable HardwareMythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy, Ranjani Narayan. 13-18 [doi]
- Floating point multiplication rounding schemes for interval arithmeticAlexandru Amaricai, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan, Oana Boncalo. 19-24 [doi]
- Fast multivariate signature generation in hardware: The case of rainbowSundar Balasubramanian, Harold W. Carter, Andrey Bogdanov, Andy Rupp, Jintai Ding. 25-30 [doi]
- Fault-tolerant dynamically reconfigurable NoC-based SoCMohammad Hosseinabady, José L. Núñez-Yáñez. 31-36 [doi]
- Security processor with quantum key distributionThomas Lorunser, Edwin Querasser, Thomas Matyus, Momtchil Peev, Johannes Wolkerstorfer, Michael Hutter, Alexander Szekely, Ilse Wimberger, Christian Pfaffel-Janser, Andreas Neppach. 37-42 [doi]
- Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transformPramod Kumar Meher, Jagdish Chandra Patra. 43-48 [doi]
- Reconfigurable Viterbi decoder on mesh connected multiprocessor architectureRitesh Rajore, Ganesh Garga, H. S. Jamadagni, S. K. Nandy. 49-54 [doi]
- Run-time thread sorting to expose data-level parallelismTirath Ramdas, Gregory K. Egan, David Abramson, Kim Baldridge. 55-60 [doi]
- A new high-performance scalable dynamic interconnection for FPGA-based reconfigurable systemsSlavisa Jovanovic, Camel Tanougast, Serge Weber. 61-66 [doi]
- Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platformsDavid Dickin, Lesley Shannon. 67-72 [doi]
- PERMAP: A performance-aware mapping for application-specific SoCsAbbas Eslami Kiasari, Shaahin Hessabi, Hamid Sarbazi-Azad. 73-78 [doi]
- Low-cost implementations of NTRU for pervasive securityAli Can Atici, Lejla Batina, Junfeng Fan, Ingrid Verbauwhede, Siddika Berna Örs. 79-84 [doi]
- On the high-throughput implementation of RIPEMD-160 hash algorithmMiroslav Knezzevic, Kazuo Sakiyama, Yong Ki Lee, Ingrid Verbauwhede. 85-90 [doi]
- Zodiac: System architecture implementation for a high-performance Network Security ProcessorWang Haixin, Bai Guoqiang, Chen Hongyi. 91-96 [doi]
- Efficient systolization of cyclic convolution for systolic implementation of sinusoidal transformsPramod Kumar Meher. 97-101 [doi]
- Resource efficient generators for the floating-point uniform and exponential distributionsDavid B. Thomas, Wayne Luk. 102-107 [doi]
- Low discrepancy sequences for Monte Carlo simulations on reconfigurable platformsIshaan L. Dalal, Deian Stefan, Jared Harwayne-Gidansky. 108-113 [doi]
- A subsampling pulsed UWB demodulator based on a flexible complex SVDYves Vanderperren, Wim Dehaene. 114-119 [doi]
- Dynamically reconfigurable regular expression matching architectureJ. Divyasree, H. Rajashekar, Kuruvilla Varghese. 120-125 [doi]
- An MPSoC architecture for the Multiple Target Tracking application in driver assistant systemJehangir Khan, Smaïl Niar, Atika Rivenq, Yassin Elhillali, Jean-Luc Dekeyser. 126-131 [doi]
- Managing multi-core soft-error reliability through utility-driven cross domain optimizationWangyuan Zhang, Tao Li. 132-137 [doi]
- An efficient implementation of a phase unwrapping kernel on reconfigurable hardwareSherman Braganza, Miriam Leeser. 138-143 [doi]
- A parallel hardware architecture for connected component labeling based on fast label mergingHolger Flatt, Steffen Blume, Sebastian Hesselbarth, Torsten Schünemann, Peter Pirsch. 144-149 [doi]
- Operation shuffling over cycle boundaries for low energy L0 clusteringYuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai. 150-155 [doi]
- An efficient digital circuit for implementing Sequence Alignment algorithm in an extended processorVamsi Kundeti, Yunsi Fei, Sanguthevar Rajasekaran. 156-161 [doi]
- Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transformBasant K. Mohanty, Pramod Kumar Meher. 162-166 [doi]
- Design space exploration of a cooperative MIMO receiver for reconfigurable architecturesShahnam Mirzaei, Ali Irturk, Ryan Kastner, Brad T. Weals, Richard E. Cagley. 167-172 [doi]
- Dynamic holographic reconfiguration on a four-context ODRGAMao Nakajima, Minoru Watanabe. 173-178 [doi]
- FPGA-based hardware accelerator of the heat equation with applications on infrared thermographyFernando Pardo, Paula López Martinez, Diego Cabello. 179-184 [doi]
- FPGA based singular value decomposition for image processing applicationsMasih Rahmaty, Mohammad S. Sadri, Mehdi Ataei Naeini. 185-190 [doi]
- Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAsArpith C. Jacob, Jeremy Buhler, Roger D. Chamberlain. 191-196 [doi]
- A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral OperatorJason Lee, Lesley Shannon, Matthew J. Yedlin, Gary F. Margrave. 197-202 [doi]
- Reconfigurable acceleration of microphone array algorithms for speech enhancementKa Fai Cedric Yiu, Chun Hok Ho, Nedelko Grbic, Yao Lu, Xiaoxiang Shi, Wayne Luk. 203-208 [doi]
- Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standardsYang Sun, Yuming Zhu, Manish Goel, Joseph R. Cavallaro. 209-214 [doi]
- Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codesMarcos B. S. Tavares, Steffen Kunze, Emil Matús, Gerhard Fettweis. 215-220 [doi]
- Buffer allocation for advanced packet segmentation in Network ProcessorsDaniel Llorente, Kimon Karras, Thomas Wild, Andreas Herkersdorf. 221-226 [doi]
- New insights on Ling addersÁlvaro Vázquez, Elisardo Antelo. 227-232 [doi]
- An efficient method for evaluating polynomial and rational function approximationsNicolas Brisebarre, Sylvain Chevillard, Milos D. Ercegovac, Jean-Michel Muller, Serge Torres. 233-238 [doi]
- Integer and floating-point constant multipliers for FPGAsNicolas Brisebarre, Florent de Dinechin, Jean-Michel Muller. 239-244 [doi]
- Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processorAndres Garcia, Mladen Berekovic, Tom Vander Aa. 245-250 [doi]
- RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle routerJoseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, Ranjani Narayan. 251-256 [doi]
- Loop-oriented metrics for exploring an application-specific architecture design-spaceMaria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre. 257-262 [doi]
- Rapid estimation of instruction cache hit rates using loop profilingSantanu Kumar Dash, Thambipillai Srikanthan. 263-268 [doi]
- Reducing power consumption of embedded processors through register file partitioning and compiler supportXuan Guan, Yunsi Fei. 269-274 [doi]
- Lightweight DMA management mechanisms for multiprocessors on FPGAAntonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto. 275-280 [doi]
- Memory copies in multi-level memory systemsPepijn J. de Langen, Ben H. H. Juurlink. 281-286 [doi]
- Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decodersRao Adrsha, Mythri Alle, S. K. Nandy, Ranjani Narayan. 287-292 [doi]
- An FPGA architecture for CABAC decoding in manycore systemsRoberto R. Osorio, Javier D. Bruguera. 293-298 [doi]
- Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filtersAndre Guntoro, Manfred Glesner. 299-304 [doi]
- Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coderBasant K. Mohanty, Pramod Kumar Meher. 305-309 [doi]