Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes

Marcos B. S. Tavares, Steffen Kunze, Emil Matús, Gerhard Fettweis. Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes. In 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008 Leuven, Belgium. pages 215-220, IEEE Computer Society, 2008. [doi]

Abstract

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