Basant K. Mohanty - researchr alias

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Viewing Publication 1 - 28 from 28

2023

A novel computing scheme based on pattern matching for identification of nephron loss and chronic kidney disease stageRehan Ahmad, Basant K. Mohanty. elektrik, 31(7):1237-1254, November 2023. [doi]

2021

Chronic kidney disease stage identification using texture analysis of ultrasound imagesRehan Ahmad, Basant K. Mohanty. bspc, 69:102695, 2021. [doi]

2020

Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix AdderSubodh Kumar Singhal, Basant K. Mohanty, Sujit Kumar Patel, Gaurav Saxena. jcsc, 29(12), 2020. [doi]

2019

Area-Delay-Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real DataBasant K. Mohanty, Pramod Kumar Meher. tcas, 66-I(3):1042-1050, 2019. [doi]

2016

LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive FilterBasant K. Mohanty, Pramod Kumar Meher, Sujit Kumar Patel. tvlsi, 24(5):1926-1935, 2016. [doi]

2015

Leakage-aware intra-task dynamic voltage scaling technique for energy reduction in real-time embedded systemsVivek Chaturvedi, Basant K. Mohanty, Thambipillai Srikanthan. icdsp 2015: 1266-1269 [doi]

Memory-access aware work-load distribution for peak-temperature reduction of 3D multi-core embedded systemsBasant K. Mohanty, Vivek Chaturvedi, Vijeta Rathore, Thambipillai Srikanthan. icdsp 2015: 1270-1273 [doi]

Critical-path optimization for efficient hardware realization of lifting and flipping DWTsBasant K. Mohanty, Pramod Kumar Meher, Thambipillai Srikanthan. iscas 2015: 1186-1189 [doi]

2014

2013

Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWTBasant K. Mohanty, Pramod Kumar Meher. tcsv, 23(2):353-363, 2013. [doi]

A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS AlgorithmBasant K. Mohanty, Pramod Kumar Meher. tsp, 61(4):921-932, 2013. [doi]

Efficient-Block-Processing Parallel Architecture for Multilevel Lifting 2-D DWTBasant K. Mohanty, Anurag Mahajan. jolpe, 9(1):37-44, 2013. [doi]

Scheduling-scheme and parallel structure for multi-level lifting two-dimensional discrete wavelet transform without using frame-bufferBasant K. Mohanty, Anurag Mahajan. iet-cds, 7(6):319-325, 2013. [doi]

Systolic architecture for hardware implementation of two-dimensional non-separable filter-bankBasant K. Mohanty, Somaya Al-Máadeed, Abbes Amira. idt 2013: 1-6 [doi]

2012

Efficient architectures for VLSI implementation of 2-D discrete Hadamard transformBasant K. Mohanty, Pramod Kumar Meher, Subodh Kumar Singhal. iscas 2012: 1480-1483 [doi]

Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWTBasant K. Mohanty, Anurag Mahajan, Pramod Kumar Meher. tcas, 59-II(7):434-438, 2012. [doi]

2011

Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of FramesBasant K. Mohanty, Pramod Kumar Meher. tsp, 59(11):5605-5616, 2011. [doi]

Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWTBasant K. Mohanty, Pramod Kumar Meher. tsp, 59(5):2072-2084, 2011. [doi]

2010

Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmeticAnurag Mahajan, Basant K. Mohanty. apccas 2010: 1195-1198 [doi]

Parallel and Pipeline Architectures for High-Throughput Computation of Multilevel 3-D DWTBasant K. Mohanty, Pramod Kumar Meher. tcsv, 20(9):1200-1209, 2010. [doi]

2008

Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet TransformPramod Kumar Meher, Basant K. Mohanty, Jagdish Chandra Patra. tcas, 55-II(2):151-155, 2008. [doi]

Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coderBasant K. Mohanty, Pramod Kumar Meher. asap 2008: 305-309 [doi]

Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transformBasant K. Mohanty, Pramod Kumar Meher. asap 2008: 162-166 [doi]

2006

Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet TransformBasant K. Mohanty, Pramod Kumar Meher. apccas 2006: 462-465 [doi]

VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWTBasant K. Mohanty, Pramod Kumar Meher. apccas 2006: 458-461 [doi]

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