Abstract is missing.
- Challenges in the Design of Security-Aware ProcessorsRuby B. Lee. 2 [doi]
- Context-Aware Process NetworksHylke W. van Dijk, Henk J. Sips, Ed F. Deprettere. 6-16 [doi]
- Multi-dimentsional Incremetal Loops Fusion for Data LocalitySven Verdoolaege, Maurice Bruynooghe, Gerda Janssens, Francky Catthoor. 17-27 [doi]
- Switched Memory Architectures-Moving Beyond Systolic ArraysLakshminarayanan Renganarayanan, Sanjay V. Rajopadhye. 28-39 [doi]
- Hardware Synthesis for Multi-Dimensional TimeAnne-Claire Guillou, Patrice Quinton, Tanguy Risset. 40-50 [doi]
- Using Group Theory to Specify Application Specific Interconnection Networks for SIMD DSPsThorsten Dräger, Gerhard Fettweis. 51 [doi]
- Systematic Register Bypass Customization for Application-Specific ProcessorsKevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke. 64-74 [doi]
- Storage Management in Process Networks using the Lexicographically Maximal PreimageAlexandru Turjan, Bart Kienhuis. 75-85 [doi]
- Energy Aware Register File Implementation through Instruction PredecodeJosé L. Ayala, Marisa Luisa López-Vallejo, Alexander V. Veidenbaum, Carlos A. Lopez. 86-96 [doi]
- Physical Planning for On-Chip Multiprocessor Networks and Switch FabricsTerry Tao Ye, Giovanni De Micheli. 97-107 [doi]
- Automatic Instruction Set Extension and Utilization for Embedded ProcessorsArmita Peymandoust, Laura Pozzi, Paolo Ienne, Giovanni De Micheli. 108 [doi]
- Nanotechnology in the Development of Future Computing SystemsToshishige Yamada, M. Meyyappan. 120-124 [doi]
- Circuit Characteristics of Molecular Electronic ComponentsDavid B. Janes, Subhasis Ghosh, Jaewon Choi, Saurabh Lodha. 125-131 [doi]
- Reconfigurable Computing and Electronic NanotechnologySeth Copen Goldstein, Mihai Budiu, Mahim Mishra, Girish Venkataramani. 132 [doi]
- Using Media Processors for Low-Memory AES ImplementationJames Irwin, Dan Page. 144-154 [doi]
- Variable-Length Instruction Compression for Area MinimizationPiia Simonen, Ilkka Saastamoinen, Jari Nurmi. 155-160 [doi]
- Generic Tool-Set for SoC Mulitiprocessor Debugging and SynchronizationAndreas Wieferink, Tim Kogel, Achim Nohl, Andreas Hoffmann. 161-171 [doi]
- Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable ArchitecturesJong-eun Lee, Kiyoung Choi, Nikil D. Dutt. 172-182 [doi]
- Application-Specific Computing with Adaptive Register File ArchitecturesRama Sangireddy, Arun K. Somani. 183 [doi]
- A floating-point CORDIC based SVD processorZhaohui Liu, Kevin Dickson, John V. McCanny. 194-203 [doi]
- Combined Multiplication and Sum-of-Squares UnitsMichael J. Schulte, Louis Marquette, Shankar Krithivasan, E. George Walters III, John Glossner. 204-214 [doi]
- Comparison of Branching CORDIC ImplementationsAbhishek Singh, Dhananjay S. Phatak, Tom Goff, Mike Riggs, James F. Plusquellic, Chintan Patel. 215-225 [doi]
- Unified Radix-4 Multiplier for GF(p) and GF(2^n)Lai-Sze Au, Neil Burgess. 226-236 [doi]
- Arbitrary Bit Permutations in One or Two CyclesZhijie Shi, Xiao Yang, Ruby B. Lee. 237 [doi]
- Color Space Conversion for MPEG decoding on FPGA-augmented TriMedia ProcessorMihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven. 250-259 [doi]
- Reducing dynamic power consumption in next generation DS-CDMA mobile communication receiversVikram Chandrasekhar, Frank Livingston, Joseph R. Cavallaro. 260-270 [doi]
- An Efficient Disk-Array-Based Server Design for a Multicast Video Streaming SystemP. H. Chan Patton, Jack Y. B. Lee. 271-281 [doi]
- An Efficient PIM (Processor-In-Memory) Architecture for Motion EstimationJung-Yup Kang, Sandeep Gupta, Saurabh Shah, Jean-Luc Gaudiot. 282-292 [doi]
- A VLSI Architecture for Advanced Video Coding Motion EstimationSwee Yeow, John V. McCanny. 293 [doi]
- Complex Division with Prescaling of OperandsJean-Michel Muller. 304-314 [doi]
- Iterative Methods for Logarithmic SubtractionMark G. Arnold. 315-525 [doi]
- A Family of Parallel-Pre.x Modulo 2n - 1 AddersGiorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou. 326-336 [doi]
- Performance-Improved Computation of Very Large Word-Length LNS Addition/Subtraction Using Signed-Digit ArithmeticChichyang Chen, Rui-Lin Chen. 337-347 [doi]
- Decimal Multiplication Via Carry-Save AdditionMark A. Erle, Michael J. Schulte. 348 [doi]
- Reconfigurable Viterbi Decoding Using a New ACS Pipelining TechniqueYiqun Zhu, Mohammed Benaissa. 360-368 [doi]
- Application-Specific DSP Architecture For Fast Fourier TransformKyung Lan Heo, Sung M. Cho, Jung Hoo Lee, Myung Hoon Sunwoo. 369-377 [doi]
- An Architecture for a Radix-4 Modular Pipeline Fast Fourier TransformAyman M. El-Khashab, Earl E. Swartzlander Jr.. 378-388 [doi]
- GFS: An Efficient Implementation of Fair Scheduling for Mult-Gigabit Packet NetworksGeorge Kornaros, Theofanis Orphanoudakis, Ioannis Papaefstathiou. 389-399 [doi]
- Area and Time Efficient Modular Multiplication of Large IntegersViktor Bunimov, Manfred Schimmler. 400 [doi]
- Modular Multiplication for FPGA Implementation of the IDEA Block CipherJean-luc Beauchat. 412-422 [doi]
- Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption AlgorithmGuido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri. 423-432 [doi]
- Hardware Implementation of an Elliptic Curve Processor over GF(p)Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle. 433-443 [doi]
- A Cryptograhpic Processor for Arbitrary Elliptic Curves overHans Eberle, Nils Gura, Sheueling Chang Shantz. 444-454 [doi]
- Instruction Set Extension for Fast Elliptic Curve Cryptography over Binary Finite Fields GF(2m)Johann Großschädl, Guy-Armand Kamendje. 455 [doi]