Adonios Thanailakis - researchr alias

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Viewing Publication 1 - 62 from 62

2008

A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number SystemMinas Dasygenis, K. Mitroglou, Dimitrios Soudris, Adonios Thanailakis. tcas, 55-I(2):546-558, 2008. [doi]

A CAD System for Modeling and Simulation of Computer Networks Using Cellular AutomataV. Mardiris, Georgios Ch. Sirakoulis, Ch. Mizas, Ioannis Karafyllidis, Adonios Thanailakis. tsmc, 38(2):253-264, 2008. [doi]

2007

Systematic methodology for designing low power direct digital frequency synthesisersMarios Kesoulis, Dimitrios Soudris, Christos S. Koukourlis, Adonios Thanailakis. iet-cds, 1(4):293-304, 2007. [doi]

Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applicationsKonstantinos Tatas, George Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis. integration, 40(2):74-93, 2007. [doi]

2006

2005

A modified spiral search motion estimation algorithm and its embedded system implementationNikolas Kroupis, Minas Dasygenis, K. Markou, Dimitrios Soudris, Adonios Thanailakis. iscas 2005: 3347-3350 [doi]

An Integrated Framework for Architecture Level Exploration of Reconfigurable PlatformK. Siozios, Konstantinos Tatas, George Koutroumpezis, D. J. Soudris, Adonios Thanailakis. fpl 2005: 658-661

A Low-Energy FPGA: Architecture Design and Software-Supported Design FlowK. Siozios, Dimitrios Soudris, Adonios Thanailakis. fpl 2005: 707-708

DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool ImplementationK. Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis. ipps 2005: [doi]

A fault-tolerant message passing algorithm and its hardware implementationGeorgios Ch. Sirakoulis, V. Raptis, Ioannis Karafyllidis, Phillipos Tsalides, Adonios Thanailakis. aes, 36(3):159-171, 2005. [doi]

A cellular automaton for the propagation of circular fronts and its applicationsGeorgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis. eaai, 18(6):731-744, 2005. [doi]

AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flowDimitrios Soudris, Spiridon Nikolaidis, Stilianos Siskos, Konstantinos Tatas, K. Siozios, George Koutroumpezis, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Adonios Thanailakis. aspdac 2005: 3-4 [doi]

Memory power optimization of hardware implementations of multimedia applications onto FPGA platformsKonstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis. jec, 1(3):353-362, 2005. [doi]

A Novel Division Algorithm and Architectures for Parallel and Sequential ProcessingKonstantinos Tatas, Dimitrios Soudris, D. Siomos, Adonios Thanailakis. jcsc, 14(2):281-296, 2005. [doi]

2004

2003

Designing Low Power Direct Digital Frequency SynthesizersMarios Kesoulis, Dimitrios Soudris, C. Koukourlis, Adonios Thanailakis. vlsi 2003: 105-110

A CAD system for the construction and VLSI implementation of Cellular Automata algorithms using VHDLGeorgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis. mam, 27(8):381-396, 2003. [doi]

A cellular automaton model for the study of DNA sequence evolutionGeorgios Ch. Sirakoulis, Ioannis Karafyllidis, Ch. Mizas, Vasilios A. Mardiris, Adonios Thanailakis, Phillipos Tsalides. cbm, 33(5):439-453, 2003. [doi]

A methodology for implementing FIR filters and CAD tool development for designing RNS-based systemsDimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis. iscas 2003: 129-132 [doi]

Alternative Direct Digital Frequency Synthesizer architectures with reduced memory sizeDimitrios Soudris, Marios Kesoulis, C. Koukourlis, Adonios Thanailakis, Spyros Blionas. iscas 2003: 73-76 [doi]

FPGA Architecture Design and Toolset for Logic ImplementationKonstantinos Tatas, K. Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, Stilianos Siskos, Adonios Thanailakis. patmos 2003: 607-616 [doi]

Power-Efficient Implementations of Multimedia Applications on Reconfigurable PlatformsKonstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis. fpl 2003: 1032-1035 [doi]

Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable PlatformsKonstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas. patmos 2003: 430-439 [doi]

2002

Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain ImplementationsGeorge Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis. fpl 2002: 1027-1036 [doi]

A cellular automaton methodology for the simulation of integrated circuit fabrication processesGeorgios Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis. fgcs, 18(5):639-657, 2002. [doi]

A full adder based methodology for scaling operation in residue number systemDimitrios Soudris, Minas Dasygenis, K. Mitroglou, Konstantinos Tatas, Adonios Thanailakis. icecsys 2002: 891-894 [doi]

A novel division algorithm for parallel and sequential processingKonstantinos Tatas, D. J. Soudris, D. Siomos, Minas Dasygenis, Adonios Thanailakis. icecsys 2002: 553-556 [doi]

A fast and accurate delay dependent method for switching estimation of large combinational circuitsS. Theoharis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis, Adonios Thanailakis. jsa, 48(4-5):113-124, 2002. [doi]

2001

2000

Designing RNS and QRNS full adder based convertersD. J. Soudris, M. M. Dasigenis, Adonios Thanailakis. iscas 2000: 20-23 [doi]

Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia ApplicationsDimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis. patmos 2000: 243-254 [doi]

Low power design of a multi-mode transceiverDimitrios Soudris, M. Perakis, X. Mizas, V. Mardiris, K. Katis, Chrissavgi Dre, A. E. Tzimas, E. G. Metaxakis, Grigorios Kalivas, Nikolaos D. Zervas, Spyros Theoharis, George Theodoridis, Adonios Thanailakis, Constantinos E. Goutis. iscas 2000: 721-724 [doi]

A methodology for the behavioral-level event-driven power management of digital receiversNikolaos D. Zervas, Dimitrios Soudris, Spyros Theoharis, Constantinos E. Goutis, Adonios Thanailakis. iscas 2000: 589-592 [doi]

1999

Estimation of power dissipation in glitching using complex-time cellular automataIoannis Karafyllidis, Stelios Mavridis, Dimitrios Soudris, Adonios Thanailakis. icecsys 1999: 1639-1642 [doi]

A new adiabatic technique for designing low power array architecturesC. Z. Lolas, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis. icecsys 1999: 795-798 [doi]

The VLSI implementation of a baseband receiver for DECT-based portable applicationsM. Perakis, A. E. Tzimas, E. G. Metaxakis, Dimitrios Soudris, G. A. Kalivas, C. Katis, Chrissavgi Dre, Constantinos E. Goutis, Adonios Thanailakis, Thanos Stouraitis. iscas 1999: 198-201 [doi]

Genetic partitioning and placement for VLSI circuitsGeorge Ch. Sirakoulis, Ioannis Karafyllidis, Adonios Thanailakis. icecsys 1999: 1647-1650 [doi]

The design of low power multiple-valued logic encoder and decoder circuitsI. Thoidis, D. J. Soudris, Ioannis Karafyllidis, Adonios Thanailakis. icecsys 1999: 1623-1626 [doi]

1998

Non-linear Hybrid Cellular Automata as Pseudorandom Pattern Generators for VLSI SystemsIoannis Karafyllidis, Ioannis Andreadis, Philippos G. Tsalides, Adonios Thanailakis. vlsi, 1998(2):177-189, 1998. [doi]

Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked LogicI. Thoidis, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis, Thanos Stouraitis. glvlsi 1998: 83-88 [doi]

1997

Geometrical Shape Recognition Using a Cellular Automaton Architecture and its VLSI ImplementationIoannis Karafyllidis, A. Ioannidis, Adonios Thanailakis, Phillipos Tsalides. rti, 3(4):243-254, 1997. [doi]

An efficient algorithm for the largest empty figure problem based on a 2D cellular automaton architecturePanagiotis Tzionas, Adonios Thanailakis, Phillipos G. Tsalides. ivc, 15(1):35-45, 1997. [doi]

Collision-free path planning for a diamond-shaped robot using two-dimensional cellular automataPanagiotis Tzionas, Adonios Thanailakis, Philippos G. Tsalides. trob, 13(2):237-250, 1997. [doi]

1996

1995

A Parallel Skeletonization Algorithm Based on Two-Dimensional Cellular Automata and its VLSI ImplementationPanagiotis Tzionas, Phillipos G. Tsalides, Adonios Thanailakis. rti, 1(2):105-117, 1995. [doi]

1994

Bit-serial VLSI sorter with high reliability specificationsE. D. Adamides, Phillipos G. Tsalides, Adonios Thanailakis. jsa, 40(8):523-536, 1994. [doi]

A new, cellular automaton-based, nearest neighbor pattern classifier and its VLSI implementationP. G. Tzionas, Panagiotis G. Tsalides, Adonios Thanailakis. tvlsi, 2(3):343-353, 1994. [doi]

A modified discrete Fourier-cosine transform algorithm and its VLSI implementationPanagiotis Tzionas, Philippos Tsalides, Adonios Thanailakis. mam, 18(6):343-350, 1994. [doi]

1992

Hierarchical Cellular Automata structuresE. D. Adamides, Phillipos Tsalides, Adonios Thanailakis. pc, 18(5):517-524, 1992.

Hierarchical Cellular Graph Automata as a Novel Architecture for Computer-Supported Cooperative WorkEmmanuel D. Adamides, Philippos Tsalides, Adonios Thanailakis. cj, 35(Additional-Papers), 1992.

Two-Dimensional Cellular Automata: Properties and Applications of a New VLSI ArchitecturePhilippos Tsalides, Adonios Thanailakis, Nikos Pitsianis, Georgios L. Bleris. cj, 35(Additional-Papers), 1992.

1989

Synchronization of D. Parkinsonasynchronous concurrent processes using cellular automataE. D. Adamides, Phillipos Tsalides, Adonios Thanailakis. pc, 11(2):163-169, 1989.

Algebraic Theory of Bounded One-dimensional Cellular AutomataNikos Pitsianis, Georgios L. Bleris, Philippos Tsalides, Adonios Thanailakis, Howard C. Card. compsys, 3(2), 1989. [doi]

1986

Analysis of Bounded Linear Cellular Automata Based on a Method of Image ChargesHoward C. Card, Adonios Thanailakis, Werner Pries, Robert D. McLeod. jcss, 33(3):473-480, 1986.

Group Properties of Cellular Automata and VLSI ApplicationsWerner Pries, Adonios Thanailakis, Howard C. Card. TC, 35(12):1013-1024, 1986.

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