Table of Contents

• Ambient Intelligence - Key Technologies in the Communication AgeWerner Weber. 1
• Exponential Challenges, Exponential Rewards - The future of Moore s LawShekhar Borkar. 2
• Towards safer cars - Microeletronics in AutomotiveAndreas Kirschbaum. 3
• Designing Application Specific Networks-On-Chip: Five easy piecesRadu Marculescu. 5
• Energy Efficient and Reliable System DesignNarayanan Vijaykrishnan. 6-9
• Formal VerificationKlaus Winkelmann. 10
• Substrate Modeling and Noise Reduction in Mixed-Signal CircuitsAndreas Hermann, Markus Olbrich, Erich Barke. 13-18
• Self-Timed Approach for Reducing On-Chip Switching NoiseJohanna Tuominen, Pasi Liljeberg, Jouni Isoaho. 19-24
• Dynamic Models for Substrate Coupling in Mixed-Mode SystemsJoão M. S. Silva, Luis Miguel Silveira. 25-30
• Measures to Reduce the Electromagnetic Emission of a SoCTimm Ostermann, Wolfgang Gut, Christian Bacher, Bernd Deutschmann. 31
• Communication and Timing Constraints Analysis for IP Design and IntegrationPhilippe Coussy, Adel Baganne, Eric Martin. 38-43
• A hierarchical generic approach for on-chip communication, testing and debugging of SoCsThomas Hollstein, Ralf Ludewig, Christoph Mager, Peter Zipf, Manfred Glesner. 44-49
• A Sigma-Delta Modulator Development Environment for Fractional-N Frequency SynthesisMaciej Borkowski, Juha Häkkinen, Juha Kostamovaara. 50-54
• Automated Conversion of SystemC Fixed-Point Data Types for Hardware SynthesisAxel G. Braun, Jan B. Freuer, Joachim Gerlach, Wolfgang Rosenstiel. 55
• High Performance of an AES-Rijndael ASIC working in OCB/ECB Modes of OperationCristian Chitu, Manfred Glesner. 62-67
• Architectures and FPGA Implementations of the SCO(-1, -2, -3) Ciphers FamilyNicolas Sklavos, Odysseas G. Koufopavlou. 68-73
• High Performance System Architecture of an Associative Computing Engine Optimised for Search AlgorithmsChristophe Layer. 74
• Exploration of Sequential Depth by Evolutionary AlgorithmsNicole Drechsler, Rolf Drechsler. 81-85
• Validation of asynchronous circuit specifications using IF/CADPDominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Sirianni. 86-91
• A Rule-Based Software Testing Method for VHDL ModelsAnneliese Amschler Andrews, Andrew O Fallon, Tom Chen. 92
• Logic Gates as Repeaters (LGR) for Timing Optimization of SoC InterconnectsArkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny. 99-104
• Designing Low Power Direct Digital Frequency SynthesizersMarios Kesoulis, Dimitrios Soudris, C. Koukourlis, Adonios Thanailakis. 105-110
• The Chip is Ready. Am I done? On-chip Verification using Assertion ProcessorsJosé Augusto Miranda Nacif, Flávio Miana de Paula, Harry Foster, Claudionor José Nunes Coelho Jr., Antônio Otávio Fernandes. 111
• Speeding up Online Placement for XILINX FPGAs by Reducing Configuration OverheadAli Ahmadinia, Jürgen Teich. 118-122
• Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed InterconnectionYoung-Su Kwon, Woo-Seung Yang, Chong-Min Kyung. 123-128
• Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA RealizationsJürgen Becker, Michael Hübner, Michael Ullmann. 129
• A Switched Opamp-based 10-b Integrated ADC for Ultra Low-power ApplicationsG. Bonfini, C. Garbossa, Roberto Saletti. 136-141
• Adaptive Sampling and Modeling of Analog Circuit Performance ParametersGlenn Wolfe, Mengmeng Ding, Ranga Vemuri. 142
• 3D rendering using FPGAsPéter Szántó, Béla Fehér. 149-154
• HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal ProcessingHans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Mark Bernd Kulaczewski, Peter Pirsch. 155-160
• Exploring the Capabilities of Reconfigurable Hardware for OFDM-based WLANsThilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner. 161-166
• An Adaptive Trace-Back Solution for State-Parallel Viterbi DecodersMihail Petrov, Abdulfattah Mohammad Obeid, Tudor Murgan, Peter Zipf, Jörg Brakensiek, Bernard Ölkrug, Manfred Glesner. 167
• Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip ArchitecturesAlexandre M. Amory, Leandro A. Oliveira, Fernando Gehm Moraes. 174-179
• Optimizing SOC Test Resources using Dual SequencesWei Zou, C. N. Chu, Sudhakar M. Reddy, Irith Pomeranz. 180-185
• Processor Testing Using an ADL Description and Genetic AlgorithmsElham Safi, Reihaneh Saberi, Zohreh Karimi, Zainalabedin Navabi. 186
• A New Macro-cell Generation Strategy for three metal layer CMOS TechnologiesCristiano Lazzari, Cristiano Viana Domingues, José Luís Almada Güntzel, Ricardo Augusto da Luz Reis. 193-197
• Parametric Equivalent Circuit Extraction for VLSI StructuresPavel V. Nikitin, Winnie Yam, C.-J. Richard Shi. 198-203
• A study on the performance of fast initial placement algorithmsRenato Fernandes Hentschke, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis. 204
• A PLL-Based RF Synthesizer Test SystemJuha Häkkinen, Maciej Borkowski, Juha Kostamovaara. 211-214
• Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC TestingShervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi. 215-220
• Designing and Testing High Dependable Memories for Aerospace ApplicationsAndrea S. Brogna, Franco Bigongiari, Silvia Chiusano, Paolo Prinetto, Roberto Saletti. 221
• Reprogrammable Algorithm Accelerator IP BlockTapio Ristimäki, Jari Nurmi. 228-232
• Tradeoffs in the Design Space Exploration of Application-Specific ProcessorsNikolaos Kavvadias, Spiridon Nikolaidis. 233-238
• Low Power Java Processor for Embedded ApplicationsAntonio Carlos Schneider Beck, Luigi Carro. 239
• Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off SchemesStephan Henzler, Markus Koban, Doris Schmitt-Landsiedel, Jörg Berthold, Georg Georgakos. 246-251
• Static Versus Dynamic Power Losses in CMOS VLSI Systems Considering TemperatureAdam Golda, Andrzej Kos. 252-257
• Evaluation Methodology for Single Electron Encoded Threshold Logic GatesCasper Lageweg, Sorin Cotofana, Stamatis Vassiliadis. 258-262
• Evaluation of Dynamic-Threshold Logic for Low-Power VLSI Design in 0.13um PD-SOIAlan J. Drake, Kevin J. Nowka, Richard B. Brown. 263
• Flexible Heterogeneous Multicore Architectures for Media Processing via Customized Long Instruction WordsChia-Ming Hsu, Tien-Fu Chen. 270-275
• Are coarse grain reconfigurable architectures suitable for cryptography?Daniel Mesquita, Lionel Torres, Fernando Gehm Moraes, Gilles Sassatelli, Michel Robert. 276-281
• Partitioning Reactive Data Flow Applications On Dynamically Reconfigurable SystemsKarim Ben Chehida, Michel Auguin. 282-287
• Datapath and Compiler Integration of Coarse-grain Reconfigurable XPP-Arrays into Pipelined RISC ProcessorsJürgen Becker, Alexander Thomas, Maik Scheer. 288
• In-Place Storage of Path Metrics in Viterbi DecodersTuomas Järvinen, Perttu Salmela, Teemu Sipilä, Jarmo Takala. 295-300
• Hough Transform recursive evaluation using Distributed ArithmeticJuan Manuel García Chamizo, Maria Teresa Signes Pont, Higinio Mora Mora, Gregorio de Miguel Casado. 301-306
• Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated DatapathsEduardo A. C. da Costa, José Monteiro, Sergio Bampi. 307
• Crosstalk Immune Coding from Area and Power Perspective for high performance AMBA based SoC systemsZahid Khan, Tughrul Arslan, Ahmet T. Erdogan. 314-317
• A Low Area Overhead Packet-switched Network on Chip: Architecture and PrototypingFernando Gehm Moraes, Aline Mello, Leandro Möller, Luciano Ost, Ney Laert Vilar Calazans. 318-323
• Microsystem and SoC Design with UMIPSMichael S. McCorquodale, Eric D. Marsman, Robert M. Senger, Fadi H. Gebara, Richard B. Brown. 324
• Testability of SPP Three-Level Logic NetworksValentina Ciriani, Anna Bernasconi, Rolf Drechsler. 331-336
• Reducing ATE Cost in System-on-Chip TestIlia Polian, Bernd Becker. 337-342
• DV-TSE: Difference Vector Based Test Set EmbeddingMaciej Bellos, Xrysovalantis Kavousianos, Dimitris Nikolos, Dimitri Kagaris. 343
• Calculation Methodology for Flexible Arithmetic ProcessingJuan Manuel García Chamizo, Jerónimo Mora Pascual, Higinio Mora Mora, Maria Teresa Signes Pont. 350-355
• A Versatile Cellular Neural Circuit Based on a Multi-nested Approach: Functional Capabilities and ApplicationsRadu Dogaru, Cristian Chitu, Manfred Glesner. 356-361
• Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip ArchitecturesDinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch. 362
• Delay and Short Circuit Power Estimation for a Submicron CMOS Inverter driving a CRC-PI Interconnect LoadShrutin Ulman. 369-374
• 1.8V 0.18µm CMOS Novel Successive Approximation ADCMartin Margala, Quentin Diduck, Eric Moule. 375-379
• Deep-Submicron CMOS Design Methodology for High-Performance Low-Power Analog-to-Digital ConvertersMartin Margala, John Liobe, Quentin Diduck. 380-385
• 1-V ADPCM Processor for Low-Power Wireless ApplicationsMartin Margala, Magdy A. El-Moursy, Ali El-Moursy, Junmou Zhang, Wendi Beth Heinzelman. 386-393
• A Low Power BIST Architecture for FPGA Look-Up Table TestingEhsan Atoofian, Zainalabedin Navabi. 394-397
• An All-Digital ADC for Instrumentation within SOCsAdão Antônio de Souza Jr., Luigi Carro. 398-403
• FPGA Implementation of a VVI Temporary Pacemaker Digital ControlDiego Caldas Salengue, João Baptista dos Santos Martins, Cesar Ramos Rodrigues, André Luiz Aita. 404-409
• Applying the GM/ID method in the analysis and design of Miller Amplifier, Comparator and GM-C PASS-BFernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi. 410-415
• MSL: A High-Level Language for Parameterized Analog and Mixed Signal Layout GeneratorsHemanth Sampath, Ranga Vemuri. 416-421
• Low-Power High-CMRR CMOS Instrumentation Amplifier for Biomedical ApplicationsAndré Luiz Aita, João Baptista dos Santos Martins, César Augusto Prior, Cesar Ramos Rodrigues. 422-425
• A Genetic Approach To Bus EncodingGiuseppe Ascia, Vincenzo Catania, Maurizio Palesi. 426-431
• 2D-DCT Implementation on FPGA by Polynomial Transformation in Two-DimensionsArturo Méndez Patiño, Marcos Martínez Peiró. 432-438
• FPGA-Based Variable Length DecodersJari Nikara, Stamatis Vassiliadis, Jarmo Takala, Petri Liuha. 437-441
• An Integrated Model Bridging the Gap between Technology and EconomyStephan Bingemer, Peter Zipf, Manfred Glesner. 442