Michael Moreinis - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 4 from 4

2006

Logic Gates as Repeaters (LGR) for Area-Efficient Timing OptimizationMichael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny. tvlsi, 14(11):1276-1281, 2006. [doi]

2004

Repeater insertion combined with LGR methodology for on-chip interconnect timing optimizationMichael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny. icecsys 2004: 125-128 [doi]

Asynchronous gate-diffusion-input (GDI) circuitsArkadiy Morgenshtein, Michael Moreinis, Ran Ginosar. tvlsi, 12(8):847-856, 2004. [doi]

2003

Logic Gates as Repeaters (LGR) for Timing Optimization of SoC InterconnectsArkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny. vlsi 2003: 99-104

Sign in or sign up to see more results.

runs on WebDSL