Abstract is missing.
- A new configuration of two-stage wide-band amplifier with matched input and output impedancesIgor M. Filanovsky, Andrew Sachko, John R. Long. 1-4 [doi]
- A bulk-driven CMOS OTA with 68 dB DC gainJonathan Rosenfeld, Mücahit Kozak, Eby G. Friedman. 5-8 [doi]
- A 100 dB CMRR CMOS operational amplifier with single-supply capabilityVadim Ivanov, Junlin Zhou, Igor M. Filanovsky. 9-12 [doi]
- Two novel cross-cascode differential amplifiersYuri Bruck, Michael Zelikson. 13-16 [doi]
- A wide-linear range subthreshold OTA based on FGMOS transistorAimad El Mourabit, Patrick Pittet, Guo-Neng Lu. 17-20 [doi]
- A 6 GHz low-noise quadrature Colpitts VCOMin Chu, David J. Allstot. 21-24 [doi]
- Design considerations for anti-phase injected quadrature voltage controlled oscillatorsMin Chu, Sudip Shekhar, David J. Allstot, Tarun Kanti Bhattacharyya. 25-28 [doi]
- A multi-tank LC-oscillator [microwave oscillator example]Luca Romanò, Carlo Samori, Salvatore Levantino, Andrea Bonfanti, Andrea L. Lacaita. 29-32 [doi]
- Differential tuning oscillators with reduced flicker noise upconversionSalvatore Levantino, Andrea Bonfanti, Luca Romanò, Carlo Samori, Andrea L. Lacaita. 33-36 [doi]
- Analysis and design of a dual band reconfigurable VCOAndrea Mazzanti, Paola Uggetti, Raffaele Battaglia, Francesco Svelto. 37-40 [doi]
- Dynamic range, noise and linearity optimization of continuous-time OTA-C filtersSlawomir Koziel, A. Ramachandran, Stanislaw Szczepanski, Edgar Sánchez-Sinencio. 41-44 [doi]
- Noise analysis and optimization of continuous-time active-RC filtersSlawomir Koziel. 45-48 [doi]
- General active-RC filter model for computer-aided design and optimizationSlawomir Koziel. 49-52 [doi]
- th order single-amplifier filterDrazen Jurisic, Neven Mijat, George S. Moschytz. 53-56 [doi]
- Analysis of linear system response to wide band signals with applications to filtersAsher Yahalom, Yosef Pinhasi. 57-60 [doi]
- Nonlinear dynamics of first-order DPLL with FM input and phase detector DC offsetBarry O'Donnell, Orla Feely, Paul F. Curran, Ketan Mistry. 61-64 [doi]
- The central limit theorem and low-pass filtersShlomo Engelberg. 65-68 [doi]
- Mathematical programming and resistor transformer diode networksH. Narayanan. 69-72 [doi]
- A new method to improve the impedance of the CC-II's X inputLuis Nero Alves, Rui L. Aguiar. 73-76 [doi]
- New chaotic third-order log-domain oscillator with tanh nonlinearityAlon Ascoli, Paul F. Curran, Orla Feely. 77-80 [doi]
- A unified fairness framework in multi-antenna multi-user channelsDiego Bartolomé, Ana I. Pérez-Neira. 81-84 [doi]
- Ergodic capacity of a 2 × 2 MIMO system under phase uncertainty at the transmitterM. Fayar, Xavier Mestre, Miguel Angel Lagunas. 85-88 [doi]
- Analysis of the probability distribution of the baseline wander effect for baseband PAM transmission with application to gigabit EthernetNaftali Sommer, Itay Lusky, Mor Miller. 89-92 [doi]
- Virtual input queued packet switches with non-uniform arrivals and bursty serviceItamar Elhanany, Ortal Arazi, Michael Kahane. 93-96 [doi]
- Performance evaluation of pseudo self-similar trafficMichael Kahane, Yehuda Ben-Shimol, Dan Sadot. 97-100 [doi]
- An IF input continuous-time sigma-delta analog-digital converter with high image rejectionJunhua Shen, Kong-Pang Pun, Chiu-sing Choy, Cheong-fat Chan. 101-104 [doi]
- A novel signal-predicting multibit delta-sigma modulatorXiaojun Lu. 105-108 [doi]
- A jitter insensitive continuous-time ΣΔ modulator using transmission linesLuis Hernández, Pieter Rombouts, Enrique Prefasi, Susana Patón, Mario Garcia, Celia Lopez. 109-112 [doi]
- A 250 MHz delta-sigma modulator for low cost ultrasound/sonar beamforming applicationsBoaz Shem-Tov, Mücahit Kozak, Eby G. Friedman. 113-116 [doi]
- Multibit ΔΣ CMOS DAC employing enhanced noise-shaped DEM architectureDmitry Akselrod, Shlomo Greenberg, Shlomo Hava. 117-120 [doi]
- Electromigration-dependent parametric yield estimationRoman Barsky, Israel A. Wagner. 121-124 [doi]
- Repeater insertion combined with LGR methodology for on-chip interconnect timing optimizationMichael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny. 125-128 [doi]
- 3D power grid modelingLarissa Zlydina, Yoad Yagil. 129-132 [doi]
- Pulse-forming reactance network shapes a quasi-rectangular pulse from sinusoidal voltageIgor M. Filanovsky, Xiaodai Dong. 133-136 [doi]
- Modeling of integrated monolithic transformers for silicon RF ICOuail El-Gharniti, Eric Kerherve, Jean-Baptiste Begueret, Pierre Jarry. 137-140 [doi]
- A CMOS focal-plane retinal sensor designed for shear motion detectionChung-Yu Wu, Wen-Chin Hsieh, Cheng-Ta Chiang. 141-144 [doi]
- Morton (Z) scan based real-time variable resolution CMOS image sensorEvgeny Artyomov, Yair Rivenson, Guy Levi, Orly Yadid-Pecht. 145-148 [doi]
- Low power global shutter CMOS active pixel image sensor with ultra-high dynamic rangeAlexander Fish, Alexander Belenky, Orly Yadid-Pecht. 149-152 [doi]
- CMOS APS photoresponse and crosstalk optimization analysis for scalable CMOS technologiesIgor Shcherback, Orly Yadid-Pecht. 153-155 [doi]
- CMOS SOI image sensorIgor Brouk, Yael Nemirovsky. 156-159 [doi]
- Impedance characteristics of decoupling capacitors in multi-power distribution systemsMikhail Popovich, Eby G. Friedman. 160-163 [doi]
- Low energy asynchronous addersIlya Obridko, Ran Ginosar. 164-167 [doi]
- 3 electro-optic modulator with quasi-phase-match coplanar waveguide structure for time-domain applicationsOleg V. Kolokoltsev, Svetlana V. Koshevaya, Rodrigo Amezcua Correa, Javier Siqueiros Alatorre, Miguel A. Basurto-Pensado, Volodymyr Grimalsky. 168-170 [doi]
- Noise characterization of the 0.35 μm CMOS analog process implemented in regular and SOI wafersIgor Brouk, Yael Nemirovsky. 171-174 [doi]
- A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSIHung-Pin Chen 0001, James B. Kuo. 175-178 [doi]
- A low power design on diffusive interconnection large-neighborhood cellular nonlinear network for giga-scale system applicationSheng-Hao Chen, Chung-Yu Wu. 179-182 [doi]
- A learnable self-feedback ratio-memory cellular nonlinear network (SRMCNN) for associative memory applicationsJui-Lin Lai, Chung-Yu Wu. 183-186 [doi]
- VLSI implementation of the universal 2-D CAT/ICAT systemRong-Jian Chen, Jui-Lin Lai. 187-190 [doi]
- Optimal structure of interconnection lines for GHz giga-scale nano-CMOS system-on-chip designChung-Yu Wu, Jen-Chieh Wang. 191-194 [doi]
- Spintronic logic circuit design for nanoscale computationJie Chen 0002, Chao Wang, Qinwei Shi. 195-198 [doi]
- Towards a spiking VLSI implementation of Freeman's olfactory modelThomas A. Holz, John G. Harris. 199-202 [doi]
- A winner-take-all spiking network with spiking inputsMatthias Oster, Shih-Chii Liu. 203-206 [doi]
- Spatial acuity modulation of an address-event imagerR. Jacob Vogelstein, Udayan Mallik, Eugenio Culurciello, Ralph Etienne-Cummings, Gert Cauwenberghs. 207-210 [doi]
- Improved ON/OFF temporally differentiating address-event imagerPatrick Lichtsteiner, Tobi Delbrück, Jörg Kramer. 211-214 [doi]
- Active pixel sensor with on-chip normal flow computation on the read outViktor Gruev, Ralph Etienne-Cummings. 215-218 [doi]
- Security of neural cryptographyRachel Mislovaty, Einat Klein, Ido Kanter, Wolfgang Kinzel. 219-221 [doi]
- Texture boundary detection based on multiple and parallel cellular neural networksChin-Teng Lin, Chao-Hui Huang. 222-225 [doi]
- New conditions for exponential stability of delay impulsive neural networksZhichun Yang, Daoyi Xu, Jin Deng, Jianren Niu. 226-229 [doi]
- Global exponential stability of Cohen-Grossberg neural networks with multiple time-varying delaysJin Deng, Daoyi Xu, Zhichun Yang. 230-233 [doi]
- High speed and high resolution current loser-take-all circuit of O(N) complexityAlexander Fish, Vadim Milrud, Orly Yadid-Pecht. 234-237 [doi]
- Challenges in ultra deep submicrometer high performance VLSI circuitsEby G. Friedman. 238 [doi]
- Grand challenges in image processing and analysisAlfred M. Bruckstein. 239 [doi]
- Challenges in CMOS imager designOrly Yadid-Pecht. 240 [doi]
- Grand challenges in spatial-temporal computing on image flowsTamás Roska. 241 [doi]
- Hardware-efficient PRBGs based on 1-D piecewise linear chaotic mapsTommaso Addabbo, Massimo Alioto, Simone Bernardi, Ada Fort, Santina Rocchi, Valerio Vignoli. 242-245 [doi]
- An average low offset comparator for 1.25 Gsample/s ADC in 0.18 μm CMOSNikolas Stefanou, Sameer R. Sonkusale. 246-249 [doi]
- A 4 Gsps, 2-4 GHz input bandwidth, 3-bits flash A/D converterCyril Recoquillon, Jean-Baptiste Begueret, Yann Deval, Guy Montignac, Alain Baudry. 250-253 [doi]
- A 10-b 500 MSPS current-steering CMOS D/A converter with a self-calibrated current biasing techniqueSanghoon Hwang, Minkyu Song. 254-257 [doi]
- Signal processing building blocks for pipelined A/D converterKrzysztof Wawryn, Robert Suszynski, Bogdan Strzeszewski. 258-261 [doi]
- Shunt voltage regulators for autonomous induction generators. Part I: principles of operationAlon Kuperman, Raul Rabinovici. 262-265 [doi]
- Shunt voltage regulators for autonomous induction generators. Part II: circuits and systemsAlon Kuperman, Raul Rabinovici. 266-269 [doi]
- High-voltage tolerant watchdog comparator in a low-voltage CMOS technologyVladislav Y. Potanin, Elena E. Potanina. 270-273 [doi]
- A restriction on the power system by theoretical requisitions of the BCU methodNingqiang Jiang, Wenzhong Song. 274-277 [doi]
- Performance of a glucose AFCLea Mor, Eugenia Bubis, Kas Hemmes, Pinchas Schechner. 278-281 [doi]
- thp extractor circuitsYanbin Wang, Garry Tarr, Yanjie Wang. 282-285 [doi]
- Fuzzy decision diagram realization by analog CMOS summing amplifiersVictor Varshavsky, Ilya Levin, Vyacheslav Marakhovsky, Alex Ruderman, Nataly Kravchenko. 286-289 [doi]
- A low-power analog spike detector for extracellular neural recordingsChristy L. Rogers, John G. Harris. 290-293 [doi]
- A 2.4 GHz fully CMOS integrated RF transceiver for 802.11b wireless LAN applicationWeixin Kong, Chianghua Ye, H. C. Lin. 294-297 [doi]
- Design of a differential chaotic Colpitts oscillatorOdysseus Tsakiridis, Evangelos Zervas, Dimitris Syvridis, M. Tsilis, John Stonham. 298-301 [doi]
- Multistage quantization via conditional hierarchical mappingAmit Eshet, Meir Feder. 302-305 [doi]
- Ring-shaped N+/P-well photodiode: study of responsivity enhancementTatiana Danov, Igor Shcherback, Orly Yadid-Pecht. 306-309 [doi]
- A high precision and low noise S/H circuit design for video signal samplingXinquan Lai, Donglai Xu, Lvshun Hu, Hongyi Wang. 310-313 [doi]
- Stencil shadow volumes for complex and deformable objectsIvica Kolic, Zeljka Mihajlovic, Leo Budin. 314-317 [doi]
- Algorithm for facial weight-change [image weight-change simulator]Udy Danino, Nahum Kiryati, Miriam Furst. 318-321 [doi]
- A spike-based adaptive filterXiaoxiang Gong, John G. Harris. 322-325 [doi]
- A robust offset cancellation scheme for analog multipliers [utilises digital integrator]Xiaofeng Wang, Zhouyuan Shi, Sameer Sonkusale. 326-329 [doi]
- Sparse approximations with a high resolution greedy algorithmBenjamin G. Salomon, Hanoch Ur. 330-333 [doi]
- A CPFSK/PSK-phase reconstruction-receiver for enhanced data rate Bluetooth systemsDieter Brückmann, Markus Hammes, André Neubauer. 334-337 [doi]
- A low complexity coordinated FEXT cancellation for VDSLAmir Leshem, Youming Li. 338-341 [doi]
- Fast acquisition CDMA receiver for burst transmission systemDanny M. Frai, Arie Reichman. 342-345 [doi]
- ML iterative tentative-decision-directed (ML-ITDD): a carrier synchronization system for short packet turbo coded communicationYossef Rahamim, Avraham Freedman, Arie Reichman. 346-349 [doi]
- Timing recovery of PAM signals using baud rate interpolationNaftali Sommer. 350-353 [doi]
- Analysis of lock-loss events in discrete-time phase locked loop (PLL)Liran Brecher, Naftali Sommer, Ehud Weinstein. 354-357 [doi]
- Implementation of the Berlekamp-Massey algorithm using a DSPShlomo Greenberg, Nir Feldblum, Gal Melamed. 358-361 [doi]
- Experimental extraction of point defects parameters needed for 2-D process modeling using reverse modelingEitan N. Shauly, Richard Ghez, Yigal Komem. 362-364 [doi]
- Analysis and simulation of spiral inductor fabricated on silicon substrateSadayuki Yoshitomi. 365-368 [doi]
- Efficient CAD development for emerging technologies using Objective-C and CocoaBryan A. Brady, Alex K. Jones, Ivan S. Kourtev. 369-372 [doi]
- Design of waveguiding photonic bandgap devices by using the resonant PBG device Bloch-Floquet theoremAgostino Giorgio, Roberto Diana, Anna Gina Perri. 373-376 [doi]
- Evaluation of the new OASIS format for layout fill compressionYu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng. 377-382 [doi]
- SOC modeling methodology for architectural exploration and software developmentMichal Silbermintz, Amir Sahar, Itay Peled, Moshe Anschel, Emil Watralov, Hillel Miller, Eytan Weisberger. 383-386 [doi]
- Enhancement of the semisymbolic analysis precision using the variable-length arithmeticJosef Dobes, Jan Míchal. 387-390 [doi]
- Modeling of analog circuits by using support vector regression machinesVladimir Ceperic, Adrijan Baric. 391-394 [doi]
- Analysis of harmonic distortion in deep submicron CMOSMatthias Bucher, Antonios Bazigos, Nikolaos Nastos, Yannis Papananos, François Krummenacher, Sadayuki Yoshitomi. 395-398 [doi]
- A compact method for obtaining the hybrid parameters of the BJT amplifierQassem Al-Zoubi, Adnan Al-Smadi. 399-402 [doi]
- Design and modelling of network on chip interconnects using transmission linesAnastasia Barger, David Goren, Avinoam Kolodny. 403-406 [doi]
- Signal propagation without distortion in dispersive lossy mediaRobert H. Flake, John F. Biskup. 407-410 [doi]
- Optimal resizing of bus wires in layout migrationShay Michaely, Shmuel Wimer, Avinoam Kolodny. 411-414 [doi]
- Buffer sizing for delay uncertainty induced by process variationsDimitrios Velenis, Ramyashree Sundaresha, Eby G. Friedman. 415-418 [doi]
- Optimization of chip level clock tree performance by using simultaneous drivers and wire sizingShlomo Greenberg, Ido Bloch, Moti Horwitz, Avishay Maman. 419-423 [doi]
- New ISFET catheters encapsulation techniques for brain pH in-vivo monitoringLiby Sudakov-Boreysha, Uri Dinnar, Yael Nemirovsky. 424-426 [doi]
- The ESO-Pill™: a non-invasive MEMS capsule for bolus transit monitoring in the esophagusYu-Ting Jui, Daniel C. Sadowski, Karan V. I. S. Kaler, Martin P. Mintchev. 427-430 [doi]
- Microlens array help imaging hidden objects for medical applicationsDavid Abookasis, Joseph Rosen. 431-434 [doi]
- Improvement of illumination artifacts in medical ultrasound images using a biologically based algorithm for compression of wide dynamic rangeHedva Spitzer, Yair Zimmer. 435-438 [doi]
- Distributed system design and control via multiple objectives optimizationAllon Guez, Robert E. Cochran, Ilan Rusnak. 439-442 [doi]
- Controlling an electrical motion system by a load instruction decoding algorithm using FPGASimon Cooper, Alon Kuperman, Raul Rabinovici. 443-446 [doi]
- Nanorobotic challenges in biomedical applications, design and controlAdriano Cavalcanti, Lior Rosen, Luiz C. Kretly, Moshe Rosenfeld, Shmuel Einav. 447-450 [doi]
- Numerical algorithm for measurement of angle phase shift for sines signalAbdulah Aksamovic, Samim Konjicija. 451-454 [doi]
- A new method to analyse the unique steady state of nonlinear nonautonomous circuitsFeng Ping, Erzhi Wang, Peter Cooke, Yuanchun Shi. 455-458 [doi]
- 2D photonic crystals deposited on polymer piezoelectric substrates - new kind of MOEMSEdward Bormashenko, Roman Pogreb, Oleg Stanevsky, Yaniv Biton, Yelena Bormashenko, Vladimir Streltsov, Yehoshua Socol. 459-462 [doi]
- A method to design DWDM filters on photonic crystalsAgostino Giorgio, Roberto Diana, Anna Gina Perri. 463-466 [doi]
- A novel design and fabrication method of scanning micro-mirror for retinal scan displaysOmer Cohen, Yael Nemirovsky. 467-470 [doi]
- A novel design and fabrication method of a pyramidal shape chip for scanning micro mirrorOmer Cohen, Avshalom Shai, Yael Nemirovsky. 471-474 [doi]
- Compact RF-photonic configuration for highly resolved and ultra-fast extraction of carrier and information of radar signalZeev Zalevsky, Amir Shemer, Vardit Eckhouse, David Mendlovic, Shlomo Zach. 475-478 [doi]
- Automatic hardware-efficient SoC integration by QoS network on chipEvgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny. 479-482 [doi]
- Micro-modem - reliability solution for NoC communicationsArkadiy Morgenshtein, Evgeny Bolotin, Israel Cidon, Avinoam Kolodny, R. Ginosar. 483-486 [doi]
- Practical performance of planar spiral inductorsAli Telli, Simsek Demir, Murat Askar. 487-490 [doi]
- Criterion of design for small value integrated self-inductorsGilles Petit, Richard Kielbasa, Vincent Petit. 491-494 [doi]
- A high performance data-path to accelerate DSP kernelsMichalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis. 495-498 [doi]
- A 64-way VLIW/SIMD FPGA architecture and design flowAlex K. Jones, Raymond Hoare, Ivan S. Kourtev, Joshua Fazekas, Dara Kusic, John Foster, Sedric Boddie, Ahmed Muaydh. 499-502 [doi]
- The 1: 10 phased demultiplexer circuitSerafim Poriazis. 503-506 [doi]
- SystemC opportunities in chip design flowItai Yarom, Gabi Glasser. 507-510 [doi]
- Techniques for formal transformations of binary decision diagramsGiora Kolotov, Ilya Levin, Vladimir Ostrovsky. 511-514 [doi]
- Evaluating and comparing simulation verification vs. formal verification approach on block level designEyal Segev, Sharon Goldshlager, Hillel Miller, Oren Shua, Olga Sher, Shlomo Greenberg. 515-518 [doi]
- Pattern search in hierarchical high-level designsZvi Terem, Gila Kamhi, Moshe Y. Vardi, Amitai Irron. 519-522 [doi]
- Meta-heuristics hybridizing independent component analysis with genetic algorithmsJuan Manuel Górriz, Carlos García Puntonet, Moisés Salmerón, Elmar Wolfgang Lang. 523-526 [doi]
- Image registration and mosaicing of noisy acoustic camera imagesKio Kim, Nathan Intrator, Nicola Neretti. 527-530 [doi]
- Design of low cross-talk image transceiver device and controller circuitryYitzhak David, Nonel Thirer, Itzhak Baal-Zedaka, Uzi Efron. 531-534 [doi]
- ISFET CMOS compatible design and encapsulation challengesLiby Sudakov-Boreysha, Arkadiy Morgenshtein, Uri Dinnar, Yael Nemirovsky. 535-538 [doi]
- Computer aided design using CGH of a three-dimensional objectsDavid Abookasis, Joseph Rosen. 539-542 [doi]
- VLSI sensor for multiple targets detection and trackingAlexander Fish, Aleksander Spivakovsky, Alexander Golberg, Orly Yadid-Pecht. 543-546 [doi]
- High-speed assembly FFT implementation with memory reference reduction on DSP processorsYiyan Tang, Yuke Wang, Jin-Gyun Chung, Sang Seob Song, Myoung-Seob Lim. 547-550 [doi]
- Viterbi detection analysis on RLL encoded sequences [magnetic recording applications]Raul M. Putinica, Stefan Stancescu. 551-554 [doi]
- Reconstruction of nonuniformly sampled periodic signals: algorithms and stability analysisEvgeny Margolis, Yonina C. Eldar. 555-558 [doi]
- Minimax sampling with arbitrary spaces [signal sampling and reconstruction]Yonina C. Eldar, Tsvi G. Dvorkind. 559-562 [doi]
- A statistical technique for the determination of the noise power gain in higher-order Σ-Δ A/D converters excited by DC input signalsNeil A. Fraser, Behrouz Nowrouzian. 563-566 [doi]
- Efficient implementation of the keyed-hash message authentication code (HMAC) using the SHA-1 hash functionHarris E. Michail, Athanasios P. Kakarountas, Athanasios Milidonis, Costas E. Goutis. 567-570 [doi]
- Comparison of the hardware architectures and FPGA implementations of stream ciphersMichalis D. Galanis, Paris Kitsos, Giorgos Kostopoulos, Nicolas Sklavos, Odysseas G. Koufopavlou, Costas E. Goutis. 571-574 [doi]
- High performance cryptographic engine PANAMA: hardware implementationGeorgios N. Selimis, Paris Kitsos, Odysseas G. Koufopavlou. 575-578 [doi]
- Bulk encryption crypto-processor for smart cards: design and implementationNicolas Sklavos, Georgios N. Selimis, Odysseas G. Koufopavlou. 579-582 [doi]
- Fast high-level fault simulatorStanislaw Deniziak, Krzysztof Sapiecha. 583-586 [doi]
- Automatic system for VLSI on-chip clock synthesizers characterizationYefim Fefer, Sergey Sofer. 587-590 [doi]
- Investigation of on-chip PLL irregularities under stress conditions - case studyYoav Weizman, Yefim Fefer, Sergey Sofer, Ezra Baruch. 591-594 [doi]
- On-chip area-efficient spectrum analyzer for testing analog ICMiguel Angel Domínguez, José L. Ausín, Guido Torelli, J. Francisco Duque-Carrillo. 595-598 [doi]
- LURU: global-scope FPGA technology mapping with content-addressable memoriesJoshua M. Lucas, Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones. 599-602 [doi]
- Advanced timing of level-sensitive sequential circuitsBaris Taskin, Ivan S. Kourtev. 603-606 [doi]
- Performance improvement of edge-triggered sequential circuitsBaris Taskin, Ivan S. Kourtev. 607-610 [doi]
- Design of complementary filter pairs with canonical signed-digit coefficients using genetic algorithmLi Liang 0001, Majid Ahmadi, Maher A. Sid-Ahmed. 611-614 [doi]
- A design flow for inductively degenerated LNAsDavide Guermandi, Eleonora Franchi, Antonio Gnudi. 615-618 [doi]
- n minimizationGaurab Banerjee, David T. Becher, Celia Hung, Krishnamurthy Soumyanath, David J. Allstot. 619-622 [doi]
- A high-speed CMOS op-amp design technique using negative Miller capacitanceBoaz Shem-Tov, Mücahit Kozak, Eby G. Friedman. 623-626 [doi]
- Adaptive analog-to-digital conversion using self-dithering in data acquisition systemsJosé Miguel Dias Pereira, Pedro Silva Girão, Octavian Postolache. 627-630 [doi]
- Perspectives on scaling theory and CMOS technology - understanding the past, present, and futureDaniel Foty. 631-637 [doi]
- Advanced compact models: gateway to modern CMOS designGennady Gildenblat, Colin C. McAndrew, Hailing Wang, Weimin Wu, Daniel Foty, Laurent Lemaitre, Peter Bendix. 638-641 [doi]
- Practical aspects of MOS transistor model "accuracy" in modern CMOS technologyPeter Bendix, Daniel Foty, David Pachura. 642-645 [doi]
- A robust and fast model-based athlete contour tracking in diving videosYuan Xiong, Yi Zhang, Danya Yao. 646-649 [doi]
- Efficient Gabor expansion using non minimal dual Gabor windowsNagesh K. Subbanna, Yonina C. Eldar. 650-653 [doi]
- Efficient LDPC codes for joint source-channel codingHaggai Kfir, Ido Kanter. 654-657 [doi]
- Ultra low-power DFF based shift registers design for CMOS image sensors applicationsAlexander Fish, Vladislav Mosheyev, Vitali Linkovsky, Orly Yadid-Pecht. 658-661 [doi]