Shmuel Wimer - researchr alias

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Viewing Publication 1 - 47 from 47

2023

A Self-Refreshable Bit-Cell for Single-Cycle Refreshing of Embedded MemoriesBinyamin Frankel, Shmuel Wimer. TC, 72(2):513-519, February 2023. [doi]

Energy Efficiency of Opportunistic Refreshing for Gain-Cell Embedded DRAMBinyamin Frankel, Eyal Sarfati, Davide Rossi, Shmuel Wimer. tcasI, 70(4):1605-1612, April 2023. [doi]

2021

Resource allocation in rooted trees subject to sum constraints and nonlinear cost functionsNir Halman, Shmuel Wimer. ipl, 170:106114, 2021. [doi]

2018

Queuing-Based eDRAM Refreshing for Ultra-Low Power ProcessorsBinyamin Frankel, Roi Herman, Shmuel Wimer. TC, 67(9):1331-1340, 2018. [doi]

Optimal queuing-based memory refreshing algorithm for energy efficient processorsRoi Herman, Binyamin Frankel, Shmuel Wimer. cee, 71:505-514, 2018. [doi]

Accurate Shielded Interconnect Delay Estimation by Reconfigurable Ring OscillatorEyal Sarfati, Binyamin Frankel, Yitzhak Birk, Shmuel Wimer. tcas, 65-I(10):3435-3444, 2018. [doi]

2017

Probability-Driven Multibit Flip-Flop Integration With Clock GatingDoron Gluzer, Shmuel Wimer. tvlsi, 25(3):1173-1177, 2017. [doi]

Optimal VLSI Delay Tuning by Space Tapering With Clock-Tree ApplicationEyal Sarfati, Binyamin Frankel, Yitzhak Birk, Shmuel Wimer. tcas, 64(8):2160-2170, 2017. [doi]

2016

Energy efficient computing by multi-mode additionAmir Albeck, Shmuel Wimer. integration, 55:176-182, 2016. [doi]

Optimal VLSI Delay Tuning by Wire ShieldingBinyamin Frankel, Shmuel Wimer. jota, 170(3):1060-1067, 2016. [doi]

Opportunistic Refreshing Algorithm for eDRAM MemoriesAmit Kazimirsky, Shmuel Wimer. tcas, 63-I(11):1921-1932, 2016. [doi]

Optimal weight allocation in rooted treesShmuel Wimer. jco, 31(3):1023-1033, 2016. [doi]

Energy efficient deeply fused dot-product multiplication architectureShmuel Wimer, Israel Koren. asap 2016: 115-122 [doi]

2015

Mixing Drivers in Clock-Tree for Power Supply Noise ReductionYakov Kaplan, Shmuel Wimer. tcas, 62-I(5):1382-1391, 2015. [doi]

Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacingKonstantin Moiseev, Shmuel Wimer, Avinoam Kolodny. integration, 48:116-128, 2015. [doi]

Energy efficient hybrid adder architectureShmuel Wimer, Amnon Stanislavsky. integration, 48:109-115, 2015. [doi]

2014

A Low Energy and High Performance ${\rm DM}^{2}$ AdderItamar Levi, Amir Albeck, Alexander Fish, Shmuel Wimer. tcas, 61-I(11):3175-3183, 2014. [doi]

Cell-based interconnect migration by hierarchical optimizationEugene Shaphir, Ron Y. Pinter, Shmuel Wimer. integration, 47(2):161-174, 2014. [doi]

Planar CMOS to multi-gate layout conversion for maximal fin utilizationShmuel Wimer. integration, 47(1):115-122, 2014. [doi]

A Look-Ahead Clock Gating Based on Auto-Gated Flip-FlopsShmuel Wimer, Arye Albahari. tcas, 61-I(5):1465-1472, 2014. [doi]

Using well-solvable minimum cost exact covering for VLSI clock energy minimizationShmuel Wimer, Doron Gluzer, Uri Wimer. orl, 42(5):332-336, 2014. [doi]

Easy and difficult exact covering problems arising in VLSI power reduction by clock gatingShmuel Wimer. disopt, 14:104-110, 2014. [doi]

Design Flow for Flip-Flop Grouping in Data-Driven Clock GatingShmuel Wimer, Israel Koren. tvlsi, 22(4):771-778, 2014. [doi]

A low energy dual-mode adderShmuel Wimer, Amir Albeck, Israel Koren. cee, 40(5):1524-1537, 2014. [doi]

2013

On optimal flip-flop grouping for VLSI power minimizationShmuel Wimer. orl, 41(5):486-489, 2013. [doi]

2012

Using well-solvable quadratic assignment problems for VLSI interconnect applicationsBen Emanuel, Shmuel Wimer, Gershon Wolansky. DAM, 160(4-5):525-535, 2012. [doi]

The complexity of VLSI power-delay optimization by interconnect resizingKonstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. jco, 23(2):292-300, 2012. [doi]

The Optimal Fan-Out of Clock Network for Power Minimization by Adaptive GatingShmuel Wimer, Israel Koren. tvlsi, 20(10):1772-1780, 2012. [doi]

2011

A Cost Effective Centralized Adaptive Routing for Networks-on-ChipRan Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter, Shmuel Wimer. dsd 2011: 39-46 [doi]

The Wiener maximum quadratic assignment problemEranda Çela, Nina S. Schmuck, Shmuel Wimer, Gerhard J. Woeginger. disopt, 8(3):411-416, 2011. [doi]

2010

Interconnect power and delay optimization by dynamic programming in gridded design rulesKonstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. ispd 2010: 153-160 [doi]

Interconnect Bundle Sizing Under Discrete Design RulesKonstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. tcad, 29(10):1650-1654, 2010. [doi]

2009

Power-delay optimization in VLSI microprocessors by wire spacingKonstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. todaes, 14(4), 2009. [doi]

2008

Timing-aware power-optimal ordering of signalsKonstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. todaes, 13(4), 2008. [doi]

On optimal ordering of signals in parallel wire bundlesKonstantin Moiseev, Shmuel Wimer, Avinoam Kolodny. integration, 41(2):253-268, 2008. [doi]

2006

Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacingKonstantin Moiseev, Shmuel Wimer, Avinoam Kolodny. iscas 2006: [doi]

Optimal bus sizing in migration of processor designShmuel Wimer, Shay Michaely, Konstantin Moiseev, Avinoam Kolodny. tcas, 53(5):1089-1100, 2006. [doi]

2004

Optimal resizing of bus wires in layout migrationShay Michaely, Shmuel Wimer, Avinoam Kolodny. icecsys 2004: 411-414 [doi]

1993

An efficient algorithm for some multirow layout problemsJack A. Feldman, Israel A. Wagner, Shmuel Wimer. tcad, 12(8):1178-1185, 1993. [doi]

On Paths with the Shortest Average Arc Length in Weighted GraphsShmuel Wimer, Israel Koren, Israel Cederbaum. DAM, 45(2):169-179, 1993. [doi]

1992

Balanced Block Spacing for VLSI LayoutIsrael Cederbaum, Israel Koren, Shmuel Wimer. DAM, 40(3):303-318, 1992.

1989

Depth-first-search and dynamic programming algorithms for efficient CMOS cell generationReuven Bar-Yehuda, Jack A. Feldman, Ron Y. Pinter, Shmuel Wimer. tcad, 8(7):737-743, 1989. [doi]

Optimal aspect ratios of building blocks in VLSIShmuel Wimer, Israel Koren, Israel Cederbaum. tcad, 8(2):139-145, 1989. [doi]

1988

Optimal Aspect Ratios of Building Blocks in VLSIShmuel Wimer, Israel Koren, Israel Cederbaum. dac 1988: 66-72 [doi]

Analysis of strategies for constructive general block placementShmuel Wimer, Israel Koren. tcad, 7(3):371-377, 1988. [doi]

1987

Optimal Chaining of CMOS Transistors in a Functional CellShmuel Wimer, Ron Y. Pinter, Jack A. Feldman. tcad, 6(5):795-801, 1987. [doi]

1983

HOPLA-PLA optimization and synthesisShmuel Wimer, N. Sharfman. dac 1983: 790-794 [doi]

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