Abstract is missing.
- Message from the ASAP 2016 chairsDavid Thomas, Suhaib Fahmy. [doi]
- Compressed L1 data cache and L2 cache in GPGPUsEhsan Atoofian. 1-8 [doi]
- Adaptive ILP control to increase fault tolerance for VLIW processorsAnderson Luiz Sartor, Stephan Wong, Antonio C. S. Beck. 9-16 [doi]
- Supervised and unsupervised machine learning for side-channel based Trojan detectionDirmanto Jap, Wei He, Shivam Bhasin. 17-24 [doi]
- A grain in the silicon: SCA-protected AES in less than 30 slicesPascal Sasdrich, Tim Güneysu. 25-32 [doi]
- OpenCL-based erasure coding on heterogeneous architecturesGuoyang Chen, Huiyang Zhou, Xipeng Shen, Josh Gahm, Narayan Venkat, Skip Booth, John Marshall. 33-40 [doi]
- Unleashing the performance potential of CPU-GPU platforms for the 3D atmospheric Euler solverHaohuan Fu, Jingheng Xu, Lin Gan, Chao Yang, Wei Xue, Wenlai Zhao, Wen Shi, Xinliang Wang, Guangwen Yang. 41-49 [doi]
- HW/SW-database-codesign for compressed bitmap index processingSebastian Haas, Tomas Karnagel, Oliver Arnold, Erik Laux, Benjamin Schlegel, Gerhard Fettweis, Wolfgang Lehner. 50-57 [doi]
- Modulo scheduling of symbolically tiled loops for tightly coupled processor arraysMichael Witterauf, Alexandru Tanase, Frank Hannig, Jürgen Teich. 58-66 [doi]
- Efficient pointer management of stack data for software managed multicoresJian Cai, Aviral Shrivastava. 67-74 [doi]
- A unified software approach to specify pipeline and spatial parallelism in FPGA hardwareJongsok Choi, Ruolong Lian, Stephen Dean Brown, Jason Helge Anderson. 75-82 [doi]
- A multi-beam Scan Mode Synthetic Aperture Radar processor suitable for satellite operationMohammad Reza Mohammadnia, Lesley Shannon. 83-90 [doi]
- Synthesisable recursion for C++ HLS toolsDavid B. Thomas. 91-98 [doi]
- A Domain Specific Language for accelerated Multilevel Monte Carlo simulationsBen Lindsey, Matthew Leslie, Wayne Luk. 99-106 [doi]
- F-CNN: An FPGA-based framework for training Convolutional Neural NetworksWenlai Zhao, Haohuan Fu, Wayne Luk, Teng Yu, Shaojun Wang, Bo Feng, Yuchun Ma, Guangwen Yang. 107-114 [doi]
- Energy efficient deeply fused dot-product multiplication architectureShmuel Wimer, Israel Koren. 115-122 [doi]
- Guarding the guards: Enhancing LNS performance for common applicationsMark G. Arnold, Ed Chester, John R. Cowles. 123-130 [doi]
- New non-uniform segmentation technique for software function evaluationJustine Bonnot, Erwan Nogues, Daniel Ménard. 131-138 [doi]
- Parallel floating-point expansions for extended-precision GPU computationsSylvain Collange, Mioara Joldes, Jean-Michel Muller, Valentina Popescu. 139-146 [doi]
- Temporal frequent value localityLois Orosa, Rodolfo Azevedo. 147-152 [doi]
- A MPSoC cache design space exploration approach based on ABC algorithm to optimize energy consumption and performanceMarcus V. D. dos Santos, Edna Barros, Andre Aziz. 153-158 [doi]
- gemV: A validated toolset for the early exploration of system reliabilityKarthik Tanikella, Yohan Ko, Reiley Jeyapaul, Kyoungwoo Lee, Aviral Shrivastava. 159-163 [doi]
- On-chip networks for mixed-criticality systemsPolydoros Petrakis, Mohammed Abuteir, Miltos D. Grammatikakis, Kyprianos Papadimitriou, Roman Obermaisser, Zaher Owda, Antonis Papagrigoriou, Michael Soulie, Marcello Coppola. 164-169 [doi]
- Combining GPU and FPGA technology for efficient exhaustive interaction analysis in GWASJan Christian Kässens, Lars Wienbrandt, Manfred Schimmler, Jorge González-Domínguez, Bertil Schmidt. 170-175 [doi]
- Accelerating K-means clustering on a tightly-coupled processor-FPGA heterogeneous systemTarek S. Abdelrahman. 176-181 [doi]
- Design space exploration and constrained multiobjective optimization for digital predistortion systemsLin Li, Amanullah Ghazi, Jani Boutellier, Lauri Anttila, Mikko Valkama, Shuvra S. Bhattacharyya. 182-185 [doi]
- A hardware accelerator for the alignment of multiple DNA sequences in forensic identificationAntonyus P. A. Ferreira, Joao G. M. Silva, Jefferson R. L. Anjos, Luiz H. A. Figueiroa, Edna Natividade da Silva Barros, Manoel Eusebio de Lima, Victor Wanderley Costa de Medeiros. 186-190 [doi]
- Real time all intra HEVC HD encoder on FPGASachille Atapattu, Namitha Liyanage, Nisal Menuka, Ishantha Perera, Ajith Pasqual. 191-195 [doi]
- Parametrized system level design: Real-time X-Ray image processing case studyTsvetan Shoshkov, Todor Stefanov, Bart Kienhuis. 196-201 [doi]
- Pipelined FPGA implementation of numerical integration of the Hodgkin-Huxley modelRoberto R. Osorio. 202-206 [doi]
- FPGA-based frequency estimation of a DFB laser using Rb spectroscopy for space missionsChristian Spindeldreier, Thijs J. Wendrich, Ernst Maria Rasel, Wolfgang Ertmer, Holger Blume. 207-212 [doi]
- Bridging the FPGA programmability-portability Gap via automatic OpenCL code generation and tuningKonstantinos Krommydas, Ruchira Sasanka, Wu-chun Feng. 213-218 [doi]
- Configuration technique for adaptability of multicore processors on FPGATetsuo Miyauchi, Kiyofumi Tanaka. 219-220 [doi]
- Performance optimization of Jacobi stencil algorithms based on POWER8 architectureJingheng Xu, Haohuan Fu, Lin Gan, Yu Song, Hongbo Peng, Wen Shi, Guangwen Yang. 221-222 [doi]
- Display power reduction for mobile closed-source gamesZhinan Cheng, Xi Li, Jiachen Song, Beilei Sun, Xuehai Zhou, Chao Wang. 223-224 [doi]
- An efficient embedded processor for object detection using ASIP methodologyShanlin Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda. 225-226 [doi]
- An ESL framework for low power architecture design space explorationHend Affes, Amal Ben Ameur, Michel Auguin, François Verdier, Calypso Barnes. 227-228 [doi]
- soft-NEON: A study on replacing the NEON engine of an ARM SoC with a reconfigurable fabricJose Raul Garcia Ordaz, Dirk Koch. 229-230 [doi]
- Architecture for fractal dimension estimation based on Minkowski-Bouligand method using integer distancesIsabela Rossales, Maximiliam Luppe. 231-232 [doi]
- SHA-3 Instruction Set Extension for A 32-bit RISC processor architectureAhmed S. Eissa, Mahmoud A. Elmohr, Mostafa A. Saleh, Khaled E. Ahmed, Mohammed M. Farag. 233-234 [doi]
- Temporized data prefetching algorithm for NoC-based multiprocessor systemsMaria Cireno, Andre Aziz, Edna Barros. 235-236 [doi]
- HW/SW co-design based implementation of Gas discriminationAmine Ait Si Ali, Abbes Amira, Faycal Bensaali, Mohieddine Benammar, Amine Bermak. 237-238 [doi]
- Architecture for quadruple precision floating point division with multi-precision supportManish Kumar Jaiswal, Hayden Kwok-Hay So. 239-240 [doi]
- Oolong: A Baseband processor extension to the RISC-V ISACecil Accetti R. A. Melo, Edna Barros. 241-242 [doi]
- Relation-oriented resource allocation for multi-accelerator systemsTeng Yu, Bo Feng, Mark Stillwell, José Gabriel F. Coutinho, Wenlai Zhao, Shuang Liang, Wayne Luk, Alexander L. Wolf, Yuchun Ma. 243-244 [doi]