Konstantin Moiseev - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 9 from 9

2015

Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacingKonstantin Moiseev, Shmuel Wimer, Avinoam Kolodny. integration, 48:116-128, 2015. [doi]

2012

The complexity of VLSI power-delay optimization by interconnect resizingKonstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. jco, 23(2):292-300, 2012. [doi]

2010

Interconnect power and delay optimization by dynamic programming in gridded design rulesKonstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. ispd 2010: 153-160 [doi]

Interconnect Bundle Sizing Under Discrete Design RulesKonstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. tcad, 29(10):1650-1654, 2010. [doi]

2009

Power-delay optimization in VLSI microprocessors by wire spacingKonstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. todaes, 14(4), 2009. [doi]

2008

Timing-aware power-optimal ordering of signalsKonstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. todaes, 13(4), 2008. [doi]

On optimal ordering of signals in parallel wire bundlesKonstantin Moiseev, Shmuel Wimer, Avinoam Kolodny. integration, 41(2):253-268, 2008. [doi]

2006

Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacingKonstantin Moiseev, Shmuel Wimer, Avinoam Kolodny. iscas 2006: [doi]

Optimal bus sizing in migration of processor designShmuel Wimer, Shay Michaely, Konstantin Moiseev, Avinoam Kolodny. tcas, 53(5):1089-1100, 2006. [doi]

Sign in or sign up to see more results.

runs on WebDSL