Table of Contents

• Design automation - lessons of the past, challenges for the futureJohn S. Mayo. 1-2 [doi]
• Central DA and its role: An executive viewRobert J. Camoin. 3 [doi]
• Computer Design Language - Version Munich (CDLM) a modern multi-level languageWinfried Hahn. 4-11 [doi]
• Programmimg languages for hardware descriptionPeter Robinson, Jeremy Dion. 12-16 [doi]
• Zeus: A hardware description language for VLSIKarl J. Lieberherr, Svend E. Knudsen. 17-23 [doi]
• Microprocessor systems modeling with MODLANAdam Pawlak. 24 [doi]
• Chip assemblers: Concepts and capabilitiesRandy H. Katz, Shlomo Weiss. 25-30 [doi]
• A vertically integrated VLSI design environmentJonathan B. Rosenberg, David G. Boyer, John A. Dallen, Stephen W. Daniel, Charles J. Poirier, John Poulton, C. Durward Rogers, Neil Weste. 31-38 [doi]
• IBM FSD VLSI chip design methodologyK. Ahdoot, Rita R. Alvarodiaz, L. Crawley. 39-45 [doi]
• The IC Module Compiler, a VLSI system design aidN. J. Elias, Arthur W. Wetzel. 46-49 [doi]
• On fault detection in CMOS logic networksKuang-Wei Chiang, Zvonko G. Vranesic. 50-56 [doi]
• A new integrated system for PLA testing and verificationFabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto. 57-63 [doi]
• Test generation for MOS circuits using D-algorithmSunil K. Jain, Vishwani D. Agrawal. 64-70 [doi]
• Test generation for scan design circuits with tri-state modules and bidirectional terminalsTakuji Ogihara, Shinichi Murai, Yuzo Takamatsu, Kozo Kinoshita, Hideo Fujiwara. 71-78 [doi]
• Engineering Workstations: Tools or toys?Steve Sapiro. 79-80 [doi]
• Design/synthesis workshop sessionJ. Robert Logan. 81-82 [doi]
• An interactive simulation facility for the evaluation of shared-resource architectures (Parallel ARchitecture SIMulator - PARSIM)John A. Board Jr., Peter N. Marinos. 83-92 [doi]
• Aquarius: Logic simulation on an Engineering WorkstationAndrew Sangster, John Monahan. 93-99 [doi]
• BIMOS, an MOS oriented multi-level logic simulatorPiet Stevens, Guido Arnout. 100-106 [doi]
• An algorithm to compact a VLSI symbolic layout with mixed constraintsYuh-Zen Liao, Chak-Kuen Wong. 107-112 [doi]
• Graph-optimization techniques for IC layout and compactionGershon Kedem, Hiroyuki Watanabe. 113-120 [doi]
• Improved compaction by minimized length of wiresWerner L. Schiele. 121-127 [doi]
• Tutorial - Group TechnologyHriday R. Prasad. 128 [doi]
• Computer Aided Software Engineering (CASE)F. W. Day. 129-136 [doi]
• Software architecture for the implementation of a Computer-Aided Engineering systemCharles L. Leath, Steven J. Ollanik. 137-142 [doi]
• Program visualization: Graphics support for software developmentDavid Kramlich, Gretchen P. Brown, Richard T. Carling, Christopher F. Herot. 143-149 [doi]
• HAL: A block level HArdware Logic simulatorTohru Sasaki, Nobuhiko Koike, Kenji Ohmori, Kyoji Tomita. 150-156 [doi]
• Simulating pass transistor circuits using logic simulation machinesZeev Barzilai, Leendert M. Huisman, Gabriel M. Silberman, Donald T. Tang, Lin S. Woo. 157-163 [doi]
• Placement algorithms for custom VLSIKenneth J. Supowit, Eric A. Slutz. 164-170 [doi]
• A module interchange placement machineAlexander Iosupovicz, Clarence King, Melvin A. Breuer. 171-174 [doi]
• Automatic placement algorithms for high packing density V L S ITokinori Kozawa, Hidekazu Terai, Tatsuki Ishii, Michiyoshi Hayase, Chihei Miura, Yasushi Ogawa, Kuniaki Kishida, Norio Yamada, Yasuhiro Ohno. 175-181 [doi]
• A placement algorithm for array processorsDah-Juh Chyan, Melvin A. Breuer. 182-188 [doi]
• Incorporating the human factor in color CAD systemsFrancine S. Frome. 189-195 [doi]
• Diagnosis of TCM failures in the IBM 3081 Processor complexNandakumar N. Tendolkar. 196-200 [doi]
• Quality level and fault coverage for multichip modulesE. Kofi Vida-Torku, Charles E. Radke. 201-206 [doi]
• Functional testing of digital systemsKwok-Woon Lai, Daniel P. Siewiorek. 207-213 [doi]
• Critical path tracing - an alternative to fault simulationMiron Abramovici, Premachandran R. Menon, David T. Miller. 214-220 [doi]
• Formal verification of a real-time hardware designZerksis D. Umrigar, Vijay Pitchumani. 221-227 [doi]
• Formal design verification of digital systemsAnthony S. Wojcik. 228-234 [doi]
• Automating mask layout and specification panel sessionRobert Brian Cutler. 235-236 [doi]
• An overview of the design and verification subsystem of the Engineering Design SystemLarry N. Dunn. 237-238 [doi]
• A logic design front-end for improved engineering productivityFrank Rubin, Paul W. Horstmann. 239-245 [doi]
• Structured design verification: Function and timingC. J. Rimkus, Michael R. Wayne, D. D. Cheng, F. J. Magistro. 246-252 [doi]
• Design through transformationJ. B. Bendas. 253-256 [doi]
• Routing method for VLSI design using irregular cellsHans-Jürgen Rothermel, Dieter A. Mlynski. 257-262 [doi]
• Reducing channel density in standard cell layoutKenneth J. Supowit. 263-269 [doi]
• Pictures with parentheses: Combining graphics and procedures in a VLSI layout toolRobert N. Mayo, John K. Ousterhout. 270-276 [doi]
• Importance of device independence to the CADCAM industryJames R. Warner. 277-278 [doi]
• A multiple media delay simulator for MOS LSI circuitsKaoru Okazaki, Tomoko Moriya, Toshihiko Yahara. 279-285 [doi]
• Design aids for the simulation of bipolar gate arraysPatrick Kozak, Ajoy K. Bose, A. Gupta. 286-292 [doi]
• An improved switch-level simulator for MOS circuitsVijaya Ramachandran. 293-299 [doi]
• Design For Test Calculus: An algorithm for DFT rules checkingDilip K. Bhavsar. 300-307 [doi]
• Measured performance of a programmed implementation of the subscripted D-AlgorithmC. Benmehrez, J. F. McDonald. 308-315 [doi]
• Classes of diagnostic testsCharles Paulson. 316-322 [doi]
• Petri Net based search directing heuristics for test generationE. Kofi Vida-Torku, Beverly Messick Huey. 323-330 [doi]
• HEX: An instruction-driven approach to feature extractionMark Hofmann, Ulrich Lauther. 331-336 [doi]
• Hierarchical circuit extraction with detailed parasitic capacitanceGary M. Tarolli, William J. Herman. 337-345 [doi]
• Symbolic Parasitic Extractor for Circuit Simulation (SPECS)J. D. Bastian, M. Ellement, Priscilla J. Fowler, C. E. Huang, Lawrence P. McNamee. 346-352 [doi]
• A layout verification system for analog bipolar integrated circuitsErich Barke. 353-359 [doi]
• Solid model in geometric modelling system: HICADShinji Tokumasu, Yoshio Kunitomo, Yoshimi Ohta, Shigeru Yamamoto, Norihiro Nakajima. 360-366 [doi]
• Integration of solid modeling and data base management for CAD/CAMYung-Chia Lee, King-sun Fu. 367-373 [doi]
• UNIGRAFIXCarlo H. Séquin, Paul S. Strauss. 374-381 [doi]
• VERDI: A computer aided design system for development and city planningM. Bouyat, H. Botta, J. C. Vignat. 382-385 [doi]
• Workshop - technology design rules for design automationRonald Waxman, Melvin F. Heilweil, Tom Reinke, Robert Smith, Gayla J. Von Ehr. 387-388 [doi]
• Technology rules- the other side of technology dependent codeMelvin F. Heilweil. 389 [doi]
• Technology-independent circuit layoutRobert J. Smith II. 390-393 [doi]
• Technology design rules - a user's perspectiveThomas R. Reinke. 394 [doi]
• Position paper role of technology design rules in Design AutomationGayla J. Von Ehr. 395 [doi]
• Statistical techniques of timing verificationJames H. Shelly, David R. Tryon. 396-402 [doi]
• Path delay analysis for hierarchical building block layout systemEiji Tamura, Kimihiro Ogawa, Toshio Nakano. 403-410 [doi]
• Timing analysis for nMOS VLSINorman P. Jouppi. 411-418 [doi]
• The effect of register-transfer design tradeoffs on chip area and performanceJohn J. Granacki, Alice C. Parker. 419-424 [doi]
• VGAUA: The Variable Geometry Automated Universal Array layout SystemDavid C. Smith, Richard Noto, Fred Borgini, Shanti S. Sharma, Joseph C. Werbickas. 425-429 [doi]
• APSS: An automatic PLA synthesis systemM. W. Stebnisky, M. J. McGinnis, Joseph C. Werbickas, Rathin Putatunda, A. Feller. 430-435 [doi]
• Integrated computer aided design, documentation and manufacturing system for PCB electronicsMikko Tervonen, Hannu Lehikoinen, Timo Mukari. 436-443 [doi]
• "Minimizing PWB NC drilling"John D. Litke. 444-447 [doi]
• Simplification of CNC programming for PWB routingJ. Drier. 448 [doi]
• Partitioning and placement technique for bus-structured PWBGotaro Odawara, Kazuhiko Iijima, Tetsuro Kiyomatsu. 449-456 [doi]
• Linear ordering and application to placementSungho Kang. 457-464 [doi]
• Placement of circuit modules using a graph space approachKunio Fukunaga, Shoichiro Yamada, Harold S. Stone, Tamotsu Kasai. 465-471 [doi]
• Computer-aided partitioning of behavioral hardware descriptionsMichael C. McFarland. 472-478 [doi]
• The VLSI Design Automation Assistant: Prototype systemThaddeus J. Kowalski, Donald E. Thomas. 479-483 [doi]
• A method of automatic data path synthesisCharles Y. Hitchcock III, Donald E. Thomas. 484-489 [doi]
• Facet: A procedure for the automated synthesis of digital systemsChia-Jeng Tseng, Daniel P. Siewiorek. 490-496 [doi]
• N.mPc: A retrospectiveCharles W. Rose, Greg Ordy, Frederic I. Parke. 497-505 [doi]
• Functional models for VLSI designRoy L. Druian. 506-514 [doi]
• Functional simulation shortens the development cycle of a new computerRaymond Cheng, Brian Griffin, Kun Katsumata, John Welsh. 515-519 [doi]
• The N.2 SystemGreg Ordy, Charles W. Rose. 520-526 [doi]
• Computer Aided ProgrammingPaul Bassett. 527-529 [doi]
• PLEASURE: a computer program for simple/multiple constrained/unconstrained folding of Programmable Logic ArraysGiovanni De Micheli, Alberto L. Sangiovanni-Vincentelli. 530-537 [doi]
• Bounds on the saved area ratio due to PLA foldingWentai Liu, Daniel E. Atkins. 538-544 [doi]
• PRONTO: Quick PLA product reductionJorge Martínez-Carballido, V. Michael Powers. 545-552 [doi]
• Optimum reduction of programmable logic arrayT. C. Hu, Yue-Sun Kuo. 553-558 [doi]
• Robots in design (Panel Discussion)Ernest L. Hall. 559 [doi]
• Heuristics for the Circuit Realization ProblemJames Cohoon, Sartaj Sahni. 560-566 [doi]
• Binary Decision Diagrams: From abstract representations to physical implementationsJose S. Metos, John V. Oldfield. 567-570 [doi]
• Some Computer Aided Engineering System design principlesHenry L. Nattrass, Glen K. Okita. 571-577 [doi]
• General river routing algorithmChi-Ping Hsu. 578-583 [doi]
• A new channel routing problemHon Wai Leong, Chang L. Liu. 584-590 [doi]
• Hierarchical channel routerMichael Burstein, Richard N. Pelavin. 591-597 [doi]
• The relational data model for CAD(Tutorial/Panel/Workshop): Close encounters of the third normal formStanley Wong. 598 [doi]
• Tutorial: The relational data model for Design AutomationMark N. Haynie. 599-607 [doi]
• Edisim and Edicap: Graphical simulator interfacesDwight D. Hill. 608-614 [doi]
• An algebra for logic strength simulationPeter Flake, Philip Moorby, Gerry Musgrave. 615-618 [doi]
• A data structure for MOS circuitsChi-Yuan Lo, Hao N. Nham, Ajoy K. Bose. 619-624 [doi]
• VHSIC hardware description (VHDL) development programAl Dewey. 625-628 [doi]
• The UK5000 - successful collaborative development of an integrated design system for a 5000 gate CMOS array with built-in testJ. R. Grierson, B. Cosgrove, Daniel Richert, R. E. Halliwell, Harold Kirk, John C. Knight, John A. McLean, J. M. McGrail, C. O. Newton. 629-636 [doi]
• Placement of irregular circuit elements on non-uniform gate arraysHarold Kirk, P. D. Crowhurst, J. A. Skingley, J. Dan Bowman, G. L. Taylor. 637-643 [doi]
• Automatic routing of double layer gate arrays using a moving cursorB. D. Prazic, M. A. Bozier. 644-650 [doi]
• Optimisation of global routing for the UK5000 gate array by iterationC. O. Newton, Patricia A. Young. 651-657 [doi]
• Automatic layout for gate arrays with one layer of metalPeter Robinson. 658-664 [doi]
• An over-cell gate array channel routerHoward E. Krohn. 665-670 [doi]
• A new statistical model for gate array routingAbbas El Gamal, Zahir A. Syed. 671-674 [doi]
• A topology for semicustom array-structured LSI devices, and their automatic customisationP. Jennings. 675-681 [doi]
• Automatic batch processing in multilayer ceramic metallizationNeil DalCero. 682-685 [doi]
• CAD/CAM - the foundation for Computer Integrated ManufacturingRichard L. Simon. 686-700 [doi]
• Test strategy for microprocessersSunil K. Jain, Alfred K. Susskind. 703-708 [doi]
• A design verification methodology based on concurrent simulation and clock suppressionErnst Ulrich. 709-712 [doi]
• Total stuct-at-fault testing by circuit transformationAndrea S. LaPaugh, Richard J. Lipton. 713-716 [doi]
• Testing for bridging faults (shorts) in CMOS circuitsJohn M. Acken. 717-718 [doi]
• ILS - interactive logic simulatorGregory D. Jordan, Brij B. Popli. 719-720 [doi]
• ACE: A Circuit ExtractorAnoop Gupta. 721-725 [doi]
• MACH : a high-hitting pattern checker for VLSI mask dataAkira Tsukizoe, Jun'ya Sakemi, Tokinori Kozawa, Hiroshi Fukuda. 726-731 [doi]
• Consistency checking for MOS/VLSI circuitsNing-Sang Chang, Ravi Apte. 732-733 [doi]
• Space efficient algorithms for VLSI artwork analysisThomas G. Szymanski, Christopher J. Van Wyk. 734-739 [doi]
• Experiments with the SLIM Circuit CompactorRalph McGarity, Daniel P. Siewiorek. 740-746 [doi]
• CAF: A computer-assisted floorplanning toolAndré Leblond. 747-753 [doi]
• Laying the power and ground wires on a VLSI chipAnderew S. Moulton. 754-755 [doi]
• The Transfer of University Software for Industry UseRossane Wyleczuk, Lynn Meyer, Gigi Babcock. 756-761 [doi]
• A graphical tool for conceptual design of data base applicationsCarlo Batini, C. Costa. 762-773 [doi]
• UCAD: Building Design Automation with general purpose software tools on UNIXJames H. Tomkinson. 774-787 [doi]
• Behavioral level transformation in the CMU-DA systemRobert A. Walker, Donald E. Thomas. 788-789 [doi]
• HOPLA-PLA optimization and synthesisShmuel Wimer, N. Sharfman. 790-794 [doi]
• Internal connection problem in large optimized PLAsSamuel Chuquillanqui. 795-802 [doi]
• Microprocessor systems modeling with MODLANAdam Pawlak. 804-811 [doi]