John Poulton - researchr alias

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Viewing Publication 1 - 25 from 25

2019

2018

Hardware-Enabled Artificial IntelligenceWilliam J. Dally, C. Thomas Gray, John Poulton, Brucek Khailany, John M. Wilson 0002, Larry R. Dennison. vlsic 2018: 3-6 [doi]

2010

A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth ScalingBrian S. Leibowitz, Robert Palmer, John Poulton, Yohan Frans, Simon Li, John Wilson, Michael Bucher, Andrew M. Fuller, John G. Eyles, Marko Aleksic, Trey Greer, Nhat Nguyen. jssc, 45(4):889-898, 2010. [doi]

2007

2006

A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiverMike Yun He, John Poulton. jssc, 41(3):597-606, 2006. [doi]

2004

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/OsRamin Farjad-Rad, Anhtuyet Nguyen, James Tran, Trey Greer, John Poulton, William J. Dally, John H. Edmondson, Ramesh Senthinathan, Rohit Rathi, Ming-Ju Edward Lee, Hiok-Tiaq Ng. jssc, 39(9):1553-1561, 2004. [doi]

2003

Jitter transfer characteristics of delay-locked loops - theories and design techniquesMing-Ju Edward Lee, William J. Dally, Trey Greer, Hiok-Tiaq Ng, Ramin Farjad-Rad, John Poulton, Ramesh Senthinathan. jssc, 38(4):614-621, 2003. [doi]

CMOS High-Speed I/Os - Present and FutureM.-J. Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John Poulton. iccd 2003: 454-461 [doi]

A second-order semidigital clock recovery circuit based on injection lockingHiok-Tiaq Ng, Ramin Farjad-Rad, Ming-Ju Edward Lee, William J. Dally, Trey Greer, John Poulton, John H. Edmondson, Rohit Rathi, Ramesh Senthinathan. jssc, 38(12):2101-2110, 2003. [doi]

A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/OsHiok-Tiaq Ng, M.-J. Edward Lee, Ramin Farjad-Rad, Ramesh Senthinathan, William J. Dally, Anhtuyet Nguyen, Rohit Rathi, Trey Greer, John Poulton, John H. Edmondson, James Tran. cicc 2003: 77-80 [doi]

2002

A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chipsRamin Farjad-Rad, William J. Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, M.-J. Edward Lee, Rohit Rathi, John Poulton. jssc, 37(12):1804-1812, 2002. [doi]

2001

Digital systems engineeringWilliam J. Dally, John Poulton. Cambridge University Press, 2001.

1999

Problems and Prospects for Electrical SignalingJohn Poulton. arvlsi 1999: 326 [doi]

1998

A tracking clock recovery receiver for 4-Gbps signalingJohn Poulton, William J. Dally, Steve Tell. micro, 18(1):25-27, 1998. [doi]

1997

PixelFlow: The RealizationJohn G. Eyles, Steven Molnar, John Poulton, Trey Greer, Anselmo Lastra, Nick England, Lee Westover. egh 1997: 57-67 [doi]

An Embedded DRAM for CMOS ASICsJohn Poulton. arvlsi 1997: 288-302 [doi]

1992

PixelFlow: high-speed rendering using image compositionSteven Molnar, John G. Eyles, John Poulton. siggraph 1992: 231-240 [doi]

Breaking the frame-buffer bottleneck with logic-enhanced memoriesJohn Poulton, John G. Eyles, Steven E. Molnar, Henry Fuchs. cga, 12(6):65-74, 1992. [doi]

1989

Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memoriesHenry Fuchs, John Poulton, John G. Eyles, Trey Greer, Jack Goldfeather, David Ellsworth, Steven Molnar, Greg Turk, Brice Tebbs, Laura Israel. siggraph 1989: 79-88 [doi]

1987

Pixel-Planes 4: A SummaryJohn G. Eyles, John D. Austin, Henry Fuchs, Trey Greer, John Poulton. egh 1988: 183-207

1985

1983

A vertically integrated VLSI design environmentJonathan B. Rosenberg, David G. Boyer, John A. Dallen, Stephen W. Daniel, Charles J. Poirier, John Poulton, C. Durward Rogers, Neil Weste. dac 1983: 31-38 [doi]

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