Abstract is missing.
- Foundry Future: Challenges in the 21st CenturyMorris Chang. 18-23 [doi]
- Analog and Mixed-Signal Innovation: The Process-Circuit-System-Application InteractionLewis W. Counts. 24-30 [doi]
- Towards a New Nanoelectronic CosmologyJoël Hartmann. 31-37 [doi]
- Optical CommunicationsSung Min Park, Yuriy M. Greshishchev. 40-41 [doi]
- A Fully Integrated 4ÿ10Gb/s DWDM Optoelectronic Transceiver in a standard 0.13μm CMOS SOIAdithyaram Narasimha, Behnam Analui, Yi Liang, Thomas J. Sleboda, Cary Gunn. 42-586 [doi]
- A 90nm CMOS 16Gb/s Transceiver for Optical InterconnectsSamuel Palermo, Azita Emami-Neyestanak, Mark Horowitz. 44-586 [doi]
- A 20Gb/s Burst-Mode CDR Circuit Using Injection-Locking TechniqueJri Lee, Mingchung Liu. 46-586 [doi]
- A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOSLan-chou Cho, Chihun Lee, Shen-Iuan Liu. 48-586 [doi]
- A CMOS Burst-Mode TIA with Step AGC and Selective Internally Created Reset for 1.25Gb/s EPONQuan Le, Sang-Gug Lee, Ho-Yong Kang, Sang-Hoon Chang. 50-51 [doi]
- A 40mW 3.5kΩ 3Gb/s CMOS Differential Transimpedance Amplifier Using Negative-Impedance CompensationChia-Ming Tsai, Wen Tsao Chen. 52-586 [doi]
- A 40Gb/s Transimpedance-AGC Amplifier with 19dB DR in 90nm CMOSChih-Fan Liao, Shen-Iuan Liu. 54-586 [doi]
- A 1.2V 5.2mW 40dB 2.5Gb/s Limiting Amplifier in 0.18μm CMOS Using Negative-Impedance CompensationKwisung Yoo, Dongmyung Lee, Gunhee Han, Sung Min Park, Won-Seok Oh. 56-57 [doi]
- A Fractional-N PLL for SONET-Quality Clock-Syntlhesis ApplicationisAxel Thomsen, Ligang Zhang, Doug Frey, Q. Yu, Lizhong Sun, Akhil K. Garlapati, R. Hulfachor, Douglas F. Pastorello, Richard J. Juhn. 58-587 [doi]
- TD: Emerging Devices Devices and CircuitsEugenio Cantatore, Shuichi Tahara. 60-61 [doi]
- Efficient Power Management Circuit: Thermal Energy Harvesting to Above-IC Microbattery Energy StorageHélène Lhermet, Cyril Condemine, Marc Plissonnier, Raphael Salot, Patrick Audebert, Marion Rosset. 62-587 [doi]
- Minimum Energy Tracking Loop with Embedded DC-DC Converter Delivering Voltages down to 250mV in 65nm CMOSYogesh K. Ramadass, Anantha P. Chandrakasan. 64-587 [doi]
- LAGS System Using Data/Instruction Grain Power ControlMakoto Ikeda, Taku Sogabe, Ken Ishii, Masayuki Mizuno, Toru Nakura, Koichi Nose, Kunihiro Asada. 66-587 [doi]
- Gate Work Function Engineering for Nanotube-Based CircuitsZhihong Chen, Jörg Appenzeller, Paul M. Solomon, Yu-Ming Lin, Phaedon Avouris. 68-587 [doi]
- Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with ImperfectionsJie Deng, Nishant Patil, Koungmin Ryu, Alexander Badmaev, Chongwu Zhou, Subhasish Mitra, H.-S. Philip Wong. 70-588 [doi]
- An Organic Imager for Flexible Large Area ElectronicsIvan Nausieda, Kyungbum Kevin Ryu, Ioannis Kymissis, Akintunde Ibitayo Akinwande, Vladimir Bulovic, Charles G. Sodini. 72-73 [doi]
- Passive-Matrix Flexible Electronic Paper Using Quick-Response Liquid Powder Display (QR-LPD) Technollogy and Custom Driver CircuitsReiji Hattori, Michihiro Asakawa, Yoshitomo Masuda, Norio Nihei, Akihiko Yokoo, Shuhei Yamada, Itsuo Tanuma. 74-588 [doi]
- RF Building BlocksNikolaus Klemmer, Satoshi Tanaka. 76-77 [doi]
- A Digitally Modulated Polar CMOS PA with 20MHz Signal BWAmirpouya Kavousian, David K. Su, Bruce A. Wooley. 78-588 [doi]
- A 3W 55% PAE CMOS PA with Closed-Loop 20: 1 VSWR ProtectionFrancesco Carrara, Calogero D. Presti, Antonino Scuderi, Carmelo Santagati, Giuseppe Palmisano. 80-588 [doi]
- Combined Linear and Δ-Modulated Switched-Mode PA Supply Modulator for Polar TransmittersJennifer Kitchen, Wing-Yee Chu, Ilker Deligoz, Sayfe Kiaei, Bertan Bakkaloglu. 82-588 [doi]
- A Blocker Filtering Technique for Wireless ReceiversHooman Darabi. 84-588 [doi]
- A 0.13μm 1.5V CMOS I/Q Downconverter with Digital Adaptive IIP2 CalibrationKrzysztof Dufrene, Zdravko Boos, Robert Weigel. 86-589 [doi]
- A Delay-Line-Based GFSK Demodulator for Low-IF ReceiversHong-Sing Kao, Ming-Jen Yang, Tai-Cheng Lee. 88-589 [doi]
- A 4.5GHz LC-VCO with Self-Regulating TechniqueAleksander Dec, Kenji Suyama, Tomomitsu Kitamura. 90-589 [doi]
- A 3.2-to-7.3GHz Quadrature Oscillator with Magnetic TuningGiuseppe Cusmai, Matteo Repossi, Guido Albasini, Francesco Svelto. 92-589 [doi]
- MicroprocessorsStefan Rusu, Jim Warnock. 94-95 [doi]
- Design of the Power6 MicroprocessorJoshua Friedrich, Bradley D. McCredie, Norman K. James, Bill Huott, Brian W. Curran, Eric Fluhr, Gaurav Mittal, Eddie Chan, Yuen H. Chan, Donald W. Plass, Sam G. Chu, Hung Le, Leo Clark, John R. Ripley, Scott Taylor, Jack DiLullo, Mary Yvonne Lanzerotti. 96-97 [doi]
- An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOSSriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James Tschanz, David Finan, Priya Iyer, Arvind Singh, Tiju Jacob, Shailendra Jain, Sriram Venkataraman, Yatin Hoskote, Nitin Borkar. 98-589 [doi]
- A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power ConsumptionYutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara. 100-590 [doi]
- An Integrated Quad-Core Opteron ProcessorJ. Dorsey, S. Searles, Michael Ciraula, S. Johnson, N. Bujanos, D. Wu, M. Braganza, S. Meyers, E. Fang, R. Kumar. 102-103 [doi]
- A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O SubsystemsZongjian Chen, Priya Ananthanarayanan, Sukalp Biswas, Brian Campbell, Hao Chen, Shaishav Desai, Dominic Go, Rajat Goel, Vincent von Kaenel, Jason Kassoff, Fabian Klass, Weichun Ku, Tony Li, Jonathon Lin, Khurram Malik, Anup Mehta, Daniel Murray, Eric Shiu, Chris Shuler, Sribalan Santhanam, Greg Scott, Junji Sugisawa, Toshinari Takayanagi, Honkai John Tarn, Pradeep Trivedi, James Wang, Ricky Wen, John Yong. 104-105 [doi]
- The Implementation of the 65nm Dual-Core 64b Merom ProcessorNabeel Sakran, Marcelo Yuffe, Moty Mehalel, Jack Doweck, Ernest Knoll, Avi Kovacs. 106-590 [doi]
- An 8-Core 64-Thread 64b Power-Efficient SPARC SoCUmesh Gajanan Nawathe, Mahmudul Hassan, Lynn Warriner, King Yen, Bharat Upputuri, David Greenhill, Ashok Kumar, Heechoul Park. 108-590 [doi]
- UWB and mm-Wave Communications SystemsSang-Gug Lee, Ranjit Gharpurey. 110-111 [doi]
- A WiMedia-Compliant UWB Transceiver in 65nm CMOSJos Bergervoet, Harish Kundur Subramaniyan, S. Lee, Domine Leenaerts, Remco van de Beek, Gerard Van der Weide, Raf Roovers. 112-590 [doi]
- A 0.18μm CMOS Dual-Band UWB TransceiverYuanjin Zheng, King-Wah Wong, M. Annamalai Asaru, Dan Shen, Wen Hu Zhao, Yen Ju The, P. Andrew, Fujiang Lin, Wooi Gan Yeoh, Rajinder Singh. 114-590 [doi]
- A 2.5nJ/b 0.65V 3-to-5GHz Subbanded UWB Receiver in 90nm CMOSFred S. Lee, Anantha P. Chandrakasan. 116-590 [doi]
- A 47pJ/pulse 3.1-to-5GHz All-Digital UWB Transmitter in 90nm CMOSDavid D. Wentzloff, Anantha P. Chandrakasan. 118-591 [doi]
- A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4aJulien Ryckaert, Geert Van der Plas, Vincent De Heyn, Claude Desset, Geert Vanwijnsberghe, Bart van Poucke, Jan Craninckx. 120-591 [doi]
- A 1.2V 240MHz CMOS Continuous-Time Low-Pass Filter for a UWB Radio ReceiverVille Saari, Mikko Kaltiokallio, Saska Lindfors, Jussi Ryynänen, Kari Halonen. 122-591 [doi]
- A Fully Integrated 24GHz 4-Channel Phased-Array Transceiver in 0.13μm CMOS Based on a Variable-Phase Ring Oscillator and PLL ArchitectureHarish Krishnaswamy, Hossein Hashemi. 124-591 [doi]
- A Bandpass ΔΣ DDFS-Driven 19GHz Frequency Synthesizer for FMCW Automotive RadarHoon Hee Chung, Umar Lyles, Tino Copani, Bertan Bakkaloglu, Sayfe Kiaei. 126-591 [doi]
- Display ElectronicsHiroyuki Hirashima, Oh-Kyong Kwon. 128-129 [doi]
- An 8b Source Driver for 2.0 inch Full-Color Active-Matrix OLEDs Made with LTPS TFTsYong Sung Park, Do-Youb Kim, Keum-Nam Kim, Yojiro Matsueda, Jong-Hyun Choi, Chul-Kyu Kang, Hye-Dong Kim, Ho Kyoon Chung, Oh-Kyong Kwon. 130-592 [doi]
- A 2.6 inch VGA LCD with Optical Input Function using a 1-Transistor Active-Pixel SensorChris Brown, Ben Hadwen, Hiromi Kato. 132-592 [doi]
- An Integrated LDI with Readout Function for Touch-Sensor-Embedded Display PanelsYoon Kyung Choi, Hyoung-rae Kim, Won-Gab Jung, Min-Soo Cho, Zhong-Yuan Wu, Hyo-Sun Kim, Younghun Lee, KyungMyun Kim, Kyu-Sam Lee, JongSeon Kim, Myunghee Lee. 134-135 [doi]
- A Single-Inductor Step-Up DC-DC Switching Converter with Bipolar Outputs for Active Matrix OLED Mobile Display PanelsChang-Seok Chae, Hanh-Phuc Le, Kwang-Chan Lee, Min-Chul Lee, Gyu-Hyeong Cho, Gyu-Ha Cho. 136-592 [doi]
- A 10b Driver IC for a Spatial Optical Modulator for Full HDTV ApplicationsJin-Seong Kang, Jin-Ho Kim, Seon-Yung Kim, Jun-Yong Song, Oh-Kyong Kwon, Yuen-Joong Lee, Byung-Hoon Kim, Chan-Woo Park, Kyoung-Soo Kwon, Won-Tae Choi, Sang-Kyeong Yun, In-Jae Yeo, Kyu-Bum Han, Taek-Soo Kim, Sang Il Park. 138-592 [doi]
- A 16.7M Color VGA Display Driver IC with Partial Graphic RAM and 500Mb/s/ch Serial Interface for Mobile a-Si TFT-LCDsKyung-suc Nah, Hyeokchul Kwon, Jae-Youl Lee, Dukmin Lee, Jun-Seok Han, Young-hun Lee, Hyeyeong Rho, JongSeon Kim, Bongnam Kim, Myunghee Lee. 140-592 [doi]
- A Column Driver with Low-Power Area-Efficient Push-Pull Buffer Amplifiers for Active-Matrix LCDsYoung-Suk Son, Ji-Hun Kim, Hyun-Ho Cho, Ju-Pyo Hong, Joon-Ho Na, Dae Seong Kim, Dae-Keun Han, Jin-Cheol Hong, Yong-Joon Jeon, Gyu-Hyeong Cho. 142-143 [doi]
- SE3 Last Mile Access Options: PON/DSL/Cable/WirelessLarry DeVito, Yusuke Ohtomo. 144-145 [doi]
- E1 Ultimate Limits of Integrated ElectronicsNicky Lu, C. K. Wang, Philip Wong, Sreedhar Natarajan. 146-147 [doi]
- SE4 Automotive Signal Processing TechnologiesToru Shimizu, Ram Krishnamurthy. 148-149 [doi]
- Biomedical DevicesRoland Thewes, Dennis Polla. 150-151 [doi]
- A 232-Channel Visual Prosthesis ASIC with Production-Compliant Safety and TestabilityMaurits Ortmanns, N. Linger, A. Rocke, S. Rackow, M. Gehrke, H. J. Tiedtke. 152-593 [doi]
- A Fully Integrated Digital Hearing-Aid Chip with Human-Factors ConsiderationsSunyoung Kim, Seungjin Lee, Namjun Cho, Seong-Jun Song, Hoi-Jun Yoo. 154-593 [doi]
- A Non-Coherent PSK Receiver with Interference-Canceling for Transcutaneous Neural ImplantsMingcui Zhou, Wentai Liu. 156-593 [doi]
- An 11k-Electrode 126-Channel High-Density Microelectrode Array to Interact with Electrogenic CellsUrs Frey, Flavio Heer, René Pedron, Sadik Hafizovic, Frauke Greve, Jan Sedivý, Kay-Uwe Kirstein, Andreas Hierlemann. 158-593 [doi]
- 256-Channel Neural Recording Microsystem with On-Chip 3D ElectrodesJoseph N. Y. Aziz, Roman Genov, Miron Derchansky, Berj L. Bardakjian, Peter L. Carlen. 160-594 [doi]
- A 2.2μW 94nV/√Hz, Chopper-Stabilized Instrumentation Amplifier for EEG Detection in Chronic ImplantsTimothy Denison, Kelly Consoer, Andy Kelly, April Hachenburg, Wesley Santa. 162-594 [doi]
- A Current-Sensitive Front-End Amplifier for Nano-Biosensors with a 2MHz BWGiorgio Ferrari, Fabio Gozzini, Marco Sampietro. 164-165 [doi]
- Miniaturization of Magnetic Resonance Microsystem Components for 3D Cell ImagingLong-Sheng Fan, Shawn S. H. Hsu, Jun-De Jin, Cheng-Vu Hsieh, Wei-Chen Lin, H. C. Hao, Hsin-Li Cheng, Kuo-Chin Hsueh, Chen-Zong Lee. 166-594 [doi]
- A High-Density Magnetoresistive Biosensor Array with Drift-Compensation MechanismShu-Jen Han, Heng Yu, Boris Murmann, Nader Pourmand, Shan X. Wang. 168-594 [doi]
- ClockingThucydides Xanthopoulos, Atila Alvandpour. 170-171 [doi]
- A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOIAlexander Rylyakov, José A. Tierno, George English, Daniel J. Friedman, M. Megheli. 172-173 [doi]
- A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test CapabilityShunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno. 174-594 [doi]
- All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLsYong Liu, Woogeun Rhee, Daniel J. Friedman, Donhee Ham. 176-595 [doi]
- A 40GHz DLL-Based Clock Generator in 90nm CMOS TechnologyChi-Nan Chuang, Shen-Iuan Liu. 178-595 [doi]
- 12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled TechniqueMamoru Sasaki, Mitsuru Shiozaki, Atsushi Mori, Atsushi Iwata, Hiroaki Ikeda. 180-595 [doi]
- An Adaptive Low-Jitter LC-Based Clock DistributionLi-min Lee, Chih-Kong Ken Yang. 182-595 [doi]
- A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCCDongsuk Shin, Janghoon Song, Hyunsoo Chae, Kwan-Weon Kim, Young-Jung Choi, Chulwoo Kim. 184-595 [doi]
- mm-Wave Tranceivers and Building BlocksAli Niknejad, Hiroyuki Sakai. 186-187 [doi]
- A mm-Wave CMOS Heterodyne Receiver with On-Chip LO and DividerBehzad Razavi. 188-596 [doi]
- A Highly Integrated 60GHz CMOS Front-End ReceiverSohrab Emami, Chinh H. Doan, Ali M. Niknejad, Robert W. Brodersen. 190-191 [doi]
- A 60GHz Low-Power Six-Port Transceiver for Gigabit Software-Defined Transceiver ApplicationsChi-Hsueh Wang, Hong-Yeh Chang, Pei-Si Wu, Kun-You Lin, Tian-Wei Huang, Huei Wang, Chun-Hsiung Chen. 192-596 [doi]
- A 23-to-29GHz Differentially Tuned Varactorless VCO in 0.13μm CMOSKa Chun Kwok, John R. Long, John J. Pekarik. 194-596 [doi]
- A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOSChihun Lee, Shen-Iuan Liu. 196-596 [doi]
- A 90GHz 65nm CMOS Injection-Locked Frequency DividerPierre Mayr, Christopher Weyers, Ulrich Langmann. 198-596 [doi]
- Low-Power mm-Wave Components up to 104GHz in 90nm CMOSBabak Heydari, Mounir Bohsali, Ehsan Adabi, Ali M. Niknejad. 200-597 [doi]
- A Bidirectional RF-Combining 60GHz Phased-Array Front-EndArun Natarajan, Brian A. Floyd, Ali Hajimiri. 202-597 [doi]
- TV Tuner / RFIDDavid Su, Bud Taddiken. 204-205 [doi]
- A 48-to-860MHz CMOS Direct-Conversion TV TunerM. Gupta, S. Lerstaveesin, D. Kang, B. S. Song. 206-597 [doi]
- A SiP Tuner with Integrated LC Tracking Filter for both Cable and Terrestrial TV ReceptionVincent Fillatre, Jean-Robert Tourret, Sébastien Amiot, Maxime Bernard, Mohamed Bouhamame, Claude Caron, Olivier Crand, Alexandre Daubenfeld, Gilles Denise, Thibault Kervaon, Markus Kristen, Luca Lo Coco, Frederic Mercier, Jean Marc Paris, Sébastien Prouet, Vincent Rambeau, Sebastien Robert, F. Seneschal, Jan van Sinderen, O. Susplugas. 208-597 [doi]
- A Multi-Standard Analog and Digital TV Tuner for Cable and Terrestrial ApplicationsJan-Michael Stevenson, Phil Hisayasu, Armin Deiss, Buddhika Abesingha, Kim Beumer, Jose Esquivel. 210-597 [doi]
- A Digital TV Receiver RF and BB Chipset with Adaptive Bias-Current Control for Mobile ApplicationsTakae Sakai, Shinya Ito, Nobuyoshi Kaiki, Atsushi Sakai, Mamoru Okazaki, Masayuki Natsumi, Akira Saito, Kazumasa Kioi, Masato Koutani, Koutani Kagoshima, Shuichi Kawama, Hiroshi Kijima, Shinji Toyoyama, Nobutoshi Matsunaga, Mutsumi Hamaguchi, Hiroshi Kawamura, Kunihiko Iizuka. 212-597 [doi]
- A 900MHz UHF RFID Reader Transceiver ICIssy Kipnis, Scott Chiu, Marc Loyer, J. Carrigan, Jan Rapp, Peter Johansson, David Westberg, Jonas Johansson. 214-598 [doi]
- A Single-Chip CMOS Transceiver for UHF Mobile RFID ReaderIckjin Kwon, Heemun Bang, Kyudon Choi, Sangyoon Jeon, Sungjae Jung, Donghyun Lee, YunSeong Eo, Heungbae Lee, Bongyoung Chung. 216-598 [doi]
- An Integrated RFID ReaderAminghasem Safarian, Amin Shameli, Ahmadreza Rofougaran, Maryam Rofougaran, Franco De Flaviis. 218-598 [doi]
- Gigabit CDRs EqualizersJohn T. Stonick, Jri Lee. 220-221 [doi]
- A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCODo-Hwan Oh, Deok-Soo Kim, Suhwan Kim, Deog Kyoon Jeong, Wonchan Kim. 222-598 [doi]
- A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUXNikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker. 224-598 [doi]
- A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOSThomas Toifl, Christian Menolfi, Peter Buchmann, Christoph Hagleitner, Marcel A. Kossel, Thomas Morf, Jonas Weiss, Martin L. Schmatz. 226-598 [doi]
- A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDRBrian S. Leibowitz, Jade Kizer, Haechang Lee, Fred Chen, Andrew Ho, Metha Jeeradit, Akash Bansal, Trey Greer, Simon Li, Ramin Farjad-Rad, William F. Stonecypher, Yohan Frans, Barry Daly, Fred Heaton, Bruno W. Garlepp, Carl W. Werner, Nhat Nguyen, Vladimir Stojanovic, Jared Zerbe. 228-599 [doi]
- A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE ReceiverMatt Park, John F. Bulzacchelli, Michael P. Beakes, Daniel J. Friedman. 230-599 [doi]
- A CMOS 1Gb/s 5-Tap Transversal Equalizer Based on Inductorless 3rd-Order Delay CellsDavid Hernandez-Garduno, José Silva-Martínez. 232-599 [doi]
- Cascading Techniques for a High-Speed Memory InterfaceZheng Gu, Peter Gregorius, Daniel Kehrer, Lydia Neumann, Evelyn Neuscheler, Thomas Rickes, Hermann Ruckerbauer, Ralf Schledz, Martin Streibl, Jürgen Zielbauer. 234-599 [doi]
- ΔΣ ADCs and Converter TechniquesZhongyuan Chang, Tatsuji Matsuura. 236-237 [doi]
- A 56mW CT Quadrature Cascaded ΣΔ Modulator with 77dB DR in a Near Zero-IF 20MHz BandLucien J. Breems, Robert Rutten, Robert H. M. van Veldhoven, Gerard Van der Weide, Henk A. H. Termeer. 238-599 [doi]
- A 0.13μm CMOS EDGE/UMTS/WLAN Tri-Mode ΔΣ ADC with -92dB THDThomas Christen, Thomas Burger, Qiuting Huang. 240-599 [doi]
- A 1.2V 121-Mode CT ΔΣ Modulator for Wireless Receivers in 90nm CMOSSotir Ouzounov, Robert van Veldhoven, Corné Bastiaansen, K. Vongehr, R. van Wegberg, Govert Geelen, Lucien J. Breems, Arthur H. M. van Roermund. 242-600 [doi]
- th-order CT/DT Multi-Mode ΔΣ ModulatorBas M. Putter. 244-245 [doi]
- A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOSJan Craninckx, Geert Van der Plas. 246-600 [doi]
- A 14b 40MS/s Redundant SAR ADC with 480MHz Clock in 0.13pm CMOSM. Hesener, T. Eichler, A. Hanneberg, D. Herbison, F. Kuttner, H. Wenske. 248-600 [doi]
- A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13μm CMOSMartin Clara, Wolfgang Klatzer, Berthold Seger, Antonio Di Giandomenico, Luca Gori. 250-600 [doi]
- Baseband Signal ProcessingSteffen Paul, Tzi-Dar Chiueh. 252-253 [doi]
- RTL-based Clock Recovery Architecture with All-Digital Duty-Cycle CorrectionPing-Ying Wang, Meng-Ta Yang, Shang-Ping Chen, Meng-Hsueh Lin, Jing-Bing Yang. 254-600 [doi]
- A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOSMark Anders, Sanu Mathew, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar. 256-600 [doi]
- A Telecom Baseband Circuit based on an Asynchronous Network-on-ChipDidier Lattard, Edith Beigné, Christian Bernard, Catherine Bour, Fabien Clermidy, Yves Durand, Jean Durupt, Didier Varreau, Pascal Vivet, Pierre Penard, Arnaud Bouttier, Friedbert Berens. 258-601 [doi]
- A 50mW HSDPA Baseband Receiver ASIC with Multimode Digital Front-EndChiara Martelli, Robert Reutemann, Christian Benkeser, Qiuting Huang. 260-601 [doi]
- A 65nm C64x+ Multi-Core DSP Platform for Communications InfrastructureSanjive Agarwala, Arjun Rajagopal, Anthony M. Hill, Mayur Joshi, Steven Mullinnix, Timothy Anderson, Raguram Damodaran, Lewis Nardini, Paul Wiley, Peter Groves, John Apostol, Michael Gill, Jose Flores, Abhijeet Chachad, Alan Hales, Kai Chirca, Krishna Panda, Rama Venkatasubramanian, Patrick Eyres, Rajasekhar Velamuri, Anand Rajaram, Manjeri Krishnan, Jonathan Nelson, Jose Frade, Mujibur Rahman, Nuruddin Mahmood, Usha Narasimha, Snehamay Sinha, Sridhar Krishnan, William Webster, Duc Bui, Shriram Moharil, Neil Common, Rejitha Nair, Rajesh Ramanujam, Monica Ryan. 262-601 [doi]
- A GSM Baseband Radio in 0.13μm CMOS with Fully Integrated Power-ManagementMarkus Hammes, Christian Kranz, Jens Kissing, Dietolf Seippel, Pierre-Henri Bonnaud, Enrico Pelos. 264-602 [doi]
- An Integrated Draft 802.11n Compliant MIMO Baseband and MAC ProcessorPaul Petrus, Qinfang Sun, Sam Ng, James Cho, Ning Zhang, Don Breslin, Matt Smith, Bill McFarland, Sundar Sankaran, John Thomson, Rich Mosko, Augusta Chen, Tuofu Lu, Yi-Hsiu Wang, Xioaru Zhang, Dave Nakahira, Yixiang Li, Ravi Subramanian, Arun Venkataraman, Prem Kumar, Sudhakar Swaminathan, Jeffrey M. Gilbert, Won-Joon Choi, Huanchun Ye. 266-602 [doi]
- Multimedia and Parrallel Signal ProcessorsMichel Harrand, Liang-Gee Chen. 268-269 [doi]
- XETAL-II: A 107 GOPS, 600mW Massively-Parallel Processor for Video Scene AnalysisAnteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat, Paul Wielage, Sebastien Mouy, Marc J. M. Heijligers. 270-602 [doi]
- A Programmable 512 GOPS Stream Processor for Signal, Image, and Video ProcessingBrucek Khailany, Ted Williams, Jim Lin, Eileen Long, Mark Rygh, DeForest Tovey, William J. Daly. 272-602 [doi]
- A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOSMasayuki Ito, Toshihiro Hattori, Takahiro Irita, Ken Tatezawa, Fumihito Tanaka, Kenji Hirose, Shinichi Yoshioka, Koji Ohno, Reiko Tsuchihashi, Minoru Sakata, Masayuki Yamamoto, Yuji Aral. 274-602 [doi]
- A 36fps SXGA 3D Display Processor with a Programmable 3D Graphics Rendering EngineSeok-Hoon Kim, Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Kyusik Chung, Han Shin Lim, HyunWook Park, Lee-Sup Kim. 276-602 [doi]
- A 52.4mW 3D Graphics Processor with 141Mvertices/s Vertex Shader and 3 Power Domains of Dynamic Voltage and Frequency ScalingByeong-Gyu Nam, Jeabin Lee, Kwanho Kim, Seungjin Lee, Hoi-Jun Yoo. 278-603 [doi]
- A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder ChipHsiu-Cheng Chang, Jia-Wei Chen, Ching-Lung Su, Yao-Chang Yang, Yao Li, Chun-Hao Chang, Ze-Min Chen, Wei-Sen Yang, Chien-Chang Lin, Ching-Wen Chen, Jinn-Shyan Wang, Jiun-In Guo. 280-603 [doi]
- A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video ApplicationsChih-Da Chien, Chien-Chang Lin, Yi-Hung Shih, He-Chun Chen, Chia-Jui Huang, Cheng-Yen Yu, Chih-Liang Chen, Ching-Hwa Cheng, Jiun-In Guo. 282-603 [doi]
- Power Distribution and ManagementAlice Wang, Jos Huisken. 284-285 [doi]
- On-Die Supply-Resonance Suppression Using Band-Limited Active DampingJianping Xu, Peter Hazucha, Mingwei Huang, Paolo A. Aseron, Fabrice Paillet, Gerhard Schrom, James Tschanz, Cangsang Zhao, Vivek De, Tanay Karnik, Greg Taylor. 286-603 [doi]
- Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCsMitsuya Fukazawa, Tetsuro Matsuno, Toshifumi Uemura, Rei Akiyama, Tetsuya Kagemoto, Hiroshi Makino, Hidehiro Takata, Makoto Nagata. 288-603 [doi]
- On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor ApplicationsTomio Sato, Atsuki Inoue, Tetsyoshi Shiota, Tomoko Inoue, Yukihito Kawabe, Tetsutaro Hashimoto, Toshifumi Imamura, Yoshitaka Murasaka, Makoto Nagata, Atsushi Iwata. 290-603 [doi]
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- A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18μm CMOSJinn-Shyan Wang, Jian-Shiun Chen, Yi-Ming Wang, Chingwei Yeh. 294-604 [doi]
- Embedded SoC Resource Manager to Control Temperature and Data BandwidthMakoto Saen, Kenichi Osada, Satoshi Misaka, Tetsuya Yamada, Yoshitaka Tsujimoto, Yuki Kondo, Tatsuya Kamei, Yutaka Yoshida, Ei Nagahama, Yusuke Nitta, Takayasu Ito, Tadashi Kameyama, Naohiko Irie. 296-604 [doi]
- Comparison of Split-Versus Connected-Core Supplies in the POWER6 MicroprocessorNorman James, Phillip Restle, Joshua Friedrich, Bill Huott, Bradley McCredie. 298-604 [doi]
- Analog Techniques and PLLsVadim Gutnik, Stefan Heinen. 300-301 [doi]
- A Wide-Bandwidth 2.4GHz ISM-Band Fractional-N PLL with Adaptive Phase-Noise CancellationAshok Swaminathan, Kevin J. Wang, Ian Galton. 302-604 [doi]
- A 0.65V 2.5GHz Fractional-N Frequency Synthesizer in 90nm CMOSShih-An Yu, Peter R. Kinget. 304-604 [doi]
- A 40-to-800MHz Locking Multi-Phase DLLYoung Sang Kim, Seung-Jin Park, Yong Sub Kim, Dong-Bi Jang, Seh-Woong Jeong, Hong June Park, Jae-Yoon Sim. 306-605 [doi]
- A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS ProcessShaishav Desai, Pradeep Trivedi, Vincent Von Kanael. 308-605 [doi]
- A 1.2mW 0.02mm2 2GHz Current-Controlled PLL Based on a Self-Biased Voltage-to-Current ConverterWooyoung Jung, HyoungChul Choi, ChangWon Jeong, KwiYoung Kim, Wooseok Kim, HaJun Jeon, GyeSoo Koo, Jihyun Kim, JinHo Seo, MyeongLyong Ko, Jaewhui Kim. 310-605 [doi]
- A 1V 18GHz Clock Generator in a 65nm PD-SOI TechnologyFadi H. Gebara, Jeremy D. Schaub, Tuyet Nguyen, Jarom Pena, Ivan Vo, David Boerstler, Kevin J. Nowka. 312-313 [doi]
- A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold TimeDaniël Schinkel, Eisse Mensink, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta. 314-605 [doi]
- A 0.12μm CMOS Comparator Requiring 0.5V at 600MHz and 1.5V at 6GHzBernhard Goll, Horst Zimmermann. 316-605 [doi]
- A 62μA Interface ASIC for a Capacitive 3-Axis Micro-AccelerometerMatti Paavola, Mika Kämäräinen, Jere A. M. Järvinen, Mikko Saukoski, Mika Laiho, Kari Halonen. 318-605 [doi]
- SRAMKevin Zhang, Hiroyuki Yamauchi. 320-321 [doi]
- Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3VJürgen Pille, Chad Adams, Todd Christensen, Scott R. Cottier, Sebastian Ehrenreich, Fumihiro Kono, Daniel Nelson, Osamu Takahashi, Shunsako Tokito, Otto A. Torreiter, Otto Wagner, Dieter F. Wendel. 322-606 [doi]
- A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile ApplicationsY. Wang, H. Ahn, Uddalak Bhattacharya, T. Coan, Fatih Hamzaoglu, W. Hafez, C.-H. Jan, R. Kolar, S. Kulkarni, J. Lin, Y. Ng, I. Post, L. Wel, Y. Zhang, K. Zhang, Mark Bohr. 324-606 [doi]
- A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature VariationsMakoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara. 326-606 [doi]
- A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier RedundancyNaveen Verma, Anantha P. Chandrakasan. 328-606 [doi]
- A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica SchemeTae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim. 330-606 [doi]
- A Sub-200mV 6T SRAM in 0.13μm CMOSBo Zhai, David Blaauw, Dennis Sylvester, Scott Hanson. 332-606 [doi]
- Cellular and Multi-Mode TransceiversTony Montalvo, Aarno Pärssinen. 334-335 [doi]
- Direct-Conversion WCDMA Transmitter with 163dBc/Hz Noise at 190MHz OffsetChristopher Jones, Bernard Tenbroek, Paul Fowers, Christophe Beghein, Jonathan Strange, Federico Beffa, Dimitris Nalbantis. 336-607 [doi]
- A Linear Uplink WCDMA Modulator with 156dBc/Hz Downlink SNRDimitris Papadopoulos, Qiuting Huang. 338-607 [doi]
- A WCDMA Transmitter in 0.13μm CMOS Using Direct-Digital RF ModulatorPetri Eloranta, Pauli Seppinen, Sami Kallioinen, Tuomas Saarela, Aarno Pärssinen. 340-607 [doi]
- A Single-Chip Dual-Band CDMA2000 Transceiver in 0.13μm CMOSJosef Zipper, R. Vazny, L. Maurer, M. Wilhelm, T. Greifeneder, Andreas Holm. 342-607 [doi]
- A Dual-Band CMOS Transceiver for 3G TD-SCDMAZhenbiao Li, Wenhai Ni, Jie Ma, Ming Li, Dequn Ma, Dong Zhao, Jesal Mehta, David Hartman, Xianfeng Wang, Ken K. O, Kai Che. 344-607 [doi]
- A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13μm CMOSJan Craninckx, M. Liu, Dries Hauspie, Vito Giannini, T. Kim, Jaehoon Lee, Mike Libois, D. Debaillie, Charlotte Soens, Andrea Baschirotto, Joris Van Driessche, Liesbet Van der Perre, Peter Vanbekbergen. 346-607 [doi]
- A Polar Loop Transmitter with Digital Interface including a Loop-Bandwidth Calibration SystemYukinori Akamine, Satoshi Tanaka, Manabu Kawabe, Takao Okazaki, Yasuo Shima, Masahiko Yamamoto, Ryoichi Takano, Yasuyuki Kimura. 348-608 [doi]
- A Polynomial-Predistortion Transmitter for WCDMANishiki Mizusawa, Shinichiro Tsuda, Tomoari Itagaki, Kotaro Takagi. 350-608 [doi]
- A 14mW Fractional-N PLL Modulator with an Enhanced Digital Phase Detector and Frequency Switching SchemeMark A. Ferriss, Michael P. Flynn. 352-608 [doi]
- TD: Proximity Data and Power TransmissionChris Van Hoof, Philippe Royannez. 354-355 [doi]
- 3D Capacitive Interconnections with Mono- and Bi-Directional CapabilitiesAlberto Fazzi, Roberto Canegallo, Luca Ciccarelli, Luca Magagni, Federico Natali, Erik Jung, Pier Luigi Rolandi, Roberto Guerrieri. 356-608 [doi]
- A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse ShapingNoriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda. 358-608 [doi]
- An Attachable Wireless Chip Access Interface for Arbitrary Data Rate Using Pulse-Based lnductive-Coupling through LSI PackageHiroki Ishikuro, Toshihiko Sugahara, Tadahiro Kuroda. 360-608 [doi]
- Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic SwitchesMakoto Takamiya, Tsuyoshi Sekitani, Yoshio Miyamoto, Yoshiaki Noguchi, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai. 362-609 [doi]
- A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network ApplicationsJui-Yuan Yu, Ching-Che Chung, Wan-Chun Liao, Chen-Yi Lee. 364-609 [doi]
- A 0.9V 2.6mW Body-Coupled Scalable PHY Transceiver for Body Sensor ApplicationsSeong-Jun Song, Namjun Cho, Sunyoung Kim, Jerald Yoo, Sungdae Choi, Hoi-Jun Yoo. 366-609 [doi]
- Circuit Techniques to Enable 430Gb/s/mm2 Proximity CommunicationDavid Hopkins, Alex Chow, Robert Bosnyak, Bill Coates, Jo C. Ebergen, Scott Fairbanks, Jonathan Gainsley, Ron Ho, Jon K. Lexau, Frankie Liu, Tarik Ono, Justin Schauer, Ivan E. Sutherland, Robert J. Drost. 368-609 [doi]
- SE5 Highlights of IEDM 2006Albert Theuwissen, Ernesto Perea. 370-371 [doi]
- SE6 Secure Digital SystemsDavid Money Harris, Norman J. Rohrer. 372-373 [doi]
- E2 Digital RF Fundamentally a New Technology or Just Marketing Hype?Chris Rudell, Qiuting Huang, Thomas Lee. 374-375 [doi]
- SE7 Implantable and Prosthetic Devices: Life-Changing CircuitsReid Harrison, Ken Wise. 376-377 [doi]
- Sensors and MEMSEuisik Yoon, Farrokh Ayazi. 378-379 [doi]
- A Wireless Strain Sensing Microsystem with External RF Power Source and Two-Channel Data Telemetry CapabilityMichael A. Suster, Jun Guo, Nattapon Chaimanonart, Wen H. Ko, Darrin J. Young. 380-609 [doi]
- A CMOS Single-Chip Electronic Compass with MicrocontrollerChristian Schott, Robert Racz, Samuel Huber, Angelo Manco, Markus Gloor, Nicolas Simonne. 382-609 [doi]
- A 100Hz 5nT/Hz Low-Pass ΔΣ Servo-Controlled Microfluxgate Magnetometer Using Pulsed ExcitationFabrice Gayral, Elisabeth Delevoye, Cyril Condemine, Éric Colinet, Marc Béranger, Fabien Mieyeville, Frédéric Gaffiot. 384-610 [doi]
- A 0.2°/hr Micro-Gyroscope with Automatic CMOS Mode MatchingAjit Sharma, Faisal Zaman, Farrokh Ayazi. 386-610 [doi]
- A 92dB-DR 13mW ΔΣ Modulator for Spaceborn Fluxgate SensorsWerner Magnes, Matthias Oberst, Aris Valavanoglou, Ulrich Reichold, Harald Neubauer, Hans Hauer, Peter Falkner. 388-610 [doi]
- A CMOS 2D Micro-Fluxgate Earth Magnetic Field Sensor with Digital OutputAndrea Baschirotto, Enrico Dallago, Vincenzo Ferragina, Massimo Ferri, Marco Grassi, Piero Malcovati, Marco Marchesi, Enrico Melissano, Marco Morelli, Andrea Rossini, Stefano Ruzza, Pietro Siciliano, Giuseppe Venchi. 390-610 [doi]
- An Integrated Gravimetric FBAR Circuit for Operation in Liquids Using a Flip-Chip Extended 0.13μm CMOS TechnologyM. Augustyniak, W. Weber, Gottfried Beer, Hans Mulatz, L. Elbrecht, H.-J. Timme, Marc Tiebout, Werner Simbürger, Christian Paulus, Björn Eversmann, Doris Schmitt-Landsiedel, Roland Thewes, Ralf Brederlow. 392-610 [doi]
- A 128×2 CMOS Single-Photon Streak Camera with Timing-Preserving Latchless Pipeline ReadoutMaximilian Sergio, Cristiano Niclass, Edoardo Charbon. 394-610 [doi]
- Digital Circuit InnovationsDavid Blaauw, Georgios Konstandinidis. 396-397 [doi]
- A Distributed Critical-Path Timing Monitor for a 65nm High-Performance MicroprocessorAlan Jrake, Robert M. Senger, Harmander Deogun, Gary D. Carpenter, Soraya Ghiasi, Tuyet Nguyen, Norman James, Michael S. Floyd, Vikas Pokala. 398-399 [doi]
- Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test StructureSaibal Mukhopadhyay, Keunwoo Kim, Keith A. Jenkins, Ching-Te Chuang, Kaushik Roy. 400-611 [doi]
- Fine-Grain Redundant Logic Using Defect-Prediction Flip-FlopsToru Nakura, Koichi Nose, Masayuki Mizuno. 402-611 [doi]
- True Random Number Generator with a Metastability-Based Quality ControlCarlos Tokunaga, David Blaauw, Trevor N. Mudge. 404-611 [doi]
- A 1.6pJ/bit 96% Stable Chip-ID Generating Circuit using Process VariationsYing Su, Jeremy Holleman, Brian P. Otis. 406-611 [doi]
- A One-Cycle Lock Time Slew-Rate-Controlled Output DriverYoung-Ho Kwak, Inhwa Jung, Hyung-Dong Lee, Young-Jung Choi, Yogendera Kumar, Chulwoo Kim. 408-611 [doi]
- A Single-Cycle-Access 128-Entry Fully Associative TLB for Multi-Core Multi-Threaded Server-on-a-ChipShashank Shastry, Ajay Bhatia, Sagar Reddy. 410-612 [doi]
- High-Speed and Low-Energy Capacitively-Driven On-Chip WiresRon Ho, Tarik Ono, Frankie Liu, David Hopkins, Alex Chow, Justin Schauer, Robert J. Drost. 412-612 [doi]
- A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnectsEisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta. 414-612 [doi]
- Broadband RF and RadarTom Schiltz, Kari Halonen. 416-417 [doi]
- A Broadband Receive Chain in 65nm CMOSS. Lee, Jos Bergervoet, Harish Kundur Subramaniyan, Domine Leenaerts, Raf Roovers, Remco van de Beek, Gerard Van der Weide. 418-612 [doi]
- A 0.13μm CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB ReceiversAndrea Bevilacqua, Alessio Vallese, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani. 420-612 [doi]
- An ESD-Protected DC-to-6GHz 9.7mW LNA in 90nm Digital CMOSJonathan Borremans, Piet Wambacq, Dimitri Linten. 422-613 [doi]
- A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOSRashad Ramzan, Stefan Andersson, Jerzy Dabrowski, Christer Svensson. 424-613 [doi]
- A 4-Channel UWB Beam-Former in 0.13μm CMOS using a Path-Sharing True-Time-Delay ArchitectureTa-Shun Chu, Jonathan Roderick, Hossein Hashemi. 426-613 [doi]
- Heterodyne Phase Locking: A Technique for High-Frequency DivisionBehzad Razavi. 428-429 [doi]
- A 79GHz SiGe-Bipolar Spread-Spectrum TX for Automotive RadarSaverio Trotta, Herbert Knapp, Donald Dibra, Klaus Aufinger, Thomas Meister, Josef Böck, Werner Simbürger, Arpad L. Scholtz. 430-613 [doi]
- A 75-GHz PLL in 90-nm CMOS TechnologyJri Lee. 432-613 [doi]
- Multi-GB/s TransceiversRobert Payne, Muneo Fukaishi. 434-435 [doi]
- A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock RecoveryMike Harwood, Nirmal Warke, Richard Simpson, Tom Leslie, Ajith Amerasekera, Sean Batty, Derek Colman, Eugenia Carr, Venu Gopinathan, Steve Hubbins, Peter Hunt, Andy Joy, Pulkit Khandelwal, Bob Killips, Thomas Krause, Shaun Lytollis, Andy Pickering, Mark Saxton, David Sebastio, Graeme Swanson, Andre Szczepanek, Terry Ward, Jeff Williams, Richard Williams, Tom Willwerth. 436-591 [doi]
- A 250mW Full-Rate 10Gb/s Transceiver Core in 90nm CMOS Using a Tri-State Binary PD with 100ps Gated Digital OutputTakashi Masuda, Hideyuki Suzuki, Hiroshi Iizuka, Akio Igarashi, Kaneyoshi Takeshita, Takayuki Mogi, Takayuki Shoji, Jeremy Chatwin, Iain Butler, Derek Mellor. 438-614 [doi]
- A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip CommunicationsR. Palmer, John Poulton, William J. Dally, John G. Eyles, Andrew M. Fuller, Trey Greer, Mark Horowitz, M. Kellam, F. Quan, F. Zarkeshvari. 440-614 [doi]
- A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive EqualizerYasuo Hidaka, Weixin Gai, Akira Hattori, Takeshi Horie, Jian Jiang, Kouichi Kanda, Yoichi Koyanagi, Satoshi Matsubara, Hideki Osone. 442-443 [doi]
- A 20Gb/s Broadband Transmitter with Auto-Configuration TechniqueJri Lee, Huaide Wang. 444-614 [doi]
- A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOIChristian Menolfi, Thomas Toifl, Peter Buchmann, Marcel Kossel, Thomas Morf, Jonas Weiss, Martin L. Schmatz. 446-614 [doi]
- Two 10Gb/s/pin Low-Power Interconnect Methods for 3D ICsQun Gu, Zhiwei Xu, Jenwei Ko, Mau-Chung Frank Chang. 448-614 [doi]
- Nyquist ADC TechniquesDieter Draxelmayr, Venu Gopinathan. 450-451 [doi]
- A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage BiasingMasato Yoshioka, Masahiro Kudo, Toshihiko Mori, Sanroku Tsukamoto. 452-614 [doi]
- A 10b 160MS/s 84mW 1V Subranging ADC in 90nm CMOSDan J. Huber, Rodney J. Chandler, Asad A. Abidi. 454-615 [doi]
- A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOSYoung-Deuk Jeon, Seung-Chul Lee, Kwi-Dong Kim, Jong-Kee Kwon, Jongdae Kim. 456-615 [doi]
- A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display ApplicationsSeung-Chul Lee, Young-Deuk Jeon, Kwi-Dong Kim, Jong-Kee Kwon, Jongdae Kim, Jeong-Woong Moon, Woo-Yol Lee. 458-615 [doi]
- A Zero-Crossing-Based 8b 200MS/s Pipelined ADCLane Brooks, Hae-Seung Lee. 460-615 [doi]
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- An 11b 800MS/s Time-Interleaved ADC with Digital Background CalibrationCheng-Chung Hsu, Fong-Ching Huang, Chih-Yung Shih, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee, Behzad Razavi. 464-615 [doi]
- A 50GS/s Distributed T/H Amplifier in 0.18μm SiGe BiCMOSJaesik Lee, Yves Baeyens, Joseph Weiner, Young-Kai Chen. 466-616 [doi]
- A Cryogenic ADC operating Down to 4.2KYbe Creten, Patrick Merken, Willy Sansen, Robert Mertens, Chris Van Hoof. 468-616 [doi]
- Non-Volatile MemoriesHideto Hidaka, Yair Sofer. 470-471 [doi]
- A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read ThroughputKwangJin Lee, Beak-Hyung Cho, Woo-Yeong Cho, Sangbeom Kang, Byung Gil Choi, Hyung-Rok Oh, Changsoo Lee, Hye-Jin Kim, Joon-min Park, Qi Wang, Mu-Hui Park, Yu-Hwan Ro, Joon-Yong Choi, Ki-Sung Kim, Young-Ran Kim, In-Cheol Shin, Ki Won Lim, Ho-Keun Cho, ChangHan Choi, Won-ryul Chung, Du-Eung Kim, Kwang-Suk Yu, Gitae Jeong, Hong-Sik Jeong, Choong-Keun Kwak, Chang-Hyun Kim, Kinam Kim. 472-616 [doi]
- A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write CurrentSatoru Hanzawa, Naoki Kitai, Kenichi Osada, Akira Kotabe, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Masahiro Moniwa, Takayuki Kawahara. 474-616 [doi]
- A 65nm 1Gb 2b/Cell NOR Flash with 2.25MB/s Program Throughput and 400MB/s DDR interfaceCorrado Villa, Daniele Vimercati, Stefan Schippers, Salvatore Polizzi, Andrea Scavuzzo, Maurizio Perroni, Maurizio Gaibotti, Mauro Luigi Sali. 476-616 [doi]
- A 0.13μm 2.125MB 23.5ns Embedded Flash with 2GB/s Read Throughput for Automotive MicrocontrollersChristoph Demi, Maciej Jankowski, Carmen Thalmaier. 478-617 [doi]
- 2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current ReadTakayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young-Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno. 480-617 [doi]
- A 0.05�?0.05mm2 RFID Chip with Easily Scaled-Down ID-MemoryMitsuo Usami, Hisao Tanabe, Akira Sato, Isao Sakama, Yukio Maki, Toshiaki Iwamatsu, Takashi Ipposhi, Yasuo Inoue. 482-483 [doi]
- DRAM and eRAMMartin Brox, Kazuhiko Kajigaya. 484-485 [doi]
- A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense AmplifierJohn Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer. 486-617 [doi]
- A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good DieShigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara. 488-617 [doi]
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- Phase-Tolerant Latency Control for a Combination 512Mb 2.0Gb/s/pin GDDR3 and 2.5Gb/s/pin GDDR4 SDRAMBrian Johnson, Brent Keeth, Feng Lin, Hua Zheng. 494-617 [doi]
- A DLL with Jitter-Reduction Techniques for DRAM InterfacesByung-Guk Kim, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Soo-In Cho. 496-497 [doi]
- Image SensorsJohannes Solhusvik, Hirofumi Sumi. 498-499 [doi]
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- A Per-Pixel Pulse-FM Background Subtraction Circuit with 175ppm Accuracy for Imaging ApplicationsSam Kavusi, Kunal Ghosh, Abbas El Gamal. 504-618 [doi]
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- Analog and Power Management TechniquesDoug Smith, JoAnn Close. 516-517 [doi]
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- A 200mA 93% Peak Efficiency Single-Inductor Dual-Output DC-DC Buck ConverterEdoardo Bonizzoni, Fausto Borghetti, Piero Malcovati, Franco Maloberti, Bernhard Niessen. 526-619 [doi]
- A 3MHz Low-Voltage Buck Converter with Improved Light Load EfficiencyMichael D. Mulligan, Bill Broach, Thomas H. Lee. 528-620 [doi]
- A Voltage Regulator for Subthreshold Logic with Low Sensitivity to Temperature and Process VariationsGiuseppe de Vita, Giuseppe Iannaccone. 530-620 [doi]
- A 3GHz Switching DC-DC Converter Using Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output FilterMehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, Patrick Palmer. 532-620 [doi]
- A Single-Inductor Switching DC-DC Converter with 5 Outputs and Ordered Power-Distributive ControlHanh-Phuc Le, Chang-Seok Chae, Kwang-Chan Lee, Gyu-Hyeong Cho, Se-Won Wang, Gyu-Ha Cho, Sung-Il Kim. 534-620 [doi]
- Building Blocks for High-Speed TransceiversMichael M. Green, Thomas Burger. 536-537 [doi]
- 40Gb/s High-Gain Distributed Amplifiers with Cascaded Gain Stages in 0.18μm CMOSJun-Chau Chien, Liang-Hung Lu. 538-620 [doi]
- A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOSDaeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Choongyeun Cho, Weipeng Li, Daihyun Lim, Robert Trzcinski, Mahender Kumar, Christine Norris, David Ahlgren. 540-620 [doi]
- Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOSDaihyun Lim, Jonghae Kim, Jean-Olivier Plouchart, Choongyeun Cho, Daeik Kim, Robert Trzcinski, Duane S. Boning. 542-621 [doi]
- 40GHz Wide-Locking-Range Regenerative Frequency Divider and Low-Phase-Noise Balanced VCO in 0.18μm CMOSJun-Chau Chien, Liang-Hung Lu. 544-621 [doi]
- A Self-Calibrated On-chip Phase-Noise-Measurement Circuit with -75dBc Single-Tone Sensitivity at 100kHz OffsetWaleed Khalil, Bertan Bakkaloglu, Sayfe Kiaei. 546-621 [doi]
- A 10dB 44GHz Loss-Compensated CMOS Distributed AmplifierKambiz K. Moez, Mohamed I. Elmasry. 548-621 [doi]
- A 10GHz Broadband Amplifier with Bootstrapped 2kV ESD ProtectionWolfgang Soldner, Moon-Jung Kim, Martin Streibl, Harald Gossner, Thomas H. Lee, Doris Schmitt-Landsiedel. 550-551 [doi]
- 45% Power Saving in a 0.25μm BiCMOS 10Gb/s 50Ω-Terminated Packaged Active-Load Laser DriverEmre Ayranci, Kenn Christensen, Pietro Andreani. 552-553 [doi]
- A 240MHz-BW 112dB-DR TIADaniel Micusik, Horst Zimmermann. 554-621 [doi]
- WLAN/BluetoothGeorge Chien, Mototsugu Hamada. 556-557 [doi]
- A Single-Chip Bluetooth EDR Device in 0.13μm CMOSBojko Marholev, M. Pan, Ed Chien, L. Zhang, Rozi Roufoogaran, S. Wu, Iqbal Bhatti, T.-H. Lin, M. Kappes, Shahla Khorram, S. Anand, Alireza Zolfaghari, Jesse Castaneda, C. M. Chien, B. Ibrahim, H. Jensen, H. Kim, Paul Lettieri, S. Mak, J. Lin, Y. C. Wong, R. Lee, M. Syed, Maryam Rofougaran, Ahmadreza Rofougaran. 558-759 [doi]
- A Fully Integrated MIMO Multi-Band Direct-Conversion CMOS Transceiver for WLAN Applications (802.11n)Arya Behzad, K. Carter, Ed Chien, Steve Wu, M. Pan, C. Lee, Tom Li, John C. Leete, Stephen Au, M. Kappes, Zhimin Zhou, Dayo Ojo, L. Zhang, Alireza Zolfaghari, Jesse Castanada, Hooman Darabi, B. Yeung, Reza Rofougaran, Maryam Rofougaran, J. Trachewsky, T. Moorti, R. Gaikwad, A. Bagchi, Jacob Rael, B. Marhoiev. 560-622 [doi]
- An 802.11a/b/g RF Transceiver in an SoCMartin Simon, Peter Laaser, Voicu Filimon, Hans Geltinger, Dirk Friedrich, Yalcin Raman, Robert Weigel. 562-622 [doi]
- A Fully Integrated RF Front-End with Independent RX/TX Matching and +20dBm Output Power for WLAN ApplicationsRichard Chang, David Weber, MeeLan Lee, David Su, Katelijn Vleugels, S. Simon Wong. 564-622 [doi]
- TD: Trends in Wireless SystemsDonhee Ham, Siva Narendra. 566-567 [doi]
- Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low EnergyLiesbet Van der Perre, Bruno Bougard, Jan Craninckx, Wim Dehaene, Lieven Hollevoet, Murali Jayapala, Pol Marchal, M. Miranda, Praveen Raghavan, Thomas Schuster, Piet Wambacq, Francky Catthoor, Peter Vanbekbergen. 568-569 [doi]
- A Low Phase Noise 10GHz Optoelectronic RF Oscillator Implemented Using CMOS PhotonicsCary Gunn, Drew Guckenberger, Thierry Pinguet, Deana Gunn, Danny Eliyahu, Barmak Mansoorian, Daniel A. Van Blerkom, Olli Salminen. 570-622 [doi]
- Advanced MMIC for Passive Millimeter and Submillimeter Wave ImagingWilliam R. Deal, Larry Yujiri, Mansoor Siddiqui, Richard Lai. 572-622 [doi]
- UHF RFCPUs on Flexible and Glass Substrates for Secure RFID SystemsYoshiyuki Kurokawa, Takayuki Ikeda, Masami Endo, Hiroki Dembo, Daisuke Kawae, Takayuki Inoue, Munehiro Kozuma, Daisuke Ohgarane, Satoru Saito, Koji Dairiki, Hidekazu Takahashi, Yutaka Shionoiri, Tomoaki Atsumi, Takeshi Osada, Kei Takahashi, Takanori Matsuzaki, Hiroyuki Takashina, Yoshinari Yamashita, Shunpei Yamazaki. 574-575 [doi]
- A 1V 600μW 2.1GHz Quadrature VCO Using BAW ResonatorsShailesh Rai, Brian P. Otis. 576-623 [doi]
- A 1.8V 165mW Discrete Wavelet Multi-Tone Baseband Receiver for Cognitive Radio ApplicationsKuan-Hung Chen, Tzi-Dar Chiueh. 578-623 [doi]
- A 2GHz 0.25μm SiGe BiCMOS Oscillator with Flip-Chip Mounted BAW ResonatorS. Razafimandimby, Andreia Cathelin, Jerome Lajoinie, Andreas Kaiser, Didier Belot. 580-623 [doi]
- A Passive UHF RFID Transponder for EPC Gen 2 with -14dBm Sensitivity in 0.13μm CMOSRay Barnett, Ganesh K. Balachandran, Steve Lazar, Brad Kramer, George Konnail, Sribhotla Rajasekhar, Vladimir Drobny. 582-623 [doi]
- Analog, Mixed-Signal, and RF Circuit Design in Nanometer CMOSIan Galton, Matt Miller, Robert Bogdan Staszewski, Bram Nauta, Michel Steyaert. 635-636 [doi]