Yatin Hoskote - researchr alias

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Viewing Publication 1 - 15 from 15

2018

2015

2014

High level design for wearables and IoTYatin Hoskote, Ilya Klotchkov. iccad 2014: 72 [doi]

Edit distance based instruction merging technique to improve flexibility of custom instructions toward flexible accelerator designHui Huang, Taemin Kim, Yatin Hoskote. aspdac 2014: 219-224 [doi]

Automatic generation of custom SIMD instructions for Superword Level ParallelismTaemin Kim, Yatin Hoskote. date 2014: 1-6 [doi]

2013

Keynote talk II: Designing tomorrow's chipsYatin Hoskote. memocode 2013: 75-76 [doi]

2012

A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-ChipPraveen Salihundam, Mohammed Asadullah Khan, Shailendra Jain, Yatin Hoskote, Satish Yada, Shasi Kumar, Vasantha Erraguntla, Sriram R. Vangal, Nitin Borkar. vlsid 2012: 292-297 [doi]

2011

A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOSPraveen Salihundam, Shailendra Jain, Tiju Jacob, Shasi Kumar, Vasantha Erraguntla, Yatin Hoskote, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar. jssc, 46(4):757-766, 2011. [doi]

2010

2008

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOSSriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James Tschanz, David Finan, Arvind Singh, Tiju Jacob, Shailendra Jain, Vasantha Erraguntla, Clark Roberts, Yatin Hoskote, Nitin Borkar, Shekhar Borkar. jssc, 43(1):29-41, 2008. [doi]

2007

A 5-GHz Mesh Interconnect for a Teraflops ProcessorYatin Hoskote, Sriram Vangal, Arvind Singh, Nitin Borkar, Shekhar Borkar. micro, 27(5):51-61, 2007. [doi]

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOSSriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James Tschanz, David Finan, Priya Iyer, Arvind Singh, Tiju Jacob, Shailendra Jain, Sriram Venkataraman, Yatin Hoskote, Nitin Borkar. isscc 2007: 98-589 [doi]

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